Hello Nick,
[ ... ]
+case TOD_TX_TTYPE_CTRL_REG:
+if (val & PPC_BIT(35)) { /* SCOM addressing */
+uint32_t addr = val >> 32;
+uint32_t reg = addr & 0xfff;
+PnvCore *pc;
+
+if (reg != PC_TOD) {
+qemu_log_mask(LOG_GUEST_E
Hi David,
>
> On 13.06.23 10:26, Kasireddy, Vivek wrote:
> > Hi David,
> >
> >>
> >> On 12.06.23 09:10, Kasireddy, Vivek wrote:
> >>> Hi Mike,
> >>
> >> Hi Vivek,
> >>
> >>>
> >>> Sorry for the late reply; I just got back from vacation.
> >>> If it is unsafe to directly use the subpages of a huge
W dniu 7.06.2023 o 04:33, Yuquan Wang pisze:
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses system bus XHCI to provide a usb controller with
64-bit DMA capablity instead of EHCI.
Signed-off-by: Yuqu
On 6/4/23 01:36, Nicholas Piggin wrote:
TFMR is the Time Facility Management Register which is specific to POWER
CPUs, and used for the purpose of timebase management (generally by
firmware, not the OS).
This adds an initial simple TFMR register, which will form part of the
core timebase facilit
On 6/14/23 07:14, Nicholas Piggin wrote:
On Tue Jun 6, 2023 at 11:59 PM AEST, Cédric Le Goater wrote:
On 6/4/23 01:36, Nicholas Piggin wrote:
This adds support for chiptod and core timebase state machine models in
the powernv POWER9 and POWER10 models.
This does not actually change the time or
On 6/4/23 01:36, Nicholas Piggin wrote:
This implements the core timebase state machine, which is the core side
of the time-of-day system in POWER processors. This facility is operated
by control fields in the TFMR register, which also contains status
fields.
The core timebase interacts with the
On 6/12/23 08:10, Christoph Muellner wrote:
From: Christoph Müllner
This patch moves the extension test functions that are used
to gate vendor extension decoders, into cpu_cfg.h.
This allows to reuse them in the disassembler.
This patch does not introduce new functionality.
However, the pat
On 6/12/23 08:10, Christoph Muellner wrote:
From: Christoph Müllner
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei
Acked-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Reviewed-by: Daniel Henrique Barboza
disas/meson.buil
On 01.06.23 14:14, David Hildenbrand wrote:
Working on adding multi-memslot support for virtio-mem (teaching memory
device code about memory devices that can consume multiple memslots), I
have some preparatory cleanups in my queue that make sense independent of
the actual memory-device/virtio-mem
Hi,
On 6/12/23 03:50, Yong-Xuan Wang wrote:
Hi Daniel,
I think this checking can be removed too. Would you send a patch to
fix it? Or I can remove it in this patch.
Please go ahead and fix it on this patch. Thanks,
Daniel
Regards,
Yong-Xuan
On Tue, Jun 6, 2023 at 2:45 AM Daniel Henrique
On 6/14/23 00:25, Weiwei Li wrote:
As specified in privilege spec:"When MPRV=1, load and store memory
addresses are treated as though the current XLEN were set to MPP’s
XLEN". So the xlen for address may be different from current xlen.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
-
On 6/14/23 00:25, Weiwei Li wrote:
Pointer mask is also affected by MPRV which means cur_pmbase/pmmask
should also take MPRV into consideration. As pointer mask for instruction
is not supported currently, so we can directly update cur_pmbase/pmmask
based on address related mode and xlen affect
>-Original Message-
>From: Duan, Zhenzhong
>Sent: Friday, June 9, 2023 12:02 PM
>To: Peter Xu
>Cc: qemu-devel@nongnu.org; m...@redhat.com; jasow...@redhat.com;
>pbonz...@redhat.com; richard.hender...@linaro.org; edua...@habkost.net;
>marcel.apfelb...@gmail.com; alex.william...@redhat.com;
>-Original Message-
>From: Peter Xu
>Sent: Saturday, June 10, 2023 5:26 AM
>Subject: Re: [PATCH v3 5/5] intel_iommu: Optimize out some unnecessary
>UNMAP calls
>
>On Fri, Jun 09, 2023 at 05:49:06AM +, Duan, Zhenzhong wrote:
>> Seems vtd_page_walk_one() already works in above way, chec
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index cd33a1dcdd..26b284bcec 100644
--
Hi,
this patch series is in response to the tickets [1] [2], which point out missing
instructions from ISA v1.6.2. This is the first series that implements the low
hanging fruits.
Cheers,
Bastian
v1 -> v2:
- Shuffle now uses shifts, instead of a buffer
- Shuffle now does rev8 for all byt
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 14 --
target/tricore/tricore-opcodes.h | 9 -
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
inde
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 11 ++-
target/tricore/tricore-opcodes.h |
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a4c60e8ae2..f01000efd4 100644
--- a/targe
we also introduce the tc37x CPU that implements that ISA version.
Acked-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.c | 13 +
target/tricore/cpu.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
i
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 3 ++-
target/tricore/op_helper.c | 10 +-
target/tricore/translate.c | 12 ++--
target/tricore/tricore-opcodes.h | 3 ++-
4 files changed, 23 insertions(+), 5 de
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 8
target/tricore/translate.c | 7 +++
target/tricore/tricore-opcodes.h | 1 +
4 files changed, 17 insertions(+)
diff --git a/target
this is based on code by volumit (https://github.com/volumit/qemu/)
Signed-off-by: Bastian Koppelmann
---
target/tricore/helper.h | 1 +
target/tricore/op_helper.c | 36
target/tricore/translate.c | 8 +++
target/tricore/tricore-opcodes
On Wed, 14 Jun 2023, Nicholas Piggin wrote:
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
Most exceptions are raised with nip pointing to the faulting
instruction but the sc instruction generating a syscall exception
leaves nip pointing to next instruction. Fix gen_sc to not use
gen
On Wed, 14 Jun 2023, Nicholas Piggin wrote:
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Some changes are a m
On Wed, 14 Jun 2023, Nicholas Piggin wrote:
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
Use the env_cpu function to get the CPUState for cpu_abort. These are
only needed in case of fatal errors so this allows to avoid casting
and storing CPUState in a local variable wnen not neede
Marcelo Tosatti writes:
> A regression has been detected in latency testing of KVM guests.
> More specifically, it was observed that the cyclictest
> numbers inside of an isolated vcpu (running on isolated pcpu) are:
>
> # Max Latencies: 00090 00096 00141
>
> Where a maximum of 50us is acceptable
On Fri Jun 9, 2023 at 5:05 PM AEST, Harsh Prateek Bora wrote:
> Since we have the spapr_exit_nested routine that gets executed during
> return path which contains the below change, I think mentioning
> spapr_exit_nested in the title may be more specific/appropriate.
It's the H_ENTER_NESTED call
On Fri Jun 9, 2023 at 5:09 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/8/23 14:43, Nicholas Piggin wrote:
> > Rather than use a copy of CPUPPCState to store the host state while
> > the environment has been switched to the L2, use a new struct for
> > this purpose.
> >
> > Have helper functions
On Fri Jun 9, 2023 at 6:00 PM AEST, Harsh Prateek Bora wrote:
>
>
> On 6/8/23 14:43, Nicholas Piggin wrote:
> > Arguably this is just shuffling around register accesses, but one nice
> > thing it does is allow the exit to save away the L2 state then switch
> > the environment to the L1 before copyi
On 6/14/23 12:00, Bastian Koppelmann wrote:
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1452
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
This commit addresses a bug in the AVR interrupt handling code.
The modification involves replacing the usage of the ctz32 function
with ctz64 to ensure proper handling of interrupts above 33 in the AVR
target.
Previously, timers 3, 4, and 5 interrupts were not functioning correctly
because most o
On 6/14/23 12:00, Bastian Koppelmann wrote:
this variant saves the 'IE' bit to a 'd' register. The 'IE' bitfield
changed from ISA version 1.6.1, so we add icr_ie_offset to DisasContext
as with the other DISABLE insn.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 11 +
github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230614
for you to fetch changes up to 860029321d9ebdff47e89561de61e9441fead70a:
hw/intc: If mmsiaddrcfgh.L == 1, smsiaddrcfg and smsiaddrcfgh are read-only.
(2023-06-14 10:04:30 +1000)
Is anything there worth to apply to -stable?
I p
On 14/6/23 16:07, Lucas Dietrich wrote:
This commit addresses a bug in the AVR interrupt handling code.
The modification involves replacing the usage of the ctz32 function
with ctz64 to ensure proper handling of interrupts above 33 in the AVR
target.
Previously, timers 3, 4, and 5 interrupts wer
On 1/6/23 14:14, David Hildenbrand wrote:
Let's move memory_device_check_addable() and basic checks out of
memory_device_get_free_addr() directly into memory_device_pre_plug().
Separating basic checks from address assignment is cleaner and
prepares for further changes.
As all memory device user
Reviewed-by: Michael Rolnik
On Wed, Jun 14, 2023 at 3:22 PM Philippe Mathieu-Daudé
wrote:
> On 14/6/23 16:07, Lucas Dietrich wrote:
> > This commit addresses a bug in the AVR interrupt handling code.
> > The modification involves replacing the usage of the ctz32 function
> > with ctz64 to ensur
PCIE root ports only allow one device on slot 0/function 0. When hotplugging a
device on a pcie root port, make sure that the device address passed is
always 0x00 that represents slot 0 and function 0. Any other slot value and
function value would be illegal on a root port.
CC: jus...@redhat.com
C
On 6/12/23 17:05, Alex Williamson wrote:
On Mon, 12 Jun 2023 16:07:33 +0200
Cédric Le Goater wrote:
On 6/8/23 20:05, Alex Williamson wrote:
NVIDIA Turing and newer GPUs implement the MSI-X capability at the offset
previously reserved for use by hypervisors to implement the GPUDirect
Cliques c
On 14/6/23 06:55, Richard Henderson wrote:
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/tcg/translate.c
@@ -37,6 +37,11 @@
#include "exec/helper-gen.h.inc"
#undef HELPER_H
+#define HELPER_H "tcg/helper-m.h.inc"
+#include "exec/helper-proto.h.inc"
+#include "exec/helper-g
On 14/6/23 07:03, Richard Henderson wrote:
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/tcg/vec_helper.c
@@ -19,12 +19,15 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/helper-proto.h"
#include "tcg/tcg-gvec-desc.h"
#include "fpu/softfloat.h"
#include "
On 14/6/23 07:01, Richard Henderson wrote:
On 6/11/23 10:58, Philippe Mathieu-Daudé wrote:
+++ b/target/arm/helper.c
@@ -26,6 +26,11 @@
#include "qapi/error.h"
#include "qemu/guest-random.h"
#ifdef CONFIG_TCG
+
+#define HELPER_H "helper.h"
+#include "exec/helper-gen.h.inc"
+#undef HELPER_
On Wed, Jun 14, 2023 at 09:38:41AM +, Duan, Zhenzhong wrote:
> It looks the benefit of this patch is negligible for legacy container and
> iommufd.
> I'd like to drop this patch as it makes no difference, your opinion?
Thanks for the test results. Sounds good here.
--
Peter Xu
Hi all,
I am working on improving nRF51 emulation. Specifically I want to implement the
special "System OFF" mode. System OFF is a power saving mode. In this mode, the
system can only be woken up by a reset or a handful of peripherals (most
notably, GPIO via high/low level detection on configur
The previous code checks whether the highest 16 bits of virtual address
equal to that of CSR.DMW0-3. This is incorrect according to the spec,
and is corrected to compare only the highest four bits instead.
Signed-off-by: Jiajie Chen
---
target/loongarch/tlb_helper.c | 4 ++--
1 file changed, 2 i
On Wed, 14 Jun 2023 18:01:50 +0530
Ani Sinha wrote:
> PCIE root ports only allow one device on slot 0/function 0. When hotplugging a
> device on a pcie root port, make sure that the device address passed is
> always 0x00 that represents slot 0 and function 0. Any other slot value and
> function v
This patch fixes the problem that vhost_net_start_one() doesn't cancel
the device startup and returns 0 even if the device's ack is VIRTIO_NET_ERR
in net->nc->info->load().
Note that this problem also exists in
patch "vdpa: Add vhost_vdpa_net_load_offloads()" at [1].
Because this patch has not bee
According to VirtIO standard, "The class, command and
command-specific-data are set by the driver,
and the device sets the ack byte.
There is little it can do except issue a diagnostic
if ack is not VIRTIO_NET_OK."
Therefore, QEMU should stop sending the queued SVQ commands and
cancel the device s
On 6/1/23 14:14, David Hildenbrand wrote:
Let's use our new helper and stop always allocating ms->device_memory.
There is no difference in common memory-device code anymore between
ms->device_memory being NULL or the size being 0. So we only have to
teach spapr code that ms->device_memory isn't a
On 6/14/23 14:50, Philippe Mathieu-Daudé wrote:
We get:
../../target/arm/tcg/vec_helper.c:268:6: error: no previous prototype for function
'helper_gvec_qrdmlah_s16' [-Werror,-Wmissing-prototypes]
../../target/arm/tcg/vec_helper.c:293:6: error: no previous prototype for function
'helper_gvec_qr
On Tue, Jun 13, 2023 at 06:02:05PM +0200, Juan Quintela wrote:
> Peter Xu wrote:
> > On Tue, May 30, 2023 at 08:39:25PM +0200, Juan Quintela wrote:
> >> Remove the increase in qemu_file_fill_buffer() and add asserts to
> >> qemu_file_transferred* functions.
> >>
> >> Signed-off-by: Juan Quintela
On Wed, Jun 14, 2023 at 06:01:50PM +0530, Ani Sinha wrote:
> PCIE root ports only allow one device on slot 0/function 0.
Why do you say this? PCI devices can be multifunction.
> When hotplugging a
> device on a pcie root port, make sure that the device address passed is
> always 0x00 that repres
On 02/02/2023 12:08, Fiona Ebner wrote:
Hi,
over the years we've got 1-2 dozen reports[0] about suddenly
missing/corrupted MBR/partition tables. The issue seems to be very rare
and there was no success in trying to reproduce it yet. I'm asking here
in the hope that somebody has seen something sim
On Tue, May 30, 2023 at 08:39:27PM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> migration/qemu-file.c | 4
> 1 file changed, 4 deletions(-)
>
> diff --git a/migration/qemu-file.c b/migration/qemu-file.c
> index eb0497e532..6b6deea19b 100644
> --- a/migration/qemu-file.
On Wed, 14 Jun 2023 14:37:08 +0200
Cédric Le Goater wrote:
> On 6/12/23 17:05, Alex Williamson wrote:
> > On Mon, 12 Jun 2023 16:07:33 +0200
> > Cédric Le Goater wrote:
> >
> >> On 6/8/23 20:05, Alex Williamson wrote:
> >>> NVIDIA Turing and newer GPUs implement the MSI-X capability at the
On Tue, May 30, 2023 at 08:39:37PM +0200, Juan Quintela wrote:
> This is how everything else in QEMUFile is structured.
> As a bonus they are three less lines of code.
>
> Signed-off-by: Juan Quintela
> ---
> migration/rdma.c | 35 ---
> 1 file changed, 16 inserti
Peter Xu writes:
> On Mon, Jun 12, 2023 at 03:39:34PM -0400, Steven Sistare wrote:
>> On 6/12/2023 2:44 PM, Peter Xu wrote:
>> > Hi, Steve,
>> >
>> > On Wed, Jun 07, 2023 at 11:38:59AM -0700, Steve Sistare wrote:
>> >> Extend the migration URI to support file:. This can be used for
>> >> any mi
On Wed, Jun 14, 2023 at 12:47:41PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Jun 12, 2023 at 03:39:34PM -0400, Steven Sistare wrote:
> >> On 6/12/2023 2:44 PM, Peter Xu wrote:
> >> > Hi, Steve,
> >> >
> >> > On Wed, Jun 07, 2023 at 11:38:59AM -0700, Steve Sistare wrote:
> >> >
On Tue, May 30, 2023 at 08:39:39PM +0200, Juan Quintela wrote:
> It is not used outside of qemu_file, and it shouldn't.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Tue, May 30, 2023 at 08:39:40PM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Tue, May 30, 2023 at 08:39:41PM +0200, Juan Quintela wrote:
> It was not used outside of qemu_file.c anyways.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
> On 14-Jun-2023, at 7:52 PM, Michael S. Tsirkin wrote:
>
> On Wed, Jun 14, 2023 at 06:01:50PM +0530, Ani Sinha wrote:
>> PCIE root ports only allow one device on slot 0/function 0.
>
>
> Why do you say this? PCI devices can be multifunction.
Yeah you are right, the language needs correctio
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 41 +-
1 file changed, 32 insertions(+), 9 deletions(-)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index a0644dd120..edbc319fa1 100644
--- a/target/tricore/translate.c
Signed-off-by: Bastian Koppelmann
---
target/tricore/cpu.h | 17 -
target/tricore/translate.c | 15 +--
2 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 041fc0b6e5..257fcf3cee 100644
--- a/target/t
the CPU can change the privilege level by writing the corresponding bits
in PSW. If this happens all instructions after this 'mtcr' in the TB are
translated with the wrong privilege level. So we have to exit to the
cpu_loop() and start translating again with the new privilege level.
Signed-off-by:
Hi,
this patch series tries to properly implement privilege levels for the TriCore,
as discussed in
https://lore.kernel.org/qemu-devel/20230118090319.32n4uto7ogy3gfr6@schnipp.zuhause/.
While implementing privilege traps for the SV/UM1 only insns, I saw that
the RESTORE insn uses the wrong ICR.IE
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/tricore/tr
> On 14-Jun-2023, at 6:31 PM, Igor Mammedov wrote:
>
> On Wed, 14 Jun 2023 18:01:50 +0530
> Ani Sinha wrote:
>
>> PCIE root ports only allow one device on slot 0/function 0. When hotplugging
>> a
>> device on a pcie root port, make sure that the device address passed is
>> always 0x00 that
Peter Xu writes:
> On Wed, Jun 14, 2023 at 12:47:41PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Mon, Jun 12, 2023 at 03:39:34PM -0400, Steven Sistare wrote:
>> >> On 6/12/2023 2:44 PM, Peter Xu wrote:
>> >> > Hi, Steve,
>> >> >
>> >> > On Wed, Jun 07, 2023 at 11:38:59AM -0700,
On Wed, Jun 14, 2023 at 02:59:54PM -0300, Fabiano Rosas wrote:
> In this message Daniel mentions virDomainSnapshotXXX which would benefit
> from using the same "file" migration, but being done live:
>
> https://lore.kernel.org/r/zd7mrgq+4qsdb...@redhat.com
>
> And from your response here:
> http
On Mon, 5 Jun 2023, BALATON Zoltan wrote:
We don't emulate the gigabit ethernet part of the chip but the MorphOS
driver accesses these and expects to get some valid looking result
otherwise it hangs. Add some minimal dummy implementation to avoid rhis.
Signed-off-by: BALATON Zoltan
---
This is
On Wed, Jun 14, 2023 at 10:31:40PM +0530, Ani Sinha wrote:
>
>
> > On 14-Jun-2023, at 6:31 PM, Igor Mammedov wrote:
> >
> > On Wed, 14 Jun 2023 18:01:50 +0530
> > Ani Sinha wrote:
> >
> >> PCIE root ports only allow one device on slot 0/function 0. When
> >> hotplugging a
> >> device on a pc
On Wed, Jun 14, 2023 at 10:09:35PM +0530, Ani Sinha wrote:
>
>
> > On 14-Jun-2023, at 7:52 PM, Michael S. Tsirkin wrote:
> >
> > On Wed, Jun 14, 2023 at 06:01:50PM +0530, Ani Sinha wrote:
> >> PCIE root ports only allow one device on slot 0/function 0.
> >
> >
> > Why do you say this? PCI dev
On Wed, 14 Jun 2023, Nicholas Piggin wrote:
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
Most exceptions are raised with nip pointing to the faulting
instruction but the sc instruction generating a syscall exception
leaves nip pointing to next instruction. Fix gen_sc to not use
gen
On Wed, 14 Jun 2023, Nicholas Piggin wrote:
On Mon Jun 12, 2023 at 8:42 AM AEST, BALATON Zoltan wrote:
After previous changes the hypercall handling in 7xx and 74xx
exception handlers can be folded into one if statement to simpilfy
this code.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_
After previous changes the hypercall handling in 7xx and 74xx
exception handlers can be folded into one if statement to simpilfy
this code.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/
Use the env_cpu function to get the CPUState for cpu_abort. These are
only needed in case of fatal errors so this allows to avoid casting
and storing CPUState in a local variable wnen not needed.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 118 +--
Improve readability by shortening some long comments, removing
comments that state the obvious and dropping some empty lines so they
don't distract when reading the code.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/excp_helper.c | 180
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
the unused define as well.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Nicholas Piggin
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/ppc/translate.c b/t
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 114 +--
1 file changed, 25 insertions(+), 89 deletions(-)
diff --git a/target/
Most exceptions are raised with nip pointing to the faulting
instruction but the sc instruction generating a syscall exception
leaves nip pointing to next instruction. Fix gen_sc to not use
gen_exception_err() which sets nip back but correctly set nip to
pc_next so we don't have to patch this in th
Changing the parameter of cpu_interrupt_exittb() from CPUState to env
allows removing some more local CPUState variables in callers.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 9 +++--
target/ppc/helper_regs.c | 15 ++-
target/ppc/helper_regs.h | 2 +-
3 files
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 12d8a7257b..8298217e78 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc
CPUState is rarely needed by this function (only for logging a fatal
error) and it's easy to get from the env parameter so passing it
separately is not necessary.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 9 -
1 file changed, 4 insertions(+),
These are some small clean ups for target/ppc/excp_helper.c trying to
make this code a bit simpler. No functional change is intended.
v2: Patch 3 changes according to review, added tags
Regards,
BALATON Zoltan
BALATON Zoltan (10):
target/ppc: Remove some superfluous parentheses
target/ppc: R
We can get CPUState from env with env_cpu without going through
PowerPCCPU and casting that.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 66
This series of patches provides the ability to retrieve eBPF program
through qmp, so management application may load bpf blob with proper
capabilities.
Now, virtio-net devices can accept eBPF programs and maps through properties
as external file descriptors. Access to the eBPF map is direct throug
Added command "request-ebpf". This command returns
eBPF program encoded base64. The program taken from the
skeleton and essentially is an ELF object that can be
loaded in the future with libbpf.
Signed-off-by: Andrew Melnychenko
---
qapi/ebpf.json| 55
Updated section name, so libbpf should init/gues proper
program type without specifications during open/load.
Signed-off-by: Andrew Melnychenko
---
ebpf/rss.bpf.skeleton.h | 1469 ---
tools/ebpf/rss.bpf.c|2 +-
2 files changed, 741 insertions(+), 730 d
Now, the binary objects may be retrieved by id.
It would require for future qmp commands that may require specific
eBPF blob.
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf.c | 70
ebpf/ebpf.h | 31 +
ebpf/ebpf_rss.c
Changed eBPF map updates through mmaped array.
Mmaped arrays provide direct access to map data.
It should omit using bpf_map_update_elem() call,
which may require capabilities that are not present.
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss.c | 117 ++
eBPF RSS program and maps may now be passed during initialization.
Initially was implemented for libvirt to launch qemu without permissions,
and initialized eBPF program through the helper.
Signed-off-by: Andrew Melnychenko
---
hw/net/virtio-net.c| 55 ++--
It allows using file descriptors of eBPF provided
outside of QEMU.
QEMU may be run without capabilities for eBPF and run
RSS program provided by management tool(g.e. libvirt).
Signed-off-by: Andrew Melnychenko
---
ebpf/ebpf_rss-stub.c | 6 ++
ebpf/ebpf_rss.c | 27 ++
This patch set introduces a new ARM and HVF specific machine type
called "vmapple". It mimicks the device model that Apple's proprietary
Virtualization.Framework exposes, but implements it in QEMU.
With this new machine type, you can run macOS guests on Apple Silicon
systems via HVF. To do so, you
In addition to the ISA and PCI variants of pvpanic, let's add an MMIO
platform device that we can use in embedded arm environments.
Signed-off-by: Alexander Graf
---
hw/misc/Kconfig | 4 +++
hw/misc/meson.build | 1 +
hw/misc/pvpanic-mmio.c| 66 +
MacOS unconditionally disables interrupts of the physical timer on boot
and then continues to use the virtual one. We don't really want to support
a full physical timer emulation, so let's just ignore those writes.
Signed-off-by: Alexander Graf
---
target/arm/hvf/hvf.c | 7 +++
1 file change
For PVG we will need more than the current 32 possible memory slots.
Bump the limit to 512 instead.
Signed-off-by: Alexander Graf
---
accel/hvf/hvf-accel-ops.c | 2 +-
include/sysemu/hvf_int.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/hvf/hvf-accel-ops.c b/acc
Recent versions of macOS use clang instead of gcc. The OS_OBJECT_USE_OBJC
define is only necessary when building with gcc. Let's not define it when
building with clang.
With this patch, I can successfully include GCD headers in QEMU when
building with clang.
Signed-off-by: Alexander Graf
---
me
MacOS unconditionally disables interrupts of the physical timer on boot
and then continues to use the virtual one. We don't really want to support
a full physical timer emulation, so let's just ignore those writes.
Signed-off-by: Alexander Graf
---
target/arm/hvf/hvf.c | 7 +++
1 file change
Apple has its own virtio-blk PCI device ID where it deviates from the
official virtio-pci spec slightly: It puts a new "apple type"
field at a static offset in config space and introduces a new discard
command.
This patch adds a new qdev property called "apple-type" to virtio-blk-pci.
When that pr
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