Hi Mike,
Sorry for the late reply; I just got back from vacation.
If it is unsafe to directly use the subpages of a hugetlb page, then reverting
this patch seems like the only option for addressing this issue immediately.
So, this patch is
Acked-by: Vivek Kasireddy
As far as the use-case is conc
On Mon, Jun 12, 2023 at 02:56:33PM +0800, Siqi Chen wrote:
> When translating "imask" instruction of Tricore architecture, QEMU did not
> check whether the register index was out of bounds, resulting in a
> global-buffer-overflow.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698
On 6/12/23 03:44, Wu, Fei wrote:
On 6/7/2023 8:24 PM, Fei Wu wrote:
+void hmp_info_tb(Monitor *mon, const QDict *qdict)
+{
+const int id = qdict_get_int(qdict, "id");
+g_autoptr(GString) buf = g_string_new("");
+
+if (!tcg_enabled()) {
+monitor_printf(mon, "Only available wit
On 2023/6/12 13:40, LIU Zhiwei wrote:
On 2023/6/12 12:35, Weiwei Li wrote:
On 2023/6/12 11:18, LIU Zhiwei wrote:
On 2023/6/12 11:16, Weiwei Li wrote:
On 2023/6/12 11:08, LIU Zhiwei wrote:
On 2023/5/29 20:17, Weiwei Li wrote:
MPV and GVA bits are added by hypervisor extension to mstatu
On 12.06.23 09:10, Kasireddy, Vivek wrote:
Hi Mike,
Hi Vivek,
Sorry for the late reply; I just got back from vacation.
If it is unsafe to directly use the subpages of a hugetlb page, then reverting
this patch seems like the only option for addressing this issue immediately.
So, this patch is
Hello Pierre,
On 4/25/23 18:14, Pierre Morel wrote:
S390x provides two more topology attributes, entitlement and dedication.
Let's add these CPU attributes to the QAPI command query-cpu-fast.
Signed-off-by: Pierre Morel
Reviewed-by: Nina Schoetterl-Glausch
Reviewed-by: Thomas Huth
---
qap
This series incorporates rebased versions of the ISAParallelState patches of
[1] as requested by Mark.
v2:
* Add forgotten SoB tags (Zoltan, Phil)
Changes since [1]:
* Don't export register definitions (Phil)
* Rephrase commit message of second patch (Zoltan)
[1] https://patchew.org/QEMU/2023052
Exporting ParallelState is a precondition for exporing TYPE_ISA_PARALLEL to be
performed in the next patch.
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel.h | 21 +
hw/char/parallel.c | 20
2 files cha
Allows the struct to be embedded directly into device models without additional
allocation.
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
---
include/hw/char/parallel-isa.h | 46 ++
include/hw/char/parallel.h | 2 --
hw/char/parallel-isa.c
Hi Antonio
On Fri, Jun 9, 2023 at 4:08 PM Antonio Caggiano
wrote:
> When OpenGL is enabled, create only the OpenGL context, ignoring the SDL
> renderer as it is unused anyway.
>
> Signed-off-by: Antonio Caggiano
> ---
> v2: There is no need to specify major and minor version if the SDL
> render
When OpenGL is enabled, create only the OpenGL context, ignoring the SDL
renderer as it is unused anyway.
Signed-off-by: Antonio Caggiano
---
ui/sdl2.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/ui/sdl2.c b/ui/sdl2.c
index 9d703200bf..0d91b555e3 10064
When OpenGL is enabled, create only the OpenGL context, ignoring the SDL
renderer as it is unused anyway.
Signed-off-by: Antonio Caggiano
---
v2: There is no need to specify major and minor version if the SDL renderer is
not created. Also, tested on Windows.
v3: Completely messed up the commi
This patch series updates the documentation for
canokey in QEMU.
Kraxel, could you please pass these patches?
I still do not get my gpg key signed.
Hopefully I could meet some QEMU maintainers soon
and then I can send a PULL.
The following patch also needs to be passed.
https://lore.kernel.org/qe
canokey-qemu contains submodules so it needs
recursive cloning
Reported-By: tlaurion
Link: https://github.com/canokeys/canokey-qemu/issues/3
Signed-off-by: Hongren (Zenithal) Zheng
---
docs/system/devices/canokey.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/syste
Putting HYPERV_FEAT_SYNDBG entry under "#ifdef CONFIG_SYNDBG" in
'kvm_hyperv_properties' array is wrong: as HYPERV_FEAT_SYNDBG is not
the highest feature number, the result is an empty (zeroed) entry in
the array (and not a skipped entry!). hyperv_feature_supported() is
designed to check that all C
Hyper-V Gen1 guests are getting stuck on boot when 'hv-passthrough' is
used. While 'hv-passthrough' is a debug only feature, this significantly
limit its usefullness. While debugging the problem, I found that there are
two loosely connected issues:
- 'hv-passthrough' enables 'hv-syndbg' and this is
Windows with Hyper-V role enabled doesn't boot with 'hv-passthrough' when
no debugger is configured, this significantly limits the usefulness of the
feature as there's no support for subtracting Hyper-V features from CPU
flags at this moment (e.g. "-cpu host,hv-passthrough,-hv-syndbg" does not
work
An nRF52 implementation and a new web console was introduced.
The old web console is hosted in a different URL now.
Signed-off-by: Hongren (Zenithal) Zheng
---
docs/system/devices/canokey.rst | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/docs/system/devices/canoke
On Mon, Jun 12, 2023 at 10:39 AM Antonio Caggiano
wrote:
> When OpenGL is enabled, create only the OpenGL context, ignoring the SDL
> renderer as it is unused anyway.
>
> Signed-off-by: Antonio Caggiano
>
Reviewed-by: Marc-André Lureau
> ---
> ui/sdl2.c | 18 +++---
> 1 file cha
Hi
On Mon, Jun 12, 2023 at 4:15 AM Keqian Zhu via
wrote:
> The following points sometimes can reduce much data
> to copy:
> 1. When width matches, we can transfer data with one
> call of iov_to_buf().
> 2. Only the required height need to transfer, not
> whole image.
>
> Signed-off-by: Keqian Zh
Hi
On Thu, Jun 8, 2023 at 4:56 PM Akihiko Odaki
wrote:
> A console does not have a window if the surface is a placeholder and
> the console is not the first one. sdl2 cannot update the texture in
> such a case.
>
> Add a proper check for window existence. Such a check is only necessary
> for the
Am 11. Juni 2023 13:15:58 UTC schrieb BALATON Zoltan :
>On Sun, 11 Jun 2023, Bernhard Beschow wrote:
>> Allows the struct to be embedded directly into device models without
>> additional
>> allocation.
>>
>> Suggested-by: Mark Cave-Ayland
>
>Patches missing SoB, checkpatch should have cought
On 6/12/2023 3:17 PM, Richard Henderson wrote:
> On 6/12/23 03:44, Wu, Fei wrote:
>> On 6/7/2023 8:24 PM, Fei Wu wrote:
>>> +void hmp_info_tb(Monitor *mon, const QDict *qdict)
>>> +{
>>> + const int id = qdict_get_int(qdict, "id");
>>> + g_autoptr(GString) buf = g_string_new("");
>>> +
>>> +
When OpenGL is enabled, create only the OpenGL context, ignoring the SDL
renderer as it is unused anyway.
Signed-off-by: Antonio Caggiano
Reviewed-by: Marc-André Lureau
---
v2: There is no need to specify major and minor version if the SDL renderer is
not created. Also, tested on Windows.
v3
Hi Antonio
On Thu, Jun 8, 2023 at 1:33 PM Antonio Caggiano
wrote:
> Hi Marc-André,
>
> On 07/06/2023 12:21, Marc-André Lureau wrote:
> > Hi Antonio
> >
> > On Wed, Jun 7, 2023 at 1:05 PM Antonio Caggiano <
> quic_acagg...@quicinc.com>
> > wrote:
> >
> >> Add the SDL_WINDOW_ALLOW_HIGHDPI flag whe
On 12/6/23 00:42, BALATON Zoltan wrote:
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 112 ---
1 file changed, 23 insertio
On 12/6/23 00:42, BALATON Zoltan wrote:
Commit 7a3fe174b12d removed usage of POWERPC_SYSCALL_VECTORED, drop
the unused define as well.
Signed-off-by: BALATON Zoltan
---
target/ppc/translate.c | 1 -
1 file changed, 1 deletion(-)
Reviewed-by: Philippe Mathieu-Daudé
On 11/6/23 18:00, Peter Maydell wrote:
In disas_ldst_reg_imm9() we missed one place where a call to
a gen_mte_check* function should now be passed the memop we
have created rather than just being passed the size. Fix this.
Signed-off-by: Peter Maydell
---
target/arm/tcg/translate-a64.c | 2 +-
On 11/6/23 18:00, Peter Maydell wrote:
Convert the insns in the "Barriers" instruction class to
decodetree: CLREX, DSB, DMB, ISB and SB.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-4-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode
On 11/6/23 12:34, Bernhard Beschow wrote:
I440FX realization is currently mixed with PIIX3 creation. Furthermore, it is
common practice to only set properties between a device's qdev_new() and
qdev_realize(). Clean up to resolve both issues.
Since I440FX spawns a PCI bus let's also move the pci_
From: John Högberg
https://gitlab.com/qemu-project/qemu/-/issues/1034
Signed-off-by: John Högberg
---
tests/tcg/aarch64/Makefile.target | 3 +-
tests/tcg/aarch64/icivau.c| 204 ++
2 files changed, 206 insertions(+), 1 deletion(-)
create mode 100644 tests/
The previous version of this got mangled, so I'm re-sending it through
sourcehut as mentioned in the documentation in the hopes that it's
foolproof. Sorry about the extra traffic :-(
When running in user-mode QEMU currently fails to emulate JITs that
use dual-mapped code to get around W^X re
From: John Högberg
Unlike architectures with precise self-modifying code semantics
(e.g. x86) ARM processors do not maintain coherency for instruction
execution and memory, and require the explicit use of cache
management instructions as well as an instruction barrier to make
code updates visible
On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
>
>
> On 2023/5/30 21:18, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > The disassembler needs the available extensions in order
> > to properly decode instructions in case of overlapping
> > encodings (e.g. for vendor extensions).
Hi Lucas
On Thu, Jun 8, 2023 at 9:49 PM Lucas Chollet wrote:
> No functional changes intended.
>
> Signed-off-by: Lucas Chollet
> ---
> hw/i386/vmmouse.c | 95 +++
> 1 file changed, 71 insertions(+), 24 deletions(-)
>
The patch diff isn't great, and
On 2023/6/12 17:47, Christoph Müllner wrote:
On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
On 2023/5/30 21:18, Christoph Muellner wrote:
From: Christoph Müllner
The disassembler needs the available extensions in order
to properly decode instructions in case of overlapping
encodings (e
On Mon, Jun 12, 2023 at 12:01 PM LIU Zhiwei wrote:
>
>
> On 2023/6/12 17:47, Christoph Müllner wrote:
> > On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
> >>
> >> On 2023/5/30 21:18, Christoph Muellner wrote:
> >>> From: Christoph Müllner
> >>>
> >>> The disassembler needs the available exten
On Mon, 12 Jun 2023, Bernhard Beschow wrote:
Am 11. Juni 2023 13:15:58 UTC schrieb BALATON Zoltan :
On Sun, 11 Jun 2023, Bernhard Beschow wrote:
Allows the struct to be embedded directly into device models without additional
allocation.
Suggested-by: Mark Cave-Ayland
Patches missing SoB, ch
On Mon, 12 Jun 2023, Philippe Mathieu-Daudé wrote:
On 12/6/23 00:42, BALATON Zoltan wrote:
All powerpc exception handlers share some code when handling machine
check exceptions. Move this to a common function.
Signed-off-by: BALATON Zoltan
---
target/ppc/excp_helper.c | 112 -
Hi
On Wed, Jun 7, 2023 at 4:55 PM Erico Nunes wrote:
> Implement the frontend side of the get_edid feature in the qemu
> vhost-user-gpu frontend device.
>
> Signed-off-by: Erico Nunes
> ---
> hw/display/vhost-user-gpu.c | 36
> 1 file changed, 36 insertions
Hi
On Wed, Jun 7, 2023 at 4:55 PM Erico Nunes wrote:
> This adds support to the virtio-gpu get_edid command in qemu as the
> frontend as well as the vhost-user-gpu implementation in contrib/.
> So far, qemu has been outputting the following message:
> EDID requested but the backend doesn't sup
> Prcb may be set to 0 for some CPUs if the dump was taken before they
> start. The dump may still contain valuable information for started CPUs
> so don't abandon conversion in such a case.
>
> Signed-off-by: Akihiko Odaki
> ---
> contrib/elf2dmp/main.c | 5 +
> 1 file changed, 5 insertions(+
On 6/7/2023 8:24 PM, Fei Wu wrote:
> v15
> ---
> This is a large change:
> * remove all time related stuffs, including cmd 'info profile'
> * remove the per-TB flag, use global flag instead
> * remove tb_stats pause/filter, but add status
> * remove qemu_log changes, and use monitor_printf
> * use
From: Christoph Müllner
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension support can be added to the disassembler.
Reviewed-by
From: Christoph Müllner
This patch moves the extension test functions that are used
to gate vendor extension decoders, into cpu_cfg.h.
This allows to reuse them in the disassembler.
This patch does not introduce new functionality.
However, the patch includes a small change:
The parameter for the
From: Christoph Müllner
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis
Reviewed-by: LIU Zhiwei
Signed-
On Thu, Jun 8, 2023 at 3:05 PM LIU Zhiwei wrote:
>
>
> On 2023/5/30 21:18, Christoph Muellner wrote:
> > From: Christoph Müllner
> >
> > A previous patch provides a pointer to the RISCVCPUConfig data.
> > Let's use this to add the necessary code for vendor extensions.
> > This patch does not chan
From: LIU Zhiwei
Disassemble function(plugin_disas, target_disas, monitor_disas) will
always call set_disas_info before disassembling instructions.
plugin_disas and target_disas will always be called under a TB, which
has the same XLEN.
We can't ensure that monitor_disas will always be called
From: Christoph Müllner
In order to enable vendor disassembler support, we need to
move types and constants into a header file so that other
compilation units can use them as well.
This patch does not introduce any functional changes.
Reviewed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Sign
From: Christoph Müllner
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
th
From: Christoph Müllner
This series adds vendor extension support to the QEMU disassembler
for RISC-V. The following vendor extensions are covered:
* XThead{Ba,Bb,Bs,Cmo,CondMov,FMemIdx,Fmv,Mac,MemIdx,MemPair,Sync}
* XVentanaCondOps
So far, there have been two attempts to add vendor extension su
From: Christoph Müllner
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei
Acked-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
disas/meson.build | 5 -
disas/riscv-xventana.c | 41 +
di
From: Christoph Müllner
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei
Acked-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
disas/meson.build | 1 +
di
On Tue, Jun 6, 2023 at 7:38 PM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> Can you please rebase on top of Alistair's riscv-to-apply.next and re-send?
Done.
Thanks,
Christoph
>
> Some patches can't be applied cleanly, in particular patch 2, which conflicts
> with Weiwei's "target/riscv: Split RI
Ping?
--
Andreas Schwab, SUSE Labs, sch...@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."
On 11/6/23 12:34, Bernhard Beschow wrote:
The goal is to eliminate i440fx_init() which is a legacy init function. This
neccessitates the memory regions to be properties, like in Q35, which will be
assigned in board code.
Since i440fx needs different PCI devices in Xen mode, and since i440fx shal
On 11/6/23 12:34, Bernhard Beschow wrote:
`PCIHostState` is often referred to as `phb`, own device state usually as `s`.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/i440fx.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
Reviewed-by: Philippe Mathieu
On 11/6/23 12:34, Bernhard Beschow wrote:
i440fx_realize() realizes the PCI device inside the host bridge
(PCII440FXState), but is implemented between i440fx_pcihost_realize() and
i440fx_init() which deal with the host bridge itself (I440FXState). Since we
want to append i440fx_init() to i440fx_p
On 11/6/23 12:34, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/pci-host/i440fx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
:)
Reviewed-by: Philippe Mathieu-Daudé
On 11/6/23 18:00, Peter Maydell wrote:
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
all essentially the same instruction (system register access).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-7-peter.mayd...@linaro.org
-
On 11/6/23 12:34, Bernhard Beschow wrote:
The Q35 PCI host currently sets the PC machine's PCI bus attribute
through global state, thereby assuming the machine to be a PC machine.
The Q35 machine code already holds on to Q35's pci bus attribute, so can
easily set its own property while preserving
On 11/6/23 12:34, Bernhard Beschow wrote:
The Q35 PCI host already has a PCI_HOST_BYPASS_IOMMU property. However, the
host initializes this property itself by accessing global machine state,
thereby assuming it to be a PC machine. Avoid this by having board code
set this property.
Signed-off-by:
On 11/6/23 12:34, Bernhard Beschow wrote:
Introduce the property in anticipation of QOM'ification; Q35 has the same
property.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/i440fx.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
@@ -51,6 +50,7 @@ struct I440FXStat
From: Siqi Chen
When translating "imask" instruction of Tricore architecture, QEMU did not
check whether the register index was out of bounds, resulting in a
global-buffer-overflow.
Reviewed-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1698
Reported-by: Siqi
some insns were not checking if an even index was used to access a 64
bit register. In the worst case that could lead to a buffer overflow as
reported in https://gitlab.com/qemu-project/qemu/-/issues/1698.
Reported-by: Siqi Chen
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c |
We are always taking the TRICORE_FEATURE_13 branch as every CPU has
TRICORE_FEATURE_13.
For CPUs with ISA > 1.3 we have to take the else branch.
We fix this by inverting the condition. We check for
TRICORE_FEATURE_131, which every CPU except TRICORE_FEATURE_13 CPUs
have.
Resolves: https://gitlab
we don't want to save PSW.CDC to the CSA, but PSW.CDE must be saved.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1699
Signed-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/tricore/op_helper.c
Hi,
this series fixes a bunch of TriCore issues on the bugtracker.
Cheers,
Bastian
Bastian Koppelmann (3):
target/tricore: Correctly fix saving PSW.CDE to CSA on call
target/tricore: Add CHECK_REG_PAIR() for insn accessing 64 bit regs
target/tricore: Fix helper_ret() not correctly restorin
On 2023/6/12 18:04, Christoph Müllner wrote:
On Mon, Jun 12, 2023 at 12:01 PM LIU Zhiwei wrote:
On 2023/6/12 17:47, Christoph Müllner wrote:
On Mon, Jun 12, 2023 at 8:25 AM LIU Zhiwei wrote:
On 2023/5/30 21:18, Christoph Muellner wrote:
From: Christoph Müllner
The disassembler needs th
On 2023/6/12 19:10, Christoph Muellner wrote:
From: Christoph Müllner
This patch moves the extension test functions that are used
to gate vendor extension decoders, into cpu_cfg.h.
This allows to reuse them in the disassembler.
This patch does not introduce new functionality.
However, the pa
On 08.06.23 17:17, Eric Blake wrote:
On Thu, Jun 08, 2023 at 08:56:31AM -0500, Eric Blake wrote:
We had a mix of struct declarataions followed by typedefs, and direct
declarations
struct definitions as part of a typedef. Pick a single style. Also
float a couple of opaque typedefs earlier i
ping
- PI_FIRMWARE_*_RATE constsnts were moved to raspberrypi-fw-defs.h
(seems more suitable place for them)
- inclusion of "qemu/osdep.h" has been removed
- year in copyright header has been updated
Signed-off-by: Sergey Kambalin
---
hw/misc/bcm2835_property.c| 120 ++---
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> Makefile| 4 +++
> common-user/native/Makefile.include | 9 ++
> common-user/native/Makefile.target | 22 +
> configure | 50 +
> docs/devel/bu
Am 9. Juni 2023 18:51:16 UTC schrieb Mark Cave-Ayland
:
>This will enable CMD646-specific fields to be added to CMD6464IDEState in
>future.
>
>Signed-off-by: Mark Cave-Ayland
>---
> hw/ide/cmd646.c | 4 +++-
> include/hw/ide/cmd646.h | 38 ++
> 2 file
Hi
On Thu, Jun 8, 2023 at 6:26 AM Jiqian Chen wrote:
> After suspending and resuming guest VM, you will get
> a black screen, and the display can't come back.
>
> This is because when guest did suspending, it called
> into qemu to call virtio_gpu_gl_reset. In function
> virtio_gpu_gl_reset, it d
On 9/6/23 20:51, Mark Cave-Ayland wrote:
This is to allow us to use the cmd646_bmdma_ops name for the CMD646
device-specific registers in the next commit.
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Philippe Mat
On 9/6/23 20:51, Mark Cave-Ayland wrote:
Signed-off-by: Mark Cave-Ayland
---
hw/ide/cmd646.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Hi Lucas,
On 8/6/23 23:03, Adecy wrote:
-- Forwarded message -
De : *Adecy* mailto:ld.ad...@gmail.com>>
Date: jeu. 1 juin 2023 à 21:34
Subject: QEMU AVR Patch - Correct handling of AVR interrupts
To: mailto:qemu-triv...@nongnu.org>>
Hello,
I would like to submit the attached p
On Sun, 11 Jun 2023 12:33:59 +0200
Bernhard Beschow wrote:
> Fixes the following clangd warning (-Winitializer-overrides):
>
> q35.c:297:19: Initializer overrides prior initialization of this subobject
> q35.c:292:19: previous initialization is here
>
> Settle on native endian which causes
Alex Bennée writes:
> Yeqi Fu writes:
>
>> Signed-off-by: Yeqi Fu
>> ---
>> Makefile| 4 +++
>> common-user/native/Makefile.include | 9 ++
>> common-user/native/Makefile.target | 22 +
>> configure | 50 +++
From: "liguang.zhang"
kernel log
```shell
The system is going down NOW!
Sent SIGTERM to all processes
logout
Sent SIGKILL to all processes
Requesting system reboot
```
then no response
for qemu command:
system_reset:
kernel log:
```shell
[ 53.739556] kvm [150]: VCPU exit error -95
[ 53.739
From: "liguang.zhang"
kernel log
```shell
reboot
The system is going down NOW!
Sent SIGTERM to all processes
logout
Sent SIGKILL to all processes
Requesting system reboot
```
then no response
for qemu command:
system_reset:
kernel log:
```shell
[ 53.739556] kvm [150]: VCPU exit error -95
[
From: "liguang.zhang"
There have a issue of guest reboot bug in kvm-mode:
1. in guest shell just run the reboot, guest can't reboot success, and host kvm
stop the vcpu schedual.
2. for smp guest, ctrl+a+c switch to qemu command, use system_reset command to
reset the guest, then vcpu crash
kern
On Fri, May 26, 2023 at 11:50:01AM +, Tejus GK wrote:
> Hi everyone,
>
> This patchset aims to cover code paths in the source code where a
> migration is marked as failed via MIGRATION_STATUS_FAILED, however the
> failure exists outside of migration.c, and without a call for
> migrate_set_e
On Jun 09 13:49, Richard Henderson wrote:
> On 6/9/23 10:23, Aaron Lindsay wrote:
> > --- a/target/arm/hvf/hvf.c
> > +++ b/target/arm/hvf/hvf.c
> > @@ -847,6 +847,7 @@ static bool
> > hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
> > { HV_SYS_REG_ID_AA64DFR1_EL1, &host_isar.id_
On Jun 09 13:51, Richard Henderson wrote:
> On 6/9/23 10:23, Aaron Lindsay wrote:
> > +static inline int isar_feature_pauth_get_features(const ARMISARegisters
> > *id)
> > +{
> > +if (isar_feature_aa64_pauth_arch_qarma5(id)) {
> > +return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, APA)
Manos Pitsidianakis writes:
> On Wed, 07 Jun 2023 19:47, Yeqi Fu wrote:
>>--- a/linux-user/main.c
>>+++ b/linux-user/main.c
>>+/* Set the library for native bypass */
>>+if (native_lib != NULL) {
>>+char *token = malloc(strlen(native_lib) + 12);
>
> malloc() can fail (in rare
On 6/8/23 23:23, Richard Henderson wrote:
Restructure the ifdef ladder, separating 64-bit from 32-bit,
and ensure _CALL_AIX is set for ELF v1. Fixes the build for
ppc64 big-endian host with clang.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
tcg/ppc/tcg-t
On 6/8/23 23:23, Richard Henderson wrote:
This implements the VCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/int_helper.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/ppc/int_helper.
On 6/8/23 23:23, Richard Henderson wrote:
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
host/include/ppc/host/cpuinfo.h | 29
h
On 6/8/23 23:23, Richard Henderson wrote:
This implements the VNCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/int_helper.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/target/ppc/int_helper.c
On 6/8/23 23:23, Richard Henderson wrote:
This implements the VCIPHER instruction.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/int_helper.c | 14 --
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/target/ppc/int_help
On 6/8/23 23:23, Richard Henderson wrote:
This implements the VNCIPHER instruction.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
target/ppc/int_helper.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/ppc/in
Yeqi Fu writes:
> Signed-off-by: Yeqi Fu
> ---
> include/qemu/envlist.h | 1 +
> linux-user/main.c | 23 +
> util/envlist.c | 56 ++
> 3 files changed, 80 insertions(+)
>
> diff --git a/include/qemu/envlist.h b/include/qemu
On 6/8/23 23:24, Richard Henderson wrote:
Detect CRYPTO in cpuinfo; implement the accel hooks.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
host/include/ppc/host/aes-round.h | 181
host/include/ppc/host/cpuinfo.h | 1 +
Hi Paolo
On Wed, May 10, 2023 at 6:05 PM Paolo Bonzini wrote:
> Signed-off-by: Paolo Bonzini
>
patch looks generally good, but does not apply anymore.
Are you planning to update it later to support the more secure "
map_shadow_stack" syscall, if/when it is added?
---
> meson.build
On Sun, 11 Jun 2023 12:34:00 +0200
Bernhard Beschow wrote:
> The Q35 PCI host currently sets the PC machine's PCI bus attribute
> through global state, thereby assuming the machine to be a PC machine.
> The Q35 machine code already holds on to Q35's pci bus attribute, so can
> easily set its own
On Sun, 11 Jun 2023 12:34:01 +0200
Bernhard Beschow wrote:
> Introduce a macro to avoid copy and pasting strings which can easily
> cause typos.
>
> Suggested-by: Michael S. Tsirkin
> Signed-off-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
> ---
> include/hw/pci/pci_host.h | 2 ++
> hw/
On Sun, 11 Jun 2023 12:34:02 +0200
Bernhard Beschow wrote:
> The Q35 PCI host already has a PCI_HOST_BYPASS_IOMMU property. However, the
> host initializes this property itself by accessing global machine state,
> thereby assuming it to be a PC machine. Avoid this by having board code
> set this
On 08.06.23 16:56, Eric Blake wrote:
Upstream NBD now documents[1] an extension that supports 64-bit effect
lengths in requests. As part of that extension, the size of the reply
headers will change in order to permit a 64-bit length in the reply
for symmetry[2]. Additionally, where the reply he
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