[PATCH 21/33] target/mips: Add emulation of MXU S16LDD S16STD S16LDI S16SDI instructions

These instructions are all load/store a halfword from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 117 +++

virtio-blk using a single iothread

Hey Stefan, Paolo, I just had a report from a user experiencing lower virtio-blk performance than he expected. This user is running virtio-blk on top of nvme-tcp device. The guest is running 12 CPU cores. The guest read/write throughput is capped at around 30% of the available throughput from th

[PATCH 20/33] target/mips: Add emulation of MXU S8STD S8LDI S8SDI instructions

These instructions are all load/store a byte from memory and put it into/get it from MXU register in various combinations. I-suffix instructions modify the base address GPR by offset provided. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 74

[PATCH 02/33] Add support of two XBurst CPUs

XBurstR1 - is the MIPS32R1 CPU which aims to cover all Ingenic SoCs older than JZ4770 and some newer. XBurstR2 - is the MIPS32R2 CPU which aims to cover all Ingenic SoCs starting from to JZ4770. Signed-off-by: Siarhei Volkau --- target/mips/cpu-defs.c.inc | 46 +++

[PATCH 03/33] target/mips: Add emulation of LXW LXB LXH LXBU LXHU instructions

These instructions used to load from memory to GPR via indexed address divided by base and index parts in GPR registers. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 83 - 1 file changed, 82 insertions(+), 1 deletion(-) diff --git a/target/

[PATCH 16/33] target/mips: Add emulation of MXU D32ACC D32ACCM D32ASUM instructions

These instructions are all dual 32-bit addition/subtraction in various combinations. The instructions are grouped in pool12, see the opcode organization in the file. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 160 1 file changed, 160 inse

[PATCH 08/33] target/mips: Add emulation of Q8ADD instruction

This instruction is used to add/subtract quadruple 8-bit values to another quadruple in parallel. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 77 + 1 file changed, 77 insertions(+) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips

[PATCH 05/33] target/mips: Add emulation of Q8SLT Q8SLTU instructions

These instructions are used to set bits depending on comparison result in each byte respectively. Signed-off-by: Siarhei Volkau --- target/mips/tcg/mxu_translate.c | 65 + 1 file changed, 65 insertions(+) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips

[PATCH v2 0/5] misc: Enforce .[ch].inc extension for re-included .c/.h files

Since v1: - addressed Richard's easy review comments Richard, this is what I had before looking at removing exec/helper*. Posting in case it is useful enough before getting there. -- Follow the convention to use the .inc extension for .c/.h files re-included, as docummented in Coding Style since

[PATCH v2 3/5] target/arm: Rename helper template headers as '.h.inc'

Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header fil

[PATCH v2 1/5] hw/remote/proxy: Remove dubious 'event_notifier-posix.c' include

event_notifier-posix.c is registered in meson's util_ss[] source set, which is built as libqemuutil.a.p library. Both tools and system emulation binaries are linked with qemuutil, so there is no point in including this source file. Introduced in commit bd36adb8df ("multi-process: create IOHUB obje

[PATCH v2 2/5] tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc

Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header fil

[PATCH v2 4/5] target/i386: Rename helper template headers as '.h.inc'

Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header fil

Re: [PATCH v2 1/5] hw/remote/proxy: Remove dubious 'event_notifier-posix.c' include

On 8/6/23 15:31, Philippe Mathieu-Daudé wrote: event_notifier-posix.c is registered in meson's util_ss[] source set, which is built as libqemuutil.a.p library. Both tools and system emulation binaries are linked with qemuutil, so there is no point in including this source file. Introduced in com

[PATCH v2 5/5] target: Bulk rename 'helper.h' -> 'helper.h.inc' for all targets

Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header fil

Re: [PATCH v2 5/5] target: Bulk rename 'helper.h' -> 'helper.h.inc' for all targets

On 8/6/23 15:31, Philippe Mathieu-Daudé wrote: Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the C

Re: [PATCH 2/8] tiva c usart module implementation

On Wed, 17 May 2023 at 09:13, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > hw/char/tm4c123_usart.c | 381 > hw/char/trace-events| 4 + > include/hw/char/tm4c123_usart.h | 124 +++ Patches that add new device sour

Re: [PATCH 3/8] tiva c gpio implementation

On Wed, 17 May 2023 at 09:14, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > hw/gpio/tm4c123_gpio.c | 372 + > hw/gpio/trace-events | 4 + > include/hw/gpio/tm4c123_gpio.h | 127 +++ > 3 files changed, 503 insertions(

Re: [PATCH] vdpa: dont check vhost_vdpa->suspended when unsupported

On 6/8/2023 6:59 PM, Eugenio Perez Martin wrote: On Thu, Jun 8, 2023 at 11:34 AM Zhu, Lingshan wrote: On 6/8/2023 4:49 PM, Eugenio Perez Martin wrote: On Thu, Jun 8, 2023 at 9:07 AM Zhu, Lingshan wrote: On 6/7/2023 9:51 PM, Eugenio Perez Martin wrote: On Wed, Jun 7, 2023 at 11:09 AM Z

Re: [PATCH v3 2/5] intel_iommu: Fix a potential issue in VFIO dirty page sync

On Thu, Jun 08, 2023 at 05:52:28PM +0800, Zhenzhong Duan wrote: > Peter Xu found a potential issue: > > "The other thing is when I am looking at the new code I found that we > actually extended the replay() to be used also in dirty tracking of vfio, > in vfio_sync_dirty_bitmap(). For that maybe i

Re: [PATCH v3 3/5] intel_iommu: Fix flag check in replay

On Thu, Jun 08, 2023 at 05:52:29PM +0800, Zhenzhong Duan wrote: > Replay doesn't notify registered notifiers but the one passed > to it. So it's meaningless to check the registered notifier's > synthetic flag. > > There is no issue currently as all replay use cases have MAP > flag set, but let's b

[PATCH] build: further refine build.ninja rules

In commit b0fcc6fc7fc1 ("build: rebuild build.ninja using "meson setup --reconfigure"", 2023-05-19) I changed the build.ninja rule in the Makefile to use "meson setup" so that the Makefile would pick up a changed path to the meson binary. However, there was a reason why build.ninja was rebuilt usi

Re: [PATCH v3 4/5] intel_iommu: Fix address space unmap

On Thu, Jun 08, 2023 at 05:52:30PM +0800, Zhenzhong Duan wrote: > During address space unmap, corresponding IOVA tree entries are > also removed. But DMAMap is set beyond notifier's scope by 1, so > in theory there is possibility to remove a continuous entry above > the notifier's scope but falling

[PATCH v4 02/24] nbd: Consistent typedef usage in header

We had a mix of struct declarataions followed by typedefs, and direct struct definitions as part of a typedef. Pick a single style. Also float a couple of opaque typedefs earlier in the file, as a later patch wants to refer NBDExport* in NBDRequest. No semantic impact. Signed-off-by: Eric Blake

[PATCH v4 20/24] nbd/client: Accept 64-bit block status chunks

Once extended mode is enabled, we need to accept 64-bit status replies (even for replies that don't exceed a 32-bit length). It is easier to normalize narrow replies into wide format so that the rest of our code only has to handle one width. Although a server is non-compliant if it sends a 64-bit

[PATCH v4 09/24] nbd: Replace bool structured_reply with mode enum

The upcoming patches for 64-bit extensions requires various points in the protocol to make decisions based on what was negotiated. While we could easily add a 'bool extended_headers' alongside the existing 'bool structured_reply', this does not scale well if more modes are added in the future. Be

[PATCH v4 13/24] nbd/server: Refactor handling of request payload

Upcoming additions to support NBD 64-bit effect lengths allow for the possibility to distinguish between payload length (capped at 32M) and effect length (up to 63 bits). Without that extension, only the NBD_CMD_WRITE request has a payload; but with the extension, it makes sense to allow at least

[PATCH v4 17/24] nbd/server: Enable initial support for extended headers

Time to start supporting clients that request extended headers. Now we can finally reach the code added across several previous patches. Even though the NBD spec has been altered to allow us to accept NBD_CMD_READ larger than the max payload size (provided our response is a hole or broken up over

[PATCH v4 19/24] nbd/client: Initial support for extended headers

Update the client code to be able to send an extended request, and parse an extended header from the server. Note that since we reject any structured reply with a too-large payload, we can always normalize a valid header back into the compact form, so that the caller need not deal with two branche

[PATCH v4 16/24] nbd/server: Support 64-bit block status

The NBD spec states that if the client negotiates extended headers, the server must avoid NBD_REPLY_TYPE_BLOCK_STATUS and instead use NBD_REPLY_TYPE_BLOCK_STATUS_EXT which supports 64-bit lengths, even if the reply does not need more than 32 bits. As of this patch, client->mode is still never NBD_

[PATCH v4 14/24] nbd/server: Prepare to receive extended header requests

Although extended mode is not yet enabled, once we do turn it on, we need to accept extended requests for all messages. Previous patches have already taken care of supporting 64-bit lengths, now we just need to read it off the wire. Note that this implementation will block indefinitely on a buggy

[PATCH v4 00/24] qemu patches for 64-bit NBD extensions

v3 was here: https://lists.gnu.org/archive/html/qemu-devel/2023-05/msg03607.html Since then, I've incorporated lots of feedback from Vladimir: - split several patches into smaller pieces - use an enum to track various negotiation modes - reorder a few patches - several new patches (2, 5, 6) -

[PATCH v4 05/24] nbd: s/handle/cookie/ to match NBD spec

Externally, libnbd exposed the 64-bit opaque marker for each client NBD packet as the "cookie", because it was less confusing when contrasted with 'struct nbd_handle *' holding all libnbd state. It also avoids confusion between the nown 'handle' as a way to identify a packet and the verb 'handle'

[PATCH v4 22/24] nbd/server: Refactor list of negotiated meta contexts

Peform several minor refactorings of how the list of negotiated meta contexts is managed, to make upcoming patches easier: Promote the internal type NBDExportMetaContexts to the public opaque type NBDMetaContexts, and mark exp const. Use a shorter member name in NBDClient. Hoist calls to nbd_chec

[PATCH v4 06/24] nbd/client: Simplify cookie vs. index computation

Our code relies on a sentinel cookie value of zero for deciding when a packet has been handled, as well as relying on array indices between 0 and MAX_NBD_REQUESTS-1 for dereferencing purposes. As long as we can symmetrically convert between two forms, there is no reason to go with the odd choice o

Re: [PATCH 4/8] tiva c sysctl implementation

On Wed, 17 May 2023 at 09:13, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > hw/misc/tm4c123_sysctl.c | 989 +++ > hw/misc/trace-events | 5 + > include/hw/misc/tm4c123_sysctl.h | 307 ++ > 3 files changed, 1301 inserti

[PATCH v4 03/24] nbd/server: Prepare for alternate-size headers

Upstream NBD now documents[1] an extension that supports 64-bit effect lengths in requests. As part of that extension, the size of the reply headers will change in order to permit a 64-bit length in the reply for symmetry[2]. Additionally, where the reply header is currently 16 bytes for simple r

[PATCH v4 07/24] nbd/client: Add safety check on chunk payload length

Our existing use of structured replies either reads into a qiov capped at 32M (NBD_CMD_READ) or caps allocation to 1000 bytes (see NBD_MAX_MALLOC_PAYLOAD in block/nbd.c). But the existing length checks are rather late; if we encounter a buggy (or malicious) server that sends a super-large payload

[PATCH v4 21/24] nbd/client: Request extended headers during negotiation

All the pieces are in place for a client to finally request extended headers. Note that we must not request extended headers when qemu-nbd is used to connect to the kernel module (as nbd.ko does not expect them, but expects us to do the negotiation in userspace before handing the socket over to th

[PATCH v4 18/24] nbd/client: Plumb errp through nbd_receive_replies

Instead of ignoring the low-level error just to refabricate our own message to pass to the caller, we can just plump the caller's errp down to the low level. Signed-off-by: Eric Blake --- v4: new patch [Vladimir] --- block/nbd.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletio

[PATCH v4 23/24] nbd/server: Prepare for per-request filtering of BLOCK_STATUS

The next commit will add support for the optional extension NBD_CMD_FLAG_PAYLOAD during NBD_CMD_BLOCK_STATUS, where the client can request that the server only return a subset of negotiated contexts, rather than all contexts. To make that task easier, this patch populates the list of contexts to r

[PATCH v4 10/24] nbd/client: Pass mode through to nbd_send_request

Once the 64-bit headers extension is enabled, the data layout we send over the wire for a client request depends on the mode negotiated with the server. Rather than adding a parameter to nbd_send_request, we can add a member to struct NBDRequest, since it already does not reflect on-wire format.

[PATCH v4 01/24] nbd/client: Use smarter assert

Assigning strlen() to a uint32_t and then asserting that it isn't too large doesn't catch the case of an input string 4G in length. Thankfully, the incoming strings can never be that large: if the export name or query is reflecting a string the client got from the server, we already guarantee that

[PATCH v4 04/24] nbd/server: Refactor to pass full request around

Part of NBD's 64-bit headers extension involves passing the client's requested offset back as part of the reply header (one reason it stated for this change: converting absolute offsets stored in NBD_REPLY_TYPE_OFFSET_DATA to relative offsets within the buffer is easier if the absolute offset of th

[PATCH v4 08/24] nbd: Use enum for various negotiation modes

Deciphering the hard-coded list of integer return values from nbd_start_negotiate() will only get more confusing when adding support for 64-bit extended headers. Better is to name things in an enum. Although the function in question is private to client.c, putting the enum in a public header and i

[PATCH v4 24/24] nbd/server: Add FLAG_PAYLOAD support to CMD_BLOCK_STATUS

Allow a client to request a subset of negotiated meta contexts. For example, a client may ask to use a single connection to learn about both block status and dirty bitmaps, but where the dirty bitmap queries only need to be performed on a subset of the disk; forcing the server to compute that info

[PATCH v4 11/24] nbd: Add types for extended headers

Add the constants and structs necessary for later patches to start implementing the NBD_OPT_EXTENDED_HEADERS extension in both the client and server, matching recent upstream nbd.git (through commit e6f3b94a934). This patch does not change any existing behavior, but merely sets the stage for upcom

[PATCH v4 12/24] nbd: Prepare for 64-bit request effect lengths

Widen the length field of NBDRequest to 64-bits, although we can assert that all current uses are still under 32 bits, because nothing ever puts us into NBD_MODE_EXTENDED yet. Thus no semantic change. No semantic change yet. Signed-off-by: Eric Blake --- v4: split off enum changes to earlier p

[PATCH v4 15/24] nbd/server: Prepare to send extended header replies

Although extended mode is not yet enabled, once we do turn it on, we need to reply with extended headers to all messages. Update the low level entry points necessary so that all other callers automatically get the right header based on the current mode. Signed-off-by: Eric Blake --- v4: new pat

Re: [PATCH 5/8] tiva c watchdog timers implementation

On Wed, 17 May 2023 at 09:14, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > hw/watchdog/tm4c123_watchdog.c | 297 + > hw/watchdog/trace-events | 3 + > include/hw/watchdog/tm4c123_watchdog.h | 97 > 3 files changed, 39

Re: [PATCH v3 5/5] intel_iommu: Optimize out some unnecessary UNMAP calls

On Thu, Jun 08, 2023 at 05:52:31PM +0800, Zhenzhong Duan wrote: > Commit 63b88968f1 ("intel-iommu: rework the page walk logic") adds logic > to record mapped IOVA ranges so we only need to send MAP or UNMAP when > necessary. But there is still a corner case of unnecessary UNMAP. > > During invalid

Re: [PATCH 7/8] tiva c board documentation

On Wed, 17 May 2023 at 09:13, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > docs/system/arm/tivac.rst | 47 +++ > 1 file changed, 47 insertions(+) > create mode 100644 docs/system/arm/tivac.rst This is missing the line to add this new fil

Re: [PATCH 8/8] adding tiva c to the qemu build system and adding my info to the maintainers list

On Wed, 17 May 2023 at 09:14, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > MAINTAINERS | 9 + > configs/devices/arm-softmmu/default.mak | 1 + > hw/arm/Kconfig | 13 + > hw/arm/meson.build

Re: [PATCH v3 5/5] intel_iommu: Optimize out some unnecessary UNMAP calls

On Thu, Jun 08, 2023 at 10:05:08AM -0400, Peter Xu wrote: > IIUC what VFIO does here is it returns succeed if unmap over nothing rather > than failing like iommufd. Curious (like JasonW) on why that retval? I'd > assume for returning "how much unmapped" we can at least still return 0 for > nothi

Re: [Libguestfs] [PATCH v4 02/24] nbd: Consistent typedef usage in header

On Thu, Jun 08, 2023 at 08:56:31AM -0500, Eric Blake wrote: > We had a mix of struct declarataions followed by typedefs, and direct declarations > struct definitions as part of a typedef. Pick a single style. Also > float a couple of opaque typedefs earlier in the file, as a later > patch wants

Re: [PATCH 6/8] tiva c general purpose timers implementation

On Wed, 17 May 2023 at 09:14, Mohamed ElSayed wrote: > > Signed-off-by: Mohamed ElSayed > --- > hw/timer/tm4c123_gptm.c | 495 > hw/timer/trace-events | 5 + > include/hw/timer/tm4c123_gptm.h | 131 + > 3 files changed, 631 insertions(

Re: [Libguestfs] [PATCH v4 05/24] nbd: s/handle/cookie/ to match NBD spec

On Thu, Jun 08, 2023 at 08:56:34AM -0500, Eric Blake wrote: > Externally, libnbd exposed the 64-bit opaque marker for each client > NBD packet as the "cookie", because it was less confusing when > contrasted with 'struct nbd_handle *' holding all libnbd state. It > also avoids confusion between th

Re: [PATCH 01/15] hw/timer/arm_timer: Declare QOM types using DEFINE_TYPES() macro

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > When multiple QOM types are registered in the same file, > it is simpler to use the the DEFINE_TYPES() macro. Replace > the type_init() / type_register_static() combination. > > Signed-off-by: Philippe Mathieu-Daudé > --- Reviewed-b

Re: [PATCH 02/15] hw/timer/arm_timer: Move SP804 code around

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Move sp804_properties[] and sp804_class_init() around > with the rest of SP804 code code. What follows the > "Integrator/CP timer module." is strictly ICP related. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/timer/arm_timer

Re: [PATCH 11/15] hw/timer/arm_timer: Iterate on timers using for() loop statement

On Wed, 31 May 2023 at 21:37, Philippe Mathieu-Daudé wrote: > > The same pattern is used for each timer, 2 or 3 times. To avoid > too much code churn in the next commits, iterate on the number > of timers using a for() loop statement. > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter

Re: [PATCH 06/15] hw/timer/arm_timer: CamelCase rename arm_timer_state -> ArmTimerState

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Following docs/devel/style.rst guidelines, rename arm_timer_state > as ArmTimerState. Ending the type name with 'State' is also a little old fashioned. But anyway Reviewed-by: Peter Maydell thanks -- PMM

[PATCH] sdl2: Check if window exists before updating it

A console does not have a window if the surface is a placeholder and the console is not the first one. sdl2 cannot update the texture in such a case. Add a proper check for window existence. Such a check is only necessary for the "gl" implementation as the "2d" implementation checks for the textur

Re: [PATCH] vdpa: dont check vhost_vdpa->suspended when unsupported

On Thu, Jun 8, 2023 at 3:38 PM Zhu, Lingshan wrote: > > > > On 6/8/2023 6:59 PM, Eugenio Perez Martin wrote: > > On Thu, Jun 8, 2023 at 11:34 AM Zhu, Lingshan > > wrote: > >> > >> > >> On 6/8/2023 4:49 PM, Eugenio Perez Martin wrote: > >>> On Thu, Jun 8, 2023 at 9:07 AM Zhu, Lingshan > >>> wro

Re: [PATCH V9 10/46] qdev-properties: strList

Hi Paolo, Daniel, Eduardo, Could one of you review this patch which is in your area? It defines DEFINE_PROP_STRLIST, which is added to migration_properties[] in patch 15 of this series: https://lore.kernel.org/qemu-devel/1658851843-236870-16-git-send-email-steven.sist...@oracle.com/ For cpr

Re: [PATCH 12/15] hw/timer/arm_timer: Pass timer output IRQ as parameter to arm_timer_new

On Wed, 31 May 2023 at 21:37, Philippe Mathieu-Daudé wrote: > > Both SP804State/IcpPitState peek at ArmTimerState internal state. > This is fine so far but we want to convert ArmTimerState to QOM > where peeking at QOM state internal should be avoided. > ArmTimerState's IRQ is just a pointer, so w

Re: [PATCH 13/15] hw/timer/arm_timer: Fix misuse of SysBus IRQ in IcpPitState

On Wed, 31 May 2023 at 21:37, Philippe Mathieu-Daudé wrote: > > SysBus IRQ are *output* IRQs. As some sort of simplification > to avoid to forward it, IcpPitState misuses it as ARM timer > input IRQ. Fix that by using a simple IRQ forwarder handler. > > Signed-off-by: Philippe Mathieu-Daudé > ---

Re: [PATCH v2] hw/acpi: Fix PM control register access

On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote: > On 07/06/2023 21:01, BALATON Zoltan wrote: > > > On pegasos2 which has ACPI as part of VT8231 south bridge the board > > firmware writes PM control register by accessing the second byte so > > addr will be 1. This wasn't handled c

[PATCH 0/5] improve ahci test suite

From: Niklas Cassel Hello John, This series should be applied on top of the series called: "[PATCH v2 0/8] misc AHCI cleanups" which can be found here: https://lists.nongnu.org/archive/html/qemu-block/2023-06/msg00038.html This series improves the ahci test suite to be in line with the AHCI spe

[PATCH 4/5] libqos/ahci: improve ahci_port_check_error()

From: Niklas Cassel Improve ahci_port_check_error() to also assert that PxIS.TFES is set when expecting errors. Signed-off-by: Niklas Cassel --- tests/qtest/libqos/ahci.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tests/qtest/libqos/ahci.c b/tests/q

[PATCH 1/5] libqos/ahci: fix ahci_command_wait()

From: Niklas Cassel A command that has ERR_STAT set, does not get to clear PxCI. See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI, and 5.3.16.5 ERR:FatalTaskfile. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready() with ready == false, intentionally sending a com

[PATCH 2/5] libqos/ahci: fix ahci_port_check_nonbusy()

From: Niklas Cassel A command that has ERR_STAT set, does not get to clear PxCI. See AHCI 1.3.1, section 5.3.8, states RegFIS:Entry and RegFIS:ClearCI, and 5.3.16.5 ERR:FatalTaskfile. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready() with ready == false, intentionally sending a com

[PATCH 3/5] libqos/ahci: simplify ahci_port_check_error()

From: Niklas Cassel Modify ahci_port_check_error() to simply take a struct AHCICommand. This way, the conditionals are in line which the existing code, e.g. ahci_port_check_nonbusy(), which checks for cmd->errors. This makes the code easier to reason with, we don't want to use cmd->errors in som

[PATCH 5/5] libqos/ahci: perform mandatory error recovery on error

From: Niklas Cassel When the HBA encouters an error, the host has to perform error recovery, see AHCI 1.3.1 section 6.2.2.1, in order to be able issue new commands. If we don't do this, all the commands that we queue will get aborted. Some tests, e.g. test_atapi_tray() call ahci_atapi_test_ready

Re: [PATCH 05/15] hw/timer/arm_timer: CamelCase rename icp_pit_state -> IntegratorPitState

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Following docs/devel/style.rst guidelines, rename icp_pit_state > using CamelCase as IntegratorPitState. > > Signed-off-by: Philippe Mathieu-Daudé > --- though PIT here is an acronym so I think style would prefer IntegratorPITState

Re: [PATCH 10/15] hw/timer/arm_timer: Use array of frequency in SP804State

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > SP804State use arrays for timers and IRQ levels. Be consistent > and use another one for the frequencies. This will allow to > simplify using for() loop statement in the next commit. > > Signed-off-by: Philippe Mathieu-Daudé Reviewe

Re: [PATCH 09/15] hw/timer/arm_timer: Convert ArmTimerState::freq to uint32_t type

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > In preparation of accessing ArmTimerState::freq as a QOM property, > convert it to uint32_t (so we'll be able to use DEFINE_PROP_UINT32). > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/timer/arm_timer.c | 2 +- Reviewed-by: Pe

Re: [PATCH v2] hw/acpi: Fix PM control register access

On Thu, 8 Jun 2023, Michael S. Tsirkin wrote: On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote: On 07/06/2023 21:01, BALATON Zoltan wrote: On pegasos2 which has ACPI as part of VT8231 south bridge the board firmware writes PM control register by accessing the second byte so add

Re: [PULL 0/6] tricore queue

On 6/7/23 09:24, Bastian Koppelmann wrote: The following changes since commit f5e6786de4815751b0a3d2235c760361f228ea48: Merge tag 'pull-target-arm-20230606' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-06-06 12:11:34 -0700) are available in the Git repository at:

Re: [PATCH 04/15] hw/timer/arm_timer: Remove pointless cast from void *

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/timer/arm_timer.c | 16 > 1 file changed, 8 insertions(+), 8 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM

Re: [EXT] Re: [Qemu RFC 0/7] Early enabling of DCD emulation in Qemu

From: Jonathan Cameron Sent: Thursday, June 8, 2023 2:43 AM To: Shesha Bhushan Sreenivasamurthy Cc: Fan Ni ; qemu-devel@nongnu.org ; linux-...@vger.kernel.org ; gregory.pr...@memverge.com ; hch...@avery-design.com.tw ; cbr...@avery-design.com ; dan.j.willi...@intel.com ; Adam Manzanares ;

Re: [PATCH 07/15] hw/timer/arm_timer: Extract arm_timer_reset()

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Extract arm_timer_reset() before converting this model to QOM/QDev > in few commits. This will become our DeviceReset handler. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/timer/arm_timer.c | 7 ++- > 1 file changed, 6 i

Re: [PATCH v3 5/5] intel_iommu: Optimize out some unnecessary UNMAP calls

On Thu, Jun 08, 2023 at 11:11:15AM -0300, Jason Gunthorpe wrote: > On Thu, Jun 08, 2023 at 10:05:08AM -0400, Peter Xu wrote: > > > IIUC what VFIO does here is it returns succeed if unmap over nothing rather > > than failing like iommufd. Curious (like JasonW) on why that retval? I'd > > assume f

[PATCH] imx_serial: set wake bit when we receive a data byte

The linux kernel added a flood check for rx data recently in commmit 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This check uses the wake bit in the uart status register 2. The wake bit indicates that the receiver detected a start bit. If the kernel sees a number of rx interrup

Re: [Qemu RFC 0/7] Early enabling of DCD emulation in Qemu

Shesha Bhushan Sreenivasamurthy wrote: > Hi Fan, >I am implementing DCD FMAPI commands and planning to start pushing changes > to the below branch. That requires the contributions you have made. Can your > changes be pushed to the below branch ? > > https://gitlab.com/jic23/qemu/-/tree/cxl-2

Re: [PATCH 08/15] hw/timer/arm_timer: Rename arm_timer_init() -> arm_timer_new()

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > QDev models often use foo_new() as the combination of > foo_init() + foo_realize(). Here arm_timer_init() is > a such combination, so rename it as arm_timer_new() to > emphasis the returned device is already realized. The other conve

Re: [PULL 0/3] SNAFU build system fixes for 2023-06-07

On 6/7/23 08:47, Paolo Bonzini wrote: The following changes since commit f5e6786de4815751b0a3d2235c760361f228ea48: Merge tag 'pull-target-arm-20230606' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-06-06 12:11:34 -0700) are available in the Git repository at: ht

Re: [PATCH 03/15] hw/timer/arm_timer: Add missing sp804_unrealize() handler

On Wed, 31 May 2023 at 21:36, Philippe Mathieu-Daudé wrote: > > Release the IRQs allocated in sp804_realize() in the > corresponding sp804_unrealize() handler. > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/timer/arm_timer.c | 10 ++ > 1 file changed, 10 insertions(+) > > diff --gi

Re: [PATCH v3 0/5] Optimize UNMAP call and bug fix

On Thu, Jun 08, 2023 at 05:52:26PM +0800, Zhenzhong Duan wrote: > Hi All, > > This patchset includes some fixes on VFIO dirty sync and vIOMMU. > PATCH1 isn't needed now as dependent changes in PATCH2 is removed, > but as Peter has given Reviewed-by, leave it to maintainer to > decide if pick or no

[PATCH v2 2/3] Add virtio-sound-pci device

This patch adds a PCI wrapper device for the virtio-sound device. To test this, you'll need a >=5.13 kernel compiled with CONFIG_SND_VIRTIO=y, which at the time of writing most distros have off by default. Use with following flags in the invocation: -device virtio-sound-pci,disable-legacy=on

[PATCH v2 0/3] Add VIRTIO sound card

This patch series adds an audio device implementing the recent virtio sound spec (1.2) and a corresponding PCI wrapper device. Main differences with v1 patch <20230526204845.673031-1-manos.pitsidiana...@linaro.org>: - Split virtio-snd and virtio-snd-pci devices to two commits - Added audio capt

[PATCH v2 1/3] Add virtio-sound device

This patch adds an audio device implementing the recent virtio sound spec (1.2). PCM functionality is implemented, and jack[0], chmaps[1] messages are at the moment left unimplemented. PS2: This patch was based on a draft patch posted by OpenSynergy in 2019. [2] [0]: https://www.kernel.org/doc/h

[PATCH v2 3/3] Implement audio capture in virtio-snd device

Signed-off-by: Emmanouil Pitsidianakis --- hw/virtio/trace-events | 3 +- hw/virtio/virtio-snd.c | 239 +++-- 2 files changed, 206 insertions(+), 36 deletions(-) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index b77d78abdc..b58c007297 100644

[PULL 1/1] 9pfs: prevent opening special files (CVE-2023-2861)

The 9p protocol does not specifically define how server shall behave when client tries to open a special file, however from security POV it does make sense for 9p server to prohibit opening any special file on host side in general. A sane Linux 9p client for instance would never attempt to open a s

[PULL 0/1] 9p security fix 2023-06-08

gs/pull-9p-20230608 for you to fetch changes up to f6b0de53fb87ddefed348a39284c8e2f28dc4eda: 9pfs: prevent opening special files (CVE-2023-2861) (2023-06-08 17:04:58 +0200) * Fix for CVE

Re: virtio-blk using a single iothread

On Thu, Jun 08, 2023 at 10:40:57AM +0300, Sagi Grimberg wrote: > Hey Stefan, Paolo, > > I just had a report from a user experiencing lower virtio-blk > performance than he expected. This user is running virtio-blk on top of > nvme-tcp device. The guest is running 12 CPU cores. > > The guest read/

Ping: [PATCH v6] Emulate dip switch language layout settings on SUN keyboard

I didn't get much response to my last version of the patch to implement emulation of language selection dip switch on SUN keyboards. By request, I changed the patch to listen for -global escc.sunkbd_layout= instead of using the -k switch to select keyboard layout. What do you think about this patc

Re: QEMU developers fortnightly conference call for 2023-06-13

Philippe Mathieu-Daudé wrote: > Hi Juan, > > On 7/6/23 15:55, juan.quint...@gmail.com wrote: >> QEMU developers fortnightly conference call >> Hi >> Here is the wiki for whover that wants to add topics to the agenda. >> https://wiki.qemu.org/QEMUCall#Call_for_agenda_for_2023-06-13 >>

Re: [PATCH v6] Emulate dip switch language layout settings on SUN keyboard

On Sun, Apr 30, 2023 at 10:55:33PM +0200, Henrik Carlqvist wrote: > I have now changed the patch to instead of using the -k switch use > > -global escc.sunkbd_layout= > > to select keyboard layout. It would be nice to somehow document this. Yes, in > the monitor, you can type "info qtree" and s

Re: [PATCH v3 5/5] intel_iommu: Optimize out some unnecessary UNMAP calls

On Thu, Jun 08, 2023 at 11:40:55AM -0400, Peter Xu wrote: > > But if there is the proper locks to prevent a map/unmap race, then > > there should also be the proper locks to check that there is no map in > > the first place and avoid the kernel call.. > > The problem is IIRC guest iommu driver ca

[PATCH] tcg/tci: Fix MemOpIdx operand index for 3-operand memops

Cut and paste error from the 4-operand memops. Fixes: ab64da797740 ("tcg/tci: Adjust passing of MemOpIdx") Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 0

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