Signed-off-by: Richard Henderson
---
.../aarch64/host/load-extract-al16-al8.h | 40 +++
1 file changed, 40 insertions(+)
create mode 100644 host/include/aarch64/host/load-extract-al16-al8.h
diff --git a/host/include/aarch64/host/load-extract-al16-al8.h
b/host/include/aarch
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 8996e29ca9..5e7ac6fb76 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-t
With FEAT_LSE2, LDP/STP suffices. Without FEAT_LSE2, use LDXP+STXP
16-byte atomicity is required and LDP/STP otherwise.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-con-set.h | 2 +
tcg/aarch64/tcg-target.h | 11 ++-
tcg/aarch64/tcg-target.c
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target-con-set.h | 2 +
tcg/ppc/tcg-target-con-str.h | 1 +
tcg/ppc/tcg-target.h
On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale
wrote:
>
> Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
> and check for it when accessing the fcsr register and its fields.
>
> Signed-off-by: Mayuresh Chitale
> Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Alist
On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale
wrote:
>
> When misa.F is 0 tb->flags.FS field is unused and can be used to save
> the current state of smstateen0.FCSR check which is needed by the
> floating point translation routines.
>
> Signed-off-by: Mayuresh Chitale
> Reviewed-by: Richard H
On Fri, May 19, 2023 at 3:51 AM Mayuresh Chitale
wrote:
>
> Patch 4 and 5 of the smstateen series need to be re-submitted with
> changes described in the email below.
> https://lists.nongnu.org/archive/html/qemu-riscv/2022-11/msg00155.html
> Hence splitting the patch 4 of the original series into
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Split RISCVCPUConfig declarations to prepare for passing it to disas.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.h | 114 +---
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Use pointer to pass more information of target to disasembler,
> such as pass cpu.cfg related information in following commits.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: A
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Pass RISCVCPUConfig as disassemble_info.target_info to support disas
> of conflict instructions related to specific extensions.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: A
On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote:
>
> Support disas for Zcmt* instructions only when related extensions
> are supported.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/ri
On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote:
>
> Support disas for Z*inx instructions only when Zfinx extension is supported.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Alistair Francis
Alistair
> ---
> disas/riscv.c
On Tue, May 23, 2023 at 7:37 PM Weiwei Li wrote:
>
> Fix lines with over 80 characters.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 201 +++
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Currently decomp_rv32 and decomp_rv64 value in opcode_data for vector
> instructions are the same op index as their own. And they have no
> functional decomp_data. So they have no functional difference from just
> leaving them as zero.
>
> Signe
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Remove redundant parenthese and fix multi-line comments.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> Reviewed-by: Daniel Henrique Barboza
Acked-by: Alistair Francis
Alistair
> ---
> disas/riscv.c | 219 +
On Thu, May 25, 2023 at 8:55 PM Viktor Prutyanov wrote:
>
> On Wed, May 24, 2023 at 11:25 AM Jason Wang wrote:
> >
> > On Sat, May 20, 2023 at 1:50 AM Viktor Prutyanov wrote:
> > >
> > > On Thu, May 18, 2023 at 9:14 AM Jason Wang wrote:
> > > >
> > > > On Fri, May 12, 2023 at 9:51 PM Viktor Pru
On Tue, May 23, 2023 at 7:38 PM Weiwei Li wrote:
>
> Some extensions have conflict encodings, such as
> * Z*inx reuse the same encodings as normal float point extensions.
> * Zcm* reuse the some encodings of Zcd.
> * Custom extensions from different vendors may share the same encodings.
> To re
On Wed, May 24, 2023 at 12:16 AM Weiwei Li wrote:
>
> Use cur_insn_len to store the length of the current instruction to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c
On Wed, May 24, 2023 at 12:14 AM Weiwei Li wrote:
>
> Reduce reliance on absolute value to prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/trans_rvi.c.inc | 4 ++--
> targ
Two copy-paste errors walking the parse tree.
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index 3f9f6876f7..e2640cc79b 100644
--- a/scripts/decodetree.py
+++ b/scr
Test err_pattern_group_empty.decode failed with exception:
Traceback (most recent call last):
File "./scripts/decodetree.py", line 1424, in main()
File "./scripts/decodetree.py", line 1342, in main toppat.build_tree()
File "./scripts/decodetree.py", line 627, in build_tree
self.tree = s
Signed-off-by: Richard Henderson
---
tests/decode/check.sh| 24
tests/decode/meson.build | 59
tests/meson.build| 5 +---
3 files changed, 60 insertions(+), 28 deletions(-)
delete mode 100755 tests/decode/check.sh
create mod
Add --test-for-error to decodetree.py and convert the tests to meson.
This exposes an exception error that had been hidden by the fact that
the script as a whole did exit with error. Which proves that this is
a better way to run the tests.
r~
Richard Henderson (4):
decodetree: Add --test-for
Invert the exit code, for use with the testsuite.
Signed-off-by: Richard Henderson
---
scripts/decodetree.py | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/scripts/decodetree.py b/scripts/decodetree.py
index a03dc6b5e3..3f9f6876f7 100644
--- a/scripts/decodetree.py
On Wed, May 24, 2023 at 12:08 AM Weiwei Li wrote:
>
> Reduce reliance on absolute values(by passing pc difference) to
> prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn_trans/tra
On Wed, May 24, 2023 at 12:14 AM Weiwei Li wrote:
>
> Reduce reliance on absolute values by using true pc difference for
> gen_pc_plus_diff() to prepare for PC-relative translation.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
> ---
> ta
On Wed, May 24, 2023 at 12:12 AM Weiwei Li wrote:
>
> Add a base pc_save for PC-relative translation(CF_PCREL).
> Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
> Use gen_pc_plus_diff to get the pc-relative address.
> Enable CF_PCREL in System mode.
>
> Signed-off-by: Weiwei
On Wed, May 24, 2023 at 12:07 AM Weiwei Li wrote:
>
> pc_succ_insn is no longer useful after the introduce of cur_insn_len
> and all pc related value use diff value instead of absolute value.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
Alistair
>
On 25/05/2023 19:49, Jonathan Cameron via wrote:
> On Fri, 19 May 2023 16:58:02 +0800
> Li Zhijian wrote:
>
>> Using the same style except the 'Topo' abbreviation.
>>
>> Signed-off-by: Li Zhijian
>> ---
>> I'm not a native speaker, feel free to correct me.
>
> I've edited slightly and applied
"The beginning of the structure, with pretaddr, should be just below 16-byte
alignment."
It is incorrect! The beginning of the structure, with pretaddr not aligned as
16-byte!
On x86-64, It aligned as (16n - sizeof(void*)) because of instruction "call" !
> -原始邮件-
> 发件人: "Richard He
On Tue, May 23, 2023 at 8:29 PM Sunil V L wrote:
>
> Currently, virt machine supports two pflash instances each with
> 32MB size. However, the first pflash is always assumed to
> contain M-mode firmware and reset vector is set to this if
> enabled. Hence, for S-mode payloads like EDK2, only one pf
> On Apr 27, 2023, at 16:05, zhenwei pi wrote:
>
> Generally guest side should discover which services the device is
> able to offer, then do requests on device.
>
> However it's also possible to break this rule in a guest. Handle
> unexpected request here to avoid NULL pointer dereference.
>
On Wed, May 24, 2023 at 12:15 AM Weiwei Li wrote:
>
> This patchset tries to add support for PC-relative translation.
>
> The existence of CF_PCREL can improve performance with the guest
> kernel's address space randomization. Each guest process maps libc.so
> (et al) at a different virtual addre
On Thu, May 25, 2023 at 8:58 PM Viktor Prutyanov wrote:
>
> The guest can disable or never enable Device-TLB. In these cases,
> it can't be used even if enabled in QEMU. So, check Device-TLB state
> before registering IOMMU notifier and select unmap flag depending on
> that. Also, implement a way
On Thu, May 25, 2023 at 8:58 PM Viktor Prutyanov wrote:
>
> If vhost is enabled for virtio-net, Device-TLB enable/disable events
> must be passed to vhost for proper IOMMU unmap flag selection.
>
> Signed-off-by: Viktor Prutyanov
Acked-by: Jason Wang
Thanks
> ---
> hw/net/virtio-net.c | 1 +
On Thu, May 25, 2023 at 1:37 AM Eugenio Perez Martin
wrote:
>
> On Wed, May 17, 2023 at 7:49 AM Jason Wang wrote:
> >
> > On Wed, May 17, 2023 at 1:46 PM Eugenio Perez Martin
> > wrote:
> > >
> > > On Wed, May 17, 2023 at 5:14 AM Jason Wang wrote:
> > > >
> > > > On Tue, May 9, 2023 at 11:44 PM
This patch series adds support for a new PCI-based UFS device.
The UFS pci device id (PCI_DEVICE_ID_REDHAT_UFS) is not registered
in the Linux kernel yet, so it does not work right away, but I confirmed
that it works with Linux when the UFS pci device id is registered.
I have also verified that i
This commit makes the UFS device support query
and nop out transfer requests.
The next patch would be support for UFS logical
unit and scsi command transfer request.
Signed-off-by: Jeuk Kim
---
hw/ufs/ufs.c | 967 ++-
hw/ufs/ufs.h | 45 +++
2 fil
Universal Flash Storage (UFS) is a high-performance mass storage device
with a serial interface. It is primarily used as a high-performance
data storage device for embedded applications.
This commit contains code for UFS device to be recognized
as a UFS PCI device.
Patches to handle UFS logical un
This commit adds support for ufs logical unit.
The LU handles processing for the SCSI command,
unit descriptor query request.
This commit enables the UFS device to process
IO requests.
Signed-off-by: Jeuk Kim
---
hw/ufs/lu.c | 1441 ++
hw/ufs/mes
This is really, really, *really* for maintainers of the code parsing
-cpu to review. Code parsing -cpu:
* parse_cpu_option() in cpu.c
Eduardo Habkost (supporter:Machine core)
Marcel Apfelbaum (supporter:Machine core)
"Philippe Mathieu-Daudé" (reviewer:Machine core)
Yanan Wang (review
On 5/25/23 21:57, Ninad Palsule wrote:
Hello Cedric,
On 5/25/23 1:37 AM, Cédric Le Goater wrote:
[ ... ]
However, regarding Cédric's log above, a reboot is expected on the first
boot of a fresh image when there's valid VPD available. For the first
boot of a fresh image we configure the kerne
Hi,
the main motivator for this series was
https://gitlab.com/qemu-project/qemu/-/issues/1453. To test that I'm not
screwing up this refactor I also extended the tests by C programs so we can test
the PCXI/ICR registers by recursive function call. Through these tests I also
found a problem, where
this seperates these tests from the upcoming tests written in C.
Also rename the compiled test to 'test_.asm.tst'.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 35 ---
tests/tcg/tricore/{ => asm}/macros.h | 0
tests/tcg/tricore/{ =>
the linker might rearrange sections, so lets reference memory by label
name instead of addr + off.
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/asm/macros.h | 1 -
tests/tcg/tricore/asm/test_ld_bu.S | 4 ++--
tests/tcg/tricore/asm/test_ld_h.S | 8
3 files changed, 6 inse
this allows us to exercise the startup code used by GCC to call main().
Signed-off-by: Bastian Koppelmann
---
configure | 1 +
tests/tcg/tricore/Makefile.softmmu-target | 13 +
tests/tcg/tricore/c/crt0-tc2x.S | 335 ++
tests/tcg/tr
Signed-off-by: Bastian Koppelmann
---
tests/tcg/tricore/Makefile.softmmu-target | 3 ++-
tests/tcg/tricore/c/test_context_save_areas.c | 15 +++
2 files changed, 17 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/tricore/c/test_context_save_areas.c
diff --git a/tests/
starting from ISA version 1.6.1 (previously known as 1.6P/E), some
bitfields in PCXI and ICR have changed. We also refactor these
registers using the register fields API.
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1453
---
v1 -> v2:
- Created ice
we were copying PSW into a local variable, updated PSW.CDE in the local
and never wrote it back. So when we called save_context_upper() we were
using the non-local version of PSW which did not contain the updated
PSW.CDE.
Signed-off-by: Bastian Koppelmann
---
target/tricore/op_helper.c | 2 ++
1
>-Original Message-
>From: Peter Xu
>Sent: Thursday, May 25, 2023 9:54 PM
>Subject: Re: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP
>calls
>
>On Thu, May 25, 2023 at 11:29:34AM +, Duan, Zhenzhong wrote:
>> Hi Peter,
>>
>> See inline.
>> >-Original Message-
>> >Fro
Sync-up Linux header to get latest KVM RISC-V headers having AIA support.
Note: This is a placeholder commit and could be replaced when all referenced
Linux patchsets are mainlined.
The linux-headers changes are from 2 different patchsets.
[1]
https://lore.kernel.org/lkml/20230404153452.2405681
- Do not set the mmio operations of APLIC and IMSIC when using KVM AIA
- Send interrupt signal to KVM AIA via KVM_IRQ_LINE API
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/intc/riscv_aplic.c | 19 +++
hw/intc/riscv_imsic.c | 16 +++-
2 files changed, 26
This series adds support for KVM AIA in RISC-V architecture.
In order to test these patches, we require Linux with KVM AIA support which can
be found in the qemu_kvm_aia branch at https://github.com/yong-xuan/linux.git
This kernel branch is based on the riscv_aia_v1 branch available at
https://git
Select KVM AIA when the host kernel has in-kernel AIA chip support.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/riscv/virt.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 18b94888ab..57a07fa6c5 100644
--- a/hw/riscv/virt.c
Remove M mode AIA devices when using KVM acceleration
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
hw/riscv/virt.c | 199 +---
1 file changed, 105 insertions(+), 94 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4e3efbee1
We check the in-kernel irqchip support when using KVM acceleration.
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
target/riscv/kvm.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 0f932a5b96..eb469e8ca5 10
implement a function to create an KVM AIA chip
Signed-off-by: Yong-Xuan Wang
Reviewed-by: Jim Shu
---
target/riscv/kvm.c | 83
target/riscv/kvm_riscv.h | 3 ++
2 files changed, 86 insertions(+)
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
On Fri, May 26, 2023 at 2:22 PM Duan, Zhenzhong
wrote:
>
>
> >-Original Message-
> >From: Peter Xu
> >Sent: Thursday, May 25, 2023 9:54 PM
> >Subject: Re: [PATCH] intel_iommu: Optimize out some unnecessary UNMAP
> >calls
> >
> >On Thu, May 25, 2023 at 11:29:34AM +, Duan, Zhenzhong wro
On 26/05/2023 07.05, Jeuk Kim wrote:
Universal Flash Storage (UFS) is a high-performance mass storage device
with a serial interface. It is primarily used as a high-performance
data storage device for embedded applications.
This commit contains code for UFS device to be recognized
as a UFS PCI d
On Thu, May 25, 2023 at 11:03:52AM -0700, Andrea Bolognani wrote:
> On Thu, May 25, 2023 at 10:18:00PM +0530, Sunil V L wrote:
> > This series improves the pflash usage in RISC-V virt machine with solutions
> > to
> > below issues.
> >
> > 1) Currently the first pflash is reserved for ROM/M-mode f
On Tue, May 23, 2023 at 8:29 PM Sunil V L wrote:
>
> Currently, virt machine supports two pflash instances each with
> 32MB size. However, the first pflash is always assumed to
> contain M-mode firmware and reset vector is set to this if
> enabled. Hence, for S-mode payloads like EDK2, only one pf
Hello Peter, all
On Thu, 25 May 2023 at 18:33, Peter Xu wrote:
> IIRC this bug used to only reproduce on rt kernels, is it still the case?
>
* Yes, it's a same crash.
> Here besides doing correct unregister, does it also mean that even if
> event_notifier_init() failed there's totally no erro
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