> -Original Message-
> From: Akihiko Odaki
> Sent: Friday, 14 April 2023 13:37
> Cc: Sriram Yagnaraman ; Jason Wang
> ; Dmitry Fleytman ;
> Michael S. Tsirkin ; Alex Bennée ;
> Philippe Mathieu-Daudé ; Thomas Huth
> ; Wainer dos Santos Moschetta
> ; Beraldo Leal ; Cleber Rosa
> ; Laurent
> -Original Message-
> From: Vladimir Sementsov-Ogievskiy
> Sent: Friday, April 14, 2023 5:51 PM
> To: Zhang, Chen ; qemu-devel@nongnu.org
> Cc: qemu-bl...@nongnu.org; pbonz...@redhat.com; arm...@redhat.com;
> ebl...@redhat.com; jasow...@redhat.com; dgilb...@redhat.com;
> quint...@redhat
The kernel does not require PROT_READ for addresses passed to mincore.
For example the fincore(1) tool from util-linux uses PROT_NONE and
currently does not work under qemu-user.
Example (with fincore(1) from util-linux 2.38):
$ fincore /proc/self/exe
RES PAGES SIZE FILE
24K 6 22.1K /proc/se
From: Mateusz Albecki
Current code will not call ide_cmd_done when aborting the unsupported
command which will lead to the command timeout on the driver side instead
of getting a D2H FIS with ABRT indication. This can lead to problems on the
driver side as the spec mandates that device should ret
The patch was developed during the debug for the UEFI SCT issue reported in
https://bugzilla.tianocore.org/show_bug.cgi?id=4016. After fixing the issue
in EDK2 the test was still failing on qemu since qemu wouldn't return abort and
instead we would get a command timeout. Additionally qemu also has
From: Nicolas Pitre
Add Kconfig options for CBQRI and an example instantiation of capacity
and bandwidth controllers.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
hw/riscv/Kconfig | 8
1 file changed, 8 insertions(+)
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
i
From: Nicolas Pitre
Implement a bandwidth controller according to the Capacity and Bandwidth
QoS Register Interface (CBQRI) which supports these capabilities:
- Number of access types: 1 (no code/data differentiation)
- Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
- Event
From: Nicolas Pitre
Initialize an example SoC that instantiates CBQRI capacity and bandwidth
controllers with specific parameters for testing purposes.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
Note: this solution is not flexible enough for upstream inclusion.
Future work wi
From: Nicolas Pitre
Implement a capacity controller according to the Capacity and Bandwidth
QoS Register Interface (CBQRI) which supports these capabilities:
- Number of access types: 2 (code and data)
- Usage monitoring operations: CONFIG_EVENT, READ_COUNTER
- Event IDs supported: None, O
From: Kornel Dulęba
Implement the sqoscfg CSR defined by the Ssqosid ISA extension
(Supervisor-mode Quality of Service ID). The CSR contains two fields:
- Resource Control ID (RCID) used determine resource allocation
- Monitoring Counter ID (MCID) used to track resource usage
The CSR is def
From: Nicolas Pitre
Instantiate a hypothetical CBQRI configuration for testing purposes with
these properties:
- L2 cache controllers
- Resource type: Capacity
- NCBLKS: 12
- Number of access types: 2 (code and data)
- Usage monitoring not supported
- Capacity allocation op
From: Nicolas Pitre
Build the CBQRI controllers and CBQRI example configuration when enabled
by Kconfig.
Signed-off-by: Nicolas Pitre
Signed-off-by: Drew Fustini
---
hw/riscv/meson.build | 4
1 file changed, 4 insertions(+)
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build
index
This RFC series implements the Ssqosid extension and the sqoscfg CSR as
defined in the RISC-V Capacity and Bandwidth Controller QoS Register
Interface (CBQRI) specification [1]. Quality of Service (QoS) in this
context is concerned with shared resources on an SoC such as cache
capacity and memory b
From: Nicolas Pitre
Define structs to represent the hardware capabilities of capacity and
bandwidth controllers according to the RISC-V Capacity and Bandwidth QoS
Register Interface (CBQRI).
Link: https://github.com/riscv-non-isa/riscv-cmqri/blob/main/riscv-cbqri.pdf
Signed-off-by: Nicolas Pitre
On Wed, Apr 12, 2023 at 9:43 PM Richard Henderson
wrote:
>
> v6: 20230325105429.1142530-1-richard.hender...@linaro.org
>
> Changes for v7:
> * Rebase on Alistair's riscv-to-apply.next.
> * Replace priv_level() with ctx->priv in trans_xthead.c.inc (Zhiwei).
>
>
> r~
>
>
> Fei Wu (2):
> target
On Thu, Apr 13, 2023 at 11:35 PM Ivan Klokov wrote:
>
> Since g_new is used to initialize the RISCVAPLICState->state structure,
> in some case we get behavior that is not as expected. This patch
> changes this to g_new0, which allows to initialize the APLIC in the correct
> state.
>
> Signed-off-
On Thu, Apr 13, 2023 at 11:35 PM Ivan Klokov wrote:
>
> Since g_new is used to initialize the RISCVAPLICState->state structure,
> in some case we get behavior that is not as expected. This patch
> changes this to g_new0, which allows to initialize the APLIC in the correct
> state.
>
> Signed-off-
On Thu, Apr 13, 2023 at 3:24 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 4/12/23 08:35, Weiwei Li wrote:
> >
> > On 2023/4/12 18:55, Alistair Francis wrote:
> >> On Wed, Apr 12, 2023 at 12:55 PM Weiwei Li wrote:
> >>>
> >>> On 2023/4/12 10:12, Alistair Francis wrote:
> On Fri, Apr 7, 2023 a
On Fri, Apr 14, 2023 at 12:13 AM Weiwei Li wrote:
>
> Even though Zca/Zcf/Zcd can be included by C/F/D, however, their priv
> version is higher than the priv version of C/F/D. So if we use check
> for them instead of check for C/F/D totally, it will trigger new
> problem when we try to disable the
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
wrote:
>
> QMP CPU commands are usually implemented by a separated file,
> -qmp-cmds.c, to allow them to be build only for softmmu targets.
> This file uses a CPU QOM header with basic QOM declarations for the
> arch.
>
> We'll introduce quer
On Wed, Apr 12, 2023 at 4:37 AM Daniel Henrique Barboza
wrote:
>
> This command is used by tooling like libvirt to retrieve a list of
> supported CPUs. Each entry returns a CpuDefinitionInfo object that
> contains more information about each CPU.
>
> This initial support includes only the name of
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
wrote:
>
> This new abstract type will be used to differentiate between static and
> non-static CPUs in query-cpu-definitions.
>
> All generic CPUs were changed to be of this type. Named CPUs are kept as
> TYPE_RISCV_CPU and will still be con
On Wed, Apr 12, 2023 at 4:36 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> In this v3 I removed patches 3 and 4 of v2.
>
> Patch 3 now implements a new type that the generic CPUs (any, rv32,
> rv64, x-rv128) were converted to. This type will be used by
> query-cpu-definitions to determine if a giv
On Tue, Apr 11, 2023 at 3:51 AM Johannes Thumshirn wrote:
>
> Add PCI based MEN Chameleon Bus carrier emulation.
>
> Signed-off-by: Johannes Thumshirn
Acked-by: Alistair Francis
Alistair
> ---
> hw/mcb/Kconfig | 6 +
> hw/mcb/mcb-pci.c| 297
On Wed, Apr 12, 2023 at 7:18 PM Alexandre Ghiti wrote:
>
> As per the specification, in 64-bit, if any of the pte reserved bits 60-54
> is set, an exception should be triggered (see 4.4.1, "Addressing and Memory
> Protection"), so implement this behaviour in the address translation process.
>
> Re
On Sat, Apr 8, 2023 at 1:34 AM Irina Ryapolova
wrote:
>
> Before changing the flow check for sv39/48/57.
>
> According to specification (for Supervisor mode):
> Sv39 implementations support a 39-bit virtual address space, divided into 4
> KiB pages.
> Instruction fetch addresses and load and stor
On 14-04-23, 17:04, Alex Bennée wrote:
> hw/virtio/vhost-user-device-pci.c | 71 +
> hw/virtio/vhost-user-device.c | 359 ++
> hw/virtio/vhost-user-fs.c | 4 +-
> hw/virtio/vhost-user-gpio.c| 405 +
> hw/virt
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
Some comments are also added to indicate that predicate() must be
provided for an impleme
On Sat, Apr 8, 2023 at 1:34 AM Irina Ryapolova
wrote:
>
> Before changing the flow check for sv39/48/57.
>
> According to specification (for Supervisor mode):
> Sv39 implementations support a 39-bit virtual address space, divided into 4
> KiB pages.
> Instruction fetch addresses and load and stor
On Mon, Apr 17, 2023 at 2:32 PM Bin Meng wrote:
>
> When reading a non-existent CSR QEMU should raise illegal instruction
> exception, but currently it just exits due to the g_assert() check.
>
> This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617.
> Some comments are also added
On Tue, Apr 11, 2023 at 3:50 AM Johannes Thumshirn wrote:
>
> Add 16z069 Watchdog over MEN Chameleon BUS emulation.
>
> Signed-off-by: Johannes Thumshirn
> ---
> hw/watchdog/Kconfig | 5 +
> hw/watchdog/meson.build | 1 +
> hw/watchdog/wdt_z069.c | 218 ++
Since the driver doesn't support interrupts, we must return early when
index is set to VIRTIO_CONFIG_IRQ_IDX.
Fixes: 544f0278afca ("virtio: introduce macro VIRTIO_CONFIG_IRQ_IDX")
Signed-off-by: Viresh Kumar
---
hw/virtio/vhost-user-i2c.c | 20
1 file changed, 20 insertions(
On 4/14/23 17:10, Fabiano Rosas wrote:
Harsh Prateek Bora writes:
A bit vague on the subject line. I would expect to see some mention to
nested at least.
Sure, will update subject line to include mention of
[h_enter|spapr_exit]_nested routines.
The bits in cr reg are grouped into eig
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