On Sun, Apr 09, 2023 at 10:18:28PM +0200, Stefan Weil wrote:
> Signed-off-by: Stefan Weil
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
It does but I don't think we should bother for 8.0. Nothing
bad will happen if
On Sun, Apr 09, 2023 at 09:40:22PM +0700, Bui Quang Minh wrote:
> Hi everyone,
>
> This series implements x2APIC mode in userspace local APIC and the
> RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
> and AMD iommu are adjusted to support x2APIC interrupt remapping. With
"Wu, Fei" writes:
> On 4/10/2023 6:36 PM, Alex Bennée wrote:
>>
>> Richard Henderson writes:
>>
>>> On 4/6/23 00:46, Alex Bennée wrote:
If your aim is to examine JIT efficiency what is wrong with the current
"info jit" that you can access via the HMP? Also I'm wondering if its
Philippe Mathieu-Daudé writes:
> "hw/core/cpu.h" defines 'first_cpu' as QTAILQ_FIRST_RCU(&cpus).
>
> arm_gic_common_reset_irq_state() calls its second argument
> 'first_cpu', producing a build failure when "hw/core/cpu.h"
> is included:
>
> hw/intc/arm_gic_common.c:238:68: warning: omitting t
Andrew Jones writes:
> On Tue, Mar 07, 2023 at 11:28:38AM +, Alex Bennée wrote:
>> I last had a go at getting these up-streamed at the end of 2021 so
>> its probably worth having another go. From the last iteration a
>> number of the groundwork patches did get merged:
>>
>> Subject: [kvm
On Sun, Apr 9, 2023 at 12:00 AM Weiwei Li wrote:
>
> Zdinx/Zhinx{min} require Zfinx. And require relationship is usually done
> by check currently.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/cpu.c | 5 +++-
On 11.04.23 06:11, Eiichi Tsukata wrote:
Use linux specific PR_SET_VMA_ANON_NAME (introduced in v5.17) to set ram
block name in the kernel. This makes each ram block distinguishable and
can help debugging and inspection. The names of ram blocks are shown in
/proc/pid/maps like this:
7f00e9400
On 10.04.23 17:46, Steve Sistare wrote:
Guest RAM created with memory-backend-memfd is aligned to a
QEMU_VMALLOC_ALIGN=2M boundary, and memory-backend-memfd does not support
the "align" parameter to change the default. This is sub-optimal on
aarch64 kernels with a 64 KB page size and 512 MB huge
On 07/04/2023 16.52, Camilla Conte wrote:
When running on the Kubernetes runner, this CI job is timing out.
Raise the limit to give the job enough time to run.
Signed-off-by: Camilla Conte
---
.gitlab-ci.d/buildtest.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.gitlab-ci.d/buildte
Andrew Jones writes:
> On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote:
>> This adds a fairly brain dead torture test for TLB flushes intended
>> for stressing the MTTCG QEMU build. It takes the usual -smp option for
>> multiple CPUs.
>>
>
> BTW, have you tried running these tests
On Tue, Apr 11, 2023 at 09:26:56AM +0100, Alex Bennée wrote:
>
> Andrew Jones writes:
>
> > On Tue, Mar 07, 2023 at 11:28:42AM +, Alex Bennée wrote:
> >> This adds a fairly brain dead torture test for TLB flushes intended
> >> for stressing the MTTCG QEMU build. It takes the usual -smp optio
When reading a non-existent CSR QEMU should raise illegal instruction
exception, but currently it just exits due to the g_assert() check.
This actually reverts commit 0ee342256af9205e7388efdf193a6d8f1ba1a617,
Some comments are also added to indicate that predicate() must be
provided for an impleme
pci_new() automatically retains a reference to a virtual function when
registering it so we need to release the reference when unregistering.
Fixes: 7c0fa8dff8 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
---
hw/pci/pcie_sriov.c | 1 +
1 file ch
On 4/11/23 11:04, Akihiko Odaki wrote:
pci_new() automatically retains a reference to a virtual function when
registering it so we need to release the reference when unregistering.
Fixes: 7c0fa8dff8 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
On Tue, Apr 11, 2023 at 08:43:49AM +0100, Alex Bennée wrote:
>
> Andrew Jones writes:
...
> > Someday mkstandalone could maybe learn how to build
> > a directory hierarchy using the group names, e.g.
> >
> > tests/mttcg/tlb/all_other
>
> So nodefault isn't enough for this?
>
nodefault is enoug
Hi Joe,
> +static int aspeed_i3c_device_ibi_finish(I3CBus *bus)
> +{
> + AspeedI3CDevice *s = ASPEED_I3C_DEVICE(bus->qbus.parent);
> + bool nack_and_disable_hj = ARRAY_FIELD_EX32(s->regs, DEVICE_CTRL,
> + HOT_JOIN_ACK_NACK_CTRL);
> + if (nack
Ping...
On Thu, 6 Apr 2023 15:21:55 +
Lukas Straub wrote:
> Ping? This should go in rc4, there is not much time left to prepare a
> PULL...
>
> Best Regards,
> Lukas Straub
>
> On Tue, 4 Apr 2023 14:36:03 +
> Lukas Straub wrote:
>
> > Since ec6f3ab9, migration with compress enabled w
On Mon, 10 Apr 2023 at 16:34, Richard Henderson
wrote:
>
> The following changes since commit 08dede07030973c1053868bc64de7e10bfa02ad6:
>
> Merge tag 'pull-ppc-20230409' of https://github.com/legoater/qemu into
> staging (2023-04-10 11:47:52 +0100)
>
> are available in the Git repository at:
>
On Tue, 15 Feb 2022 at 09:53, Paolo Bonzini wrote:
>
> These do not depend on --with-default-features, so they become
> booleans in meson too.
Hi; I've just noticed what looks like an unintentional
change in this commit. The subject says it's dealing
with "default-disabled options"...
> Signed-o
On 8/4/23 06:42, Richard Henderson wrote:
The return is by reference, not in 4 integer registers.
This error resulted in
qemu-system-i386: tcg/mips/tcg-target.c.inc:140: \
tcg_target_call_oarg_reg: Assertion `slot >= 0 && slot <= 1' failed.
Fixes: 5427a9a7604 ("tcg: Add TCG_TARGET_CALL
Linux keyring support is protected by CONFIG_KEYUTILS.
We also need CONFIG_SECRET_KEYRING.
Signed-off-by: Juan Quintela
---
- Previous version of this patch changed the meson build rules.
Daniel told me that the proper fix was to change the #ifdef test.
- Change rule again. We need both def
On 7/4/23 21:02, Richard Henderson wrote:
We can arrive here on _WIN64 because Int128 is passed by reference.
Change the assert to check that the immediate is in range,
instead of attempting to check the host ABI.
Fixes: 6a6d772e30d ("tcg: Introduce tcg_out_addi_ptr")
Resolves: https://gitlab.co
On 11/4/23 11:04, Akihiko Odaki wrote:
pci_new() automatically retains a reference to a virtual function when
registering it so we need to release the reference when unregistering.
Fixes: 7c0fa8dff8 ("pcie: Add support for Single Root I/O Virtualization
(SR/IOV)")
Signed-off-by: Akihiko Odaki
On 9/4/23 22:10, Stefan Weil via wrote:
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1529
Signed-off-by: Stefan Weil
---
I suggest to apply the patch for 8.0 because it fixes documentation.
Regards
Stefan W.
docs/system/introduction.rst | 2 +-
1 file changed, 1 insertion(+), 1
On 11/04/2023 11.51, Juan Quintela wrote:
Linux keyring support is protected by CONFIG_KEYUTILS.
We also need CONFIG_SECRET_KEYRING.
Signed-off-by: Juan Quintela
---
- Previous version of this patch changed the meson build rules.
Daniel told me that the proper fix was to change the #ifdef
The efi nic boot rom builds depend on this, they need the
EfiRom utility from edk2 BaseTools.
Fixes: 22e11539e167 ("edk2: replace build scripts")
Reported-by: Olaf Hering
Signed-off-by: Gerd Hoffmann
---
roms/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/roms/Makefile b/roms/M
On Wed, 8 Mar 2023 at 01:14, Michael S. Tsirkin wrote:
>
> From: Jonathan Cameron
>
> The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> Host Bridges if they have only a single root port. Instead, all accesses
> directed to the host bridge (as specified in CXL Fixed Memory
Hi
In this v7:
- Rebased to last upstream
- Rename the capability to a property. So we move all the problems
that we have on last review dissaper because it is not a capability.
So now, it is works as expected. Enabled for old machine types,
disabled for new machine types. Users will only fo
Tue, 11 Apr 2023 12:17:09 +0200 Gerd Hoffmann :
> + python3 edk2-build.py --config edk2-build.config -m none
Is '-m none' correct?
I think previously the result was just a native build.
Now that introduced .config attempts cross builds.
Maybe that detail must be mentioned in the release not
We need to add a new flag to mean to flush at that point.
Notice that we still flush at the end of setup and at the end of
complete stages.
Signed-off-by: Juan Quintela
---
Add missing qemu_fflush(), now it passes all tests always.
---
migration/migration.h | 3 +--
migration/migration.c | 6
We used to flush all channels at the end of each RAM section
sent. That is not needed, so preparing to only flush after a full
iteration through all the RAM.
Default value of the property is false. But we return "true" in
migrate_multifd_flush_after_each_section() until we implement the code
in
We only need to do that on the ram_save_iterate() call on sending and
on destination when we get a RAM_SAVE_FLAG_EOS.
In setup() and complete() we need to synch in both new and old cases,
so don't add a check there.
Signed-off-by: Juan Quintela
Reviewed-by: Dr. David Alan Gilbert
Signed-off-by:
In commit 8461bfdca9c we added the TYPE_AW_I2C_SUN6I, which is a
minor variant of the TYPE_AW_I2C device. However, we didn't quite
get the class hierarchy right. We made the new TYPE_AW_I2C_SUN6I a
subclass of TYPE_SYS_BUS_DEVICE, which means that you can't validly
use a pointer to this object vi
On 1/3/23 15:29, Yuval Shaia wrote:
Guest driver allocates and initialize page tables to be used as a ring
of descriptors for CQ and async events.
The page table that represents the ring, along with the number of pages
in the page table is passed to the device.
Currently our device supports only
On 11/04/2023 12.31, Peter Maydell wrote:
In commit 8461bfdca9c we added the TYPE_AW_I2C_SUN6I, which is a
minor variant of the TYPE_AW_I2C device. However, we didn't quite
get the class hierarchy right. We made the new TYPE_AW_I2C_SUN6I a
subclass of TYPE_SYS_BUS_DEVICE, which means that you c
On 9/4/23 22:05, Stefan Weil via wrote:
Signed-off-by: Stefan Weil
---
The patch does not change code and could also be applied for 8.0.
But not user-facing, so can wait 8.1 :)
Reviewed-by: Philippe Mathieu-Daudé
hw/arm/Kconfig| 2 +-
hw/arm/exynos4210.c | 4 ++--
hw
On 6/4/23 10:00, Thomas De Schampheleire wrote:
The event filename is an absolute path. Convert it to a relative path when
writing '#line' directives, to preserve reproducibility of the generated
output when different base paths are used.
Signed-off-by: Thomas De Schampheleire
---
scripts/tra
On Mon, Dec 05, 2022 at 04:23:35PM +0800, Yaowei Bai wrote:
> In our production environment a guest crashed with this log:
>
> qemu-kvm:
> /home/abuild/rpmbuild/BUILD/qemu-5.0.0/hw/rtc/mc146818rtc.c:201:
> periodic_timer_update: Assertion `lost_clock >= 0' failed.
> 2022-09-26 10:00:28.7
On Tue, Apr 11, 2023 at 12:26:47PM +0200, Olaf Hering wrote:
> Tue, 11 Apr 2023 12:17:09 +0200 Gerd Hoffmann :
>
> > + python3 edk2-build.py --config edk2-build.config -m none
>
> Is '-m none' correct?
Yes. BaseTools are built no matter what because any edk2 stuff
depends on them.
take care,
On 8/4/23 04:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 +---
tcg/i386/tcg-target.c.inc | 8 +++-
2 files changed, 4 insertions(+), 8 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/4/23 04:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h| 6 --
target/i386/tcg/translate.c | 20 ++--
target/s390x/tcg/translate.c | 4 ++--
tcg/optimize.c | 10 --
tcg/tcg.c
In rST markup syntax, the inline markup (*italics*, **bold** and
``monospaced``) must be separated from the surrending text by
non-word characters, otherwise it is not interpreted as markup.
To force interpretation as markup in the middle of a word,
you need to use a backslash-escaped space (which
ping
This patch updates an outdated description in qemu-options.hx .
The patch reflects the changes in qemu behavior already described in
another documentation, and it also changes paragraph structure for
further readability.
The original patch is:
https://patchew.org/QEMU/tyzpr06mb5418d6b0175a4
On 2023/04/11 19:11, Philippe Mathieu-Daudé wrote:
On 11/4/23 11:04, Akihiko Odaki wrote:
pci_new() automatically retains a reference to a virtual function when
registering it so we need to release the reference when unregistering.
Fixes: 7c0fa8dff8 ("pcie: Add support for Single Root I/O
Virt
Am 08.04.2023 um 00:11 hat Lukas Tschoke geschrieben:
> The corruption occurs when a BAT entry aligned to 4096 bytes is changed.
>
> Specifically, the corruption occurs during the creation of the LOG Data
> Descriptor. The incorrect behavior involves copying 4088 bytes from the
> original 4096 byt
Peter Maydell writes:
> In rST markup syntax, the inline markup (*italics*, **bold** and
> ``monospaced``) must be separated from the surrending text by
> non-word characters, otherwise it is not interpreted as markup.
> To force interpretation as markup in the middle of a word,
> you need to u
Am 11.04.2023 um 13:08 hat Kevin Wolf geschrieben:
> Am 08.04.2023 um 00:11 hat Lukas Tschoke geschrieben:
> > The corruption occurs when a BAT entry aligned to 4096 bytes is changed.
> >
> > Specifically, the corruption occurs during the creation of the LOG Data
> > Descriptor. The incorrect beha
在 2023/4/4 上午9:03, Richard Henderson 写道:
+void HELPER(vseteqz_v)(CPULoongArchState *env, uint32_t cd, uint32_t
vj)
+{
+ VReg *Vj = &(env->fpr[vj].vreg);
+ env->cf[cd & 0x7] = (Vj->Q(0) == 0);
+}
+
+void HELPER(vsetnez_v)(CPULoongArchState *env, uint32_t cd, uint32_t
vj)
+{
+ VReg *Vj
On Sun, 9 Apr 2023 22:18:28 +0200
Stefan Weil wrote:
> Signed-off-by: Stefan Weil
Acked-by: Jonathan Cameron
> ---
>
> If my change is okay I suggest to apply the patch for 8.0
> because it fixes documentation.
>
> Regards,
> Stefan W.
>
> docs/system/devices/cxl.rst | 2 +-
> 1 file chan
On Wed, 5 Apr 2023 15:58:31 +0200
David Hildenbrand wrote:
> On 04.04.23 16:36, Peter Xu wrote:
> > On Mon, Apr 03, 2023 at 10:14:21PM +, Alexander Graf wrote:
> >> Add an option for hostmem-file to start the memory object at an offset
> >> into the target file. This is useful if multiple m
Peter Maydell writes:
> In commit 8461bfdca9c we added the TYPE_AW_I2C_SUN6I, which is a
> minor variant of the TYPE_AW_I2C device. However, we didn't quite
> get the class hierarchy right. We made the new TYPE_AW_I2C_SUN6I a
> subclass of TYPE_SYS_BUS_DEVICE, which means that you can't valid
On Tue, Apr 11, 2023 at 11:31:06AM +0100, Peter Maydell wrote:
> In commit 8461bfdca9c we added the TYPE_AW_I2C_SUN6I, which is a
> minor variant of the TYPE_AW_I2C device. However, we didn't quite
> get the class hierarchy right. We made the new TYPE_AW_I2C_SUN6I a
> subclass of TYPE_SYS_BUS_DEV
Signed-off-by: Kevin Wolf
---
The corruption fixed by Lukas is actually trivial reproduce, so let's
add this test case for it along with the fix for 8.0.
tests/qemu-iotests/tests/regression-vhdx-log | 62 +++
.../tests/regression-vhdx-log.out | 14 +
2 files chan
01.04.2023 11:40, Michael Tokarev wrote:
After bringing in xen guest support, qemu fails to build on x32:
target/i386/kvm/xen-emu.c:876:5: note: in expansion of macro ‘qemu_build_assert’
876 | qemu_build_assert(sizeof(struct vcpu_info) == 64);
| ^
This one shou
On 4/7/23 22:52, Taylor Simpson wrote:
Currently, idef-parser skips all floating point instructions. However,
there are some floating point instructions that can be handled.
The following instructions are now parsed
F2_sfimm_p
F2_sfimm_n
F2_dfimm_p
F2_dfimm_n
F2_dfmpy
On Tue, 11 Apr 2023 at 12:57, Michael Tokarev wrote:
>
> 01.04.2023 11:40, Michael Tokarev wrote:
> > After bringing in xen guest support, qemu fails to build on x32:
> >
> > target/i386/kvm/xen-emu.c:876:5: note: in expansion of macro
> > ‘qemu_build_assert’
> >876 | qemu_build_assert(si
On 8/4/23 04:42, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
tcg/tcg-ldst.c.inc | 1 +
1 file changed, 1 insertion(+)
Reviewed-by: Philippe Mathieu-Daudé
Am 06.04.2023 um 22:23 hat Reinoud Zandijk geschrieben:
> On Tue, Apr 04, 2023 at 06:17:45PM +0200, Kevin Wolf wrote:
> > Am 04.04.2023 um 17:07 hat Michael Tokarev geschrieben:
> > > 04.04.2023 16:57, Kevin Wolf пишет:
> > Maybe -snapshot should error out if -blockdev is in use. You'd generally
>
On 8/4/23 04:42, Richard Henderson wrote:
There are several places where we already convert back from
bool to type. Clean things up by using type throughout.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 35 +--
1 file changed, 17 insertion
On 8/4/23 04:42, Richard Henderson wrote:
The new name is slightly more descritive as "data type",
where "extend", despite the c type, sounds like a bool.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c.inc | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
On 8/4/23 04:42, Richard Henderson wrote:
There are several places where we already convert back from
bool to type. Clean things up by using type throughout.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 56 +++
1 file changed, 27 inser
On 8/4/23 04:42, Richard Henderson wrote:
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.c.inc | 24 +---
1 file changed, 13 insertions(+), 11 deletions(-)
Reviewed-by:
On 8/4/23 04:42, Richard Henderson wrote:
We need to set this in TCGLabelQemuLdst, so plumb this
all the way through from tcg_out_op.
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.c.inc | 22 ++
1 file changed, 14 insertions(+), 8 deletions(-)
static voi
On 4/10/23 23:03, Richard Henderson wrote:
On 4/10/23 09:52, Daniel Henrique Barboza wrote:
'static' is defined in the QMP doc as:
"whether a CPU definition is static and will not change depending on
QEMU version, machine type, machine options and accelerator options. A
static model is alway
On 8/4/23 05:03, Richard Henderson wrote:
Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 88 ++-
1 fi
On Tue, 2023-04-04 at 16:04 +0200, Pierre Morel wrote:
> On 4/4/23 14:35, Cédric Le Goater wrote:
> > > > > @@ -0,0 +1,15 @@
> > > > > +/*
> > > > > + * CPU Topology
> > > > > + *
> > > > > + * Copyright IBM Corp. 2022
> > > >
> > > > Shouldn't we have some range : 2022-2023 ?
> > >
> > > There w
On 8/4/23 05:03, Richard Henderson wrote:
Emit all constants that can be loaded in exactly one insn.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 8/4/23 05:03, Richard Henderson wrote:
Emit all constants that can be loaded in exactly one insn.
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target.c.inc | 26 --
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/
On Wed, Apr 5, 2023 at 1:37 PM Eugenio Perez Martin wrote:
>
> Hi!
>
> As mentioned in the last upstream virtio-networking meeting, one of
> the factors that adds more downtime to migration is the handling of
> the guest memory (pin, map, etc). At this moment this handling is
> bound to the virtio
On 11/4/23 12:31, Peter Maydell wrote:
In commit 8461bfdca9c we added the TYPE_AW_I2C_SUN6I, which is a
minor variant of the TYPE_AW_I2C device. However, we didn't quite
get the class hierarchy right. We made the new TYPE_AW_I2C_SUN6I a
subclass of TYPE_SYS_BUS_DEVICE, which means that you can'
Stefan Weil via writes:
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1529
> Signed-off-by: Stefan Weil
Reviewed-by: Alex Bennée
> ---
>
> I suggest to apply the patch for 8.0 because it fixes documentation.
>
> Regards
> Stefan W.
>
> docs/system/introduction.rst | 2 +-
> 1 f
On 11/4/23 12:54, Peter Maydell wrote:
In rST markup syntax, the inline markup (*italics*, **bold** and
``monospaced``) must be separated from the surrending text by
non-word characters, otherwise it is not interpreted as markup.
To force interpretation as markup in the middle of a word,
you need
On 4/11/2023 2:32 AM, Jason Wang wrote:
> 在 2023/4/5 23:38, Steven Sistare 写道:
>> On 4/4/2023 6:00 PM, Philippe Mathieu-Daudé wrote:
>>> On 4/4/23 18:00, Steve Sistare wrote:
When net_init_tap() succeeds for a multi-queue device, it returns a
non-zero ret=1 code to its caller, because of
On Tue, 4 Apr 2023 at 08:45, Feng Jiang wrote:
>
> When 'res' equals -1, the array 's->g_timer.reg.comp[]' is accessed
> out of bounds.
>
> Signed-off-by: Feng Jiang
> ---
> hw/timer/exynos4210_mct.c | 13 -
> 1 file changed, 8 insertions(+), 5 deletions(-)
Only happens if you chang
On Mon, 13 Mar 2023 at 15:11, Fabiano Rosas wrote:
>
> Move the 64-bit CPUs that are TCG-only:
> - cortex-a35
> - cortex-a55
> - cortex-a72
> - cortex-a76
> - a64fx
> - neoverse-n1
>
> Keep the CPUs that can be used with KVM:
> - cortex-a57
> - cortex-a53
> - max
> - host
>
> For the special case
On Sun, 26 Mar 2023 at 21:23, Strahinja Jankovic
wrote:
>
> This patch set introduces basic emulation of Allwinner WDT.
> Since WDT in both A10 and H3 is part of Timer module, the WDT
> functionality is added as an overlay in the memory map.
>
> The focus was to enable reboot functionality, so WDT
On Tue, 11 Apr 2023 at 11:42, Philippe Mathieu-Daudé wrote:
>
> On 9/4/23 22:05, Stefan Weil via wrote:
> > Signed-off-by: Stefan Weil
> > ---
> >
> > The patch does not change code and could also be applied for 8.0.
>
> But not user-facing, so can wait 8.1 :)
>
> Reviewed-by: Philippe Mathieu-Da
On Wed, 5 Apr 2023 at 15:48, ~axelheider wrote:
>
> This patchset fixes the following issues:
> - variable shadowing reported by Coverity
> - fix check, see https://gitlab.com/qemu-project/qemu/-/issues/1491
>
> Axel Heider (2):
> hw/timer/imx_epit: don't shadow variable
> hw/timer/imx_epit: f
On Mon, 10 Apr 2023 at 04:32, Jason Wang wrote:
>
> Commit 1b2b12376c8 ("intel-iommu: PASID support") takes PASID into
> account when calculating iotlb hash like:
>
> static guint vtd_iotlb_hash(gconstpointer v)
> {
> const struct vtd_iotlb_key *key = v;
>
> return key->gfn | ((key->sid) <
Yohei Kojima writes:
> This commit adds the following description:
> 1. `memdev` option is recommended over `mem` option (see [1,2])
> 2. users must specify memory for all NUMA nodes (see [2])
>
> This commit also separates descriptions for `mem` and `memdev` into two
> paragraphs. The old doc
Kevin Wolf writes:
> Am 06.04.2023 um 22:23 hat Reinoud Zandijk geschrieben:
>> On Tue, Apr 04, 2023 at 06:17:45PM +0200, Kevin Wolf wrote:
>> > Am 04.04.2023 um 17:07 hat Michael Tokarev geschrieben:
>> > > 04.04.2023 16:57, Kevin Wolf пишет:
>> > Maybe -snapshot should error out if -blockdev
Philippe Mathieu-Daudé writes:
> This change adds set of boot tests on SBSA-ref machine:
>
> 1. boot firmware up to the EDK2 banner
> 2. boot Alpine Linux
>
> Prebuilt flash volumes are included, built using upstream documentation.
>
> To unify tests for AArch64/virt and AArch64/sbsa-ref we boo
On Fri, 7 Apr 2023 03:37:00 -0400
"Michael S. Tsirkin" wrote:
> On Thu, Apr 06, 2023 at 11:25:47AM +0100, Jonathan Cameron wrote:
> > On Fri, 17 Mar 2023 16:54:36 +
> > Jonathan Cameron via wrote:
> >
> > > Michael Tsirkin raised that we have recently had churn in the
> > > bios-tables-t
On Tue, Apr 11, 2023 at 04:02:19PM +0200, Igor Mammedov wrote:
> PS2:
> Also, I'm working on expanding PCI slots descriptors to PXBs,
> and more or less that will negate this tables split.
Hmm any ETA? We can defer this discussion until after that is posted.
--
MST
On Mon, Apr 10, 2023 at 11:32:08AM +0800, Jason Wang wrote:
> Commit 1b2b12376c8 ("intel-iommu: PASID support") takes PASID into
> account when calculating iotlb hash like:
>
> static guint vtd_iotlb_hash(gconstpointer v)
> {
> const struct vtd_iotlb_key *key = v;
>
> return key->gfn | ((
On 4/11/23 14:09, Michael S. Tsirkin wrote:
On Sun, Apr 09, 2023 at 09:40:22PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to sup
[Reposting due to broken threading in previous post]
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to support x2APIC interrupt remapping. With this
series, we can
This commit refactors apic_mem_read/write to support both MMIO access in
xAPIC and MSR access in x2APIC.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 79 ++--
hw/intc/trace-events | 4 +-
include/hw/i386/apic.h |
This commit extends the APIC ID to 32-bit long and remove the 255 max APIC
ID limit in userspace APIC. The array that manages local APICs is now
dynamically allocated based on the max APIC ID of created x86 machine.
Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC
mode reg
This commit adds support for x2APIC transitions when writing to
MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to
TCG_EXT_FEATURES.
Signed-off-by: Bui Quang Minh
---
hw/intc/apic.c | 50
hw/intc/apic_common.c| 7 ++
On Tue, 11 Apr 2023 10:05:01 -0400
"Michael S. Tsirkin" wrote:
> On Tue, Apr 11, 2023 at 04:02:19PM +0200, Igor Mammedov wrote:
> > PS2:
> > Also, I'm working on expanding PCI slots descriptors to PXBs,
> > and more or less that will negate this tables split.
>
> Hmm any ETA? We can defer th
This commit adds XTSup configuration to let user choose to whether enable
this feature or not. When XTSup is enabled, additional bytes in IRTE with
enabled guest virtual VAPIC are used to support 32-bit destination id.
Additionally, this commit changes to use IVHD type 0x11 in ACPI table for
featu
As userspace APIC now supports x2APIC, intel interrupt remapping
hardware can be set to EIM mode when userspace local APIC is used.
Signed-off-by: Bui Quang Minh
---
hw/i386/intel_iommu.c | 11 ---
1 file changed, 11 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.
On Tue, 11 Apr 2023 at 15:14, Peter Xu wrote:
>
> On Mon, Apr 10, 2023 at 11:32:08AM +0800, Jason Wang wrote:
> > @@ -222,9 +222,9 @@ static guint vtd_iotlb_hash(gconstpointer v)
> > {
> > const struct vtd_iotlb_key *key = v;
> >
> > -return key->gfn | ((key->sid) << VTD_IOTLB_SID_SHIFT)
On Wed, 5 Apr 2023 at 23:06, Richard Henderson
wrote:
>
> On 4/5/23 03:08, Philippe Mathieu-Daudé wrote:
> > Remove unused KVM/Aarch32 definitions.
> >
> > Philippe Mathieu-Daudé (2):
> >target/arm: Remove KVM AArch32 CPU definitions
> >hw/arm/virt: Restrict Cortex-A7 check to TCG
> >
> >
On 4/11/2023 3:57 AM, David Hildenbrand wrote:
> On 10.04.23 17:46, Steve Sistare wrote:
>> Guest RAM created with memory-backend-memfd is aligned to a
>> QEMU_VMALLOC_ALIGN=2M boundary, and memory-backend-memfd does not support
>> the "align" parameter to change the default. This is sub-optimal o
On Wed, 5 Apr 2023 at 08:02, Akihiko Odaki wrote:
>
> When virtualizing SMP system, kvm_arm_init_debug() will be called
> multiple times. Check if the debug feature is already initialized when the
> function is called; otherwise it will overwrite pointers to memory
> allocated with the previous ca
On Wed, 5 Apr 2023 at 16:36, Akihiko Odaki wrote:
>
> kvm_arm_init_debug() used to be called several times on a SMP system as
> kvm_arch_init_vcpu() calls it. Move the call to kvm_arch_init() to make
> sure it will be called only once; otherwise it will overwrite pointers
> to memory allocated wit
On Tue, Apr 11, 2023 at 03:30:08PM +0100, Peter Maydell wrote:
> On Tue, 11 Apr 2023 at 15:14, Peter Xu wrote:
> >
> > On Mon, Apr 10, 2023 at 11:32:08AM +0800, Jason Wang wrote:
> > > @@ -222,9 +222,9 @@ static guint vtd_iotlb_hash(gconstpointer v)
> > > {
> > > const struct vtd_iotlb_key *
On Tue, 28 Mar 2023 11:59:25 -0400
Eric DeVolder wrote:
> Currently ARM QEMU generates, and reports, MADT revision 4. ACPI 6.3
> introduces MADT revision 5.
>
> For MADT revision 5, the GICC structure adds an SPE Overflow Interrupt
> field. This new 2-byte field is created from the existing 3-by
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