On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> This function was created to move the sync between cpu->cfg.ext_N bit
> changes to env->misa_ext* from the validation step to an ealier step,
> giving us a guarantee that we could use either cpu->cfg.ext_N or
> riscv_has_ext(env,N)
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> This CPU is enabling G via cfg.ext_g and, at the same time, setting
> IMAFD in set_misa() and cfg.ext_icsr.
>
> riscv_cpu_validate_set_extensions() is already doing that, so there's no
> need for cpu_init() setups to worry about se
On Thu, Mar 30, 2023 at 3:33 AM Daniel Henrique Barboza
wrote:
>
> We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it
> the same way we did with the others: create a "g" RISCVCPUMisaExtConfig
> property, remove the old "g" property, remove all instances of 'cfg.ext_g'
> and us
This goes along with input pin modification. In some cases it's easier
to know the state of all pins on the GPIO controller before modifying
input pins, rather than knowing only the state of input pins.
For example over QMP:
{"execute":"qom-get","arguments":{
"path":"/machine/soc/gpio[0]",
In cases where the input pin is driven by an entity outside of the
machine, such as a machine the BMC is managing, we need a way to
update the pin state when the external machine drives it.
This allows us to do it via QMP.
For example, to set pin 20 on GPIO controller 0:
{"execute":"qom-set","argu
Hi all,
This series adds a couple QOM properties for retrieving and setting pin
state via qom-get and qom-get.
We ran into a situation in multi-SoC simulation where the BMC would need
to update its input pin state based on behavior from the other SoC. It
made the most sense to expose this over QM
On Thu, Mar 30, 2023 at 3:32 AM Daniel Henrique Barboza
wrote:
>
> The function is now a no-op for all cpu_init() callers that are setting
> a non-zero misa value in set_misa(), since it's no longer used to sync
> cpu->cfg props with env->misa_ext bits. Remove it in those cases.
>
> While we're at
On Thu, Mar 30, 2023 at 3:31 AM Daniel Henrique Barboza
wrote:
>
> Hi,
>
> This new version has a new patch (3) that removes the 'multi_letter'
> attribute from isa_ext_data that became redundant after the changes made
> in patch 2. The change was proposed by Weiwei Li in the v2.
>
> All patches b
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
>
> Add signature and signature-granularity properties in spike to specify the
> target
> signatrue file and the line size for signature data.
>
> Recgonize the signature section between begin_signature and end_signature
> symbols
> when loading el
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).
I don't think this is right, the spec in section 8.6.4 says this:
"MRET then in mstatus/mstatush sets MPV=0, MPP=0,
MIE=MPIE, and MPIE=1"
So i
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I don't think this is right, the spec in section 8.6.4 says this:
Sorry, I didn't find this section i
On 2023/4/6 08:36, Alistair Francis wrote:
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
Add signature and signature-granularity properties in spike to specify the
target
signatrue file and the line size for signature data.
Recgonize the signature section between begin_signature and end_s
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> mstatus.MPP field is a WARL field, so we remain it unchanged if an
Only since version 1.11 of the priv spec and we do still support priv 1.10.
I think it's ok to make this change for all priv versions, as it won't
break any software running 1
On Thu, Apr 6, 2023 at 11:02 AM liweiwei wrote:
>
>
> On 2023/4/6 08:36, Alistair Francis wrote:
> > On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
> >> Add signature and signature-granularity properties in spike to specify the
> >> target
> >> signatrue file and the line size for signature dat
On Wed, Apr 5, 2023 at 7:58 PM Weiwei Li wrote:
>
> ACT tests play an important role in riscv tests. This patch tries to
> add related support to run ACT tests.
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-act-upstream-v2
>
> The ACT tests can be run on qemu-sys
On 2023/4/6 09:26, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
mstatus.MPP field is a WARL field, so we remain it unchanged if an
Only since version 1.11 of the priv spec and we do still support priv 1.10.
I think it's ok to make this change for all priv versio
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
>
>
> On 2023/4/6 08:43, Alistair Francis wrote:
>
> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
>
> The MPP will be set to the least-privileged supported mode (U if
> U-mode is implemented, else M).
>
> I don't think this is right, the spec i
On Sun, Mar 12, 2023 at 10:07 PM Yi Chen wrote:
>
> - Trap satp/hgatp accesses from HS-mode when MSTATUS.TVM is enabled.
> - Trap satp accesses from VS-mode when HSTATUS.VTVM is enabled.
> - Raise RISCV_EXCP_ILLEGAL_INST when U-mode executes SFENCE.VMA/SINVAL.VMA.
> - Raise RISCV_EXCP_VIRT_INSTRUC
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> The RVV verification will error out if fails and it's being done at the
> end of riscv_cpu_validate_set_extensions(), after we've already set some
> extensions that are dependent on RVV. Let's put it in its own function
> and do i
On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
wrote:
>
> This setter is doing nothing else but setting env->vext_ver. Assign the
> value directly.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
> Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Alistair
>
On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
wrote:
>
> The setter is doing nothing special. Just set env->priv_ver directly.
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
> Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> All these generic CPUs are using the latest priv available, at this
> moment PRIV_VERSION_1_12_0:
>
> - riscv_any_cpu_init()
> - rv32_base_cpu_init()
> - rv64_base_cpu_init()
> - rv128_base_cpu_init()
>
> Create a new PRIV_VERSION_
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> We're doing env->priv_spec validation and assignment at the start of
> riscv_cpu_realize(), which is fine, but then we're doing a force disable
> on extensions that aren't compatible with the priv version.
>
> This second step is b
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> Let's remove more code that is open coded in riscv_cpu_realize() and put
> it into a helper. Let's also add an error message instead of just
> asserting out if env->misa_mxl_max != env->misa_mlx.
>
> Signed-off-by: Daniel Henrique
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> There is no need to init timers if we're not even sure that our
> extensions are valid. Execute riscv_cpu_validate_set_extensions() before
> riscv_timer_init().
>
> Signed-off-by: Daniel Henrique Barboza
> Reviewed-by: LIU Zhiwei
On Thu, Mar 30, 2023 at 6:11 AM Daniel Henrique Barboza
wrote:
>
> We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
> ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
> device, which happens to be the parent device of every RISC-V cpu.
>
> The result is
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP will be set to the least-privileged supported mode (U if
U-mode is implemented, else M).
I don't
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
>
>
> On 2023/4/6 09:46, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
> >>
> >> On 2023/4/6 08:43, Alistair Francis wrote:
> >>
> >> On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
> >>
> >> The MPP will be set to t
The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. It's better to have this
kind of information exported to plugin for analysis. As the host insn
size is not determined at guest->IR time, its address is recorded for
later dereference
It's only valid when inline=false, otherwise it's default to 0.
Signed-off-by: Fei Wu
---
contrib/plugins/hotblocks.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/contrib/plugins/hotblocks.c b/contrib/plugins/hotblocks.c
index 062200a7a4..c9716da7
The translation ratio of host to guest instruction count is one of the
key performance factor of binary translation. TCG doesn't collect host
instruction count at present, it does collect host instruction size
instead, although they are not the same thing as instruction size might
not be fixed, ins
On Sat, Mar 25, 2023 at 9:58 PM Richard Henderson
wrote:
>
> From: LIU Zhiwei
>
> Virt enabled state is not a constant. So we should put it into tb flags.
> Thus we can use it like a constant condition at translation phase.
>
> Reported-by: Richard Henderson
> Reviewed-by: Richard Henderson
> S
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP wil
On 2023/4/6 10:24, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
On 2023/4/6 09:46, Alistair Francis wrote:
On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
On 2023/4/6 08:43, Alistair Francis wrote:
On Thu, Mar 30, 2023 at 11:59 PM Weiwei Li wrote:
The MPP wil
>-Original Message-
>From: Michael S. Tsirkin
>Sent: Wednesday, April 5, 2023 3:13 AM
>To: Peter Maydell
>Cc: qemu-devel@nongnu.org; Duan, Zhenzhong
>; Peter Xu ; Jason Wang
>; Marcel Apfelbaum
>; Paolo Bonzini ;
>Richard Henderson ; Eduardo Habkost
>; David Hildenbrand ; Philippe
>Mat
On Thu, Apr 6, 2023 at 1:02 PM liweiwei wrote:
>
>
> On 2023/4/6 10:24, Alistair Francis wrote:
> > On Thu, Apr 6, 2023 at 12:14 PM liweiwei wrote:
> >>
> >> On 2023/4/6 09:46, Alistair Francis wrote:
> >>> On Thu, Apr 6, 2023 at 10:56 AM liweiwei wrote:
> On 2023/4/6 08:43, Alistair Franci
On Mon, Mar 27, 2023 at 04:03:54PM +0800, Yang, Weijiang wrote:
>
> On 3/27/2023 3:33 PM, Christian Ehrhardt wrote:
> > On Thu, Oct 27, 2022 at 2:36 AM Yang, Weijiang
> > wrote:
> > >
> > > On 10/26/2022 7:57 PM, Zhong, Yang wrote:
> > > > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO
Hello
You are so kind to tell me how can I use qmp to send colon character . I
speak about this character :
I tried:
{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift-sem
icolon"}]}}
{"execute":"send-key","arguments":{"keys":[{"type":"qcode","data":"shift","d
ata
Paolo Bonzini writes:
> Coroutine commands have to be declared as coroutine_fn, but the
> marker does not show up in the qapi-comands-* headers; likewise, the
> marshaling function calls the command and therefore must be coroutine_fn.
> Static analysis would want coroutine_fn to match between pro
On Wed, 5 Apr 2023, Igor Mammedov wrote:
> with Q35 using ACPI PCI hotplug by default, user's request to unplug
> device is ignored when it's issued before guest OS has been booted.
> And any additional attempt to request device hot-unplug afterwards
> results in following error:
>
> "Device
Ping ...
On Wed, 29 Mar 2023, Ani Sinha wrote:
> i440fx machine versions 2.3 and newer supports dynamic ram
> resizing. See commit a1666142db6233 ("acpi-build: make ROMs RAM blocks
> resizeable") .
> Currently supported all q35 machine types (versions 2.4 and newer) supports
> resizable RAM/ROM
06.04.2023 00:06, Michael Roth пишет:
..
Re-packaged tarball based on your 7.2.1 tag is now uploaded:
https://www.qemu.org/download/
Thank you Michael! Finally it's there :)
There's one minor caveat still, though: it is missing in the
"Full list of releases" for whatever reason. Dunno ho
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):{ECX,EDX}, which made
SGX enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Yang Zhong
R
On 06/04/2023 08.33, Michael Tokarev wrote:
06.04.2023 00:06, Michael Roth пишет:
..
Re-packaged tarball based on your 7.2.1 tag is now uploaded:
https://www.qemu.org/download/
Thank you Michael! Finally it's there :)
There's one minor caveat still, though: it is missing in the
"Full lis
On 5/4/23 18:42, Taylor Simpson wrote:
Reducing the number of arguments reduces the overhead of the helper
call
Signed-off-by: Taylor Simpson
---
target/hexagon/helper.h| 4 ++--
target/hexagon/translate.h | 1 +
target/hexagon/op_helper.c | 4 ++--
target/hexagon/translate.c | 10 +
06.04.2023 09:48, Thomas Huth пишет:
..>> There's one minor caveat still, though: it is missing in the
"Full list of releases" for whatever reason. Dunno how that
happened, maybe that page hasn't been (re)generated yet.
FWIW, I can see it on https://download.qemu.org/ now.
I still can't, no
On 05/04/2023 17.15, Peter Maydell wrote:
The s390 private runner CI job ubuntu-20.04-s390x-all seems to have
started timing out a lot recently. Here's an example where it passed,
but with only 53 seconds left on the clock before it would have been
killed:
https://gitlab.com/qemu-project/qemu/-/
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