On Thu, Mar 30, 2023 at 6:09 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> The setter is doing nothing special. Just set env->priv_ver directly.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>
> Reviewed-by: Weiwei Li <liwei...@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 29 ++++++++++++-----------------
> 1 file changed, 12 insertions(+), 17 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 19e0a6a902..75c3d4ed22 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl,
> uint32_t ext)
> env->misa_ext_mask = env->misa_ext = ext;
> }
>
> -static void set_priv_version(CPURISCVState *env, int priv_ver)
> -{
> - env->priv_ver = priv_ver;
> -}
> -
> #ifndef CONFIG_USER_ONLY
> static uint8_t satp_mode_from_str(const char *satp_mode_str)
> {
> @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj)
> VM_1_10_SV32 : VM_1_10_SV57);
> #endif
>
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> }
>
> #if defined(TARGET_RISCV64)
> @@ -354,7 +349,7 @@ static void rv64_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV64, 0);
> riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> @@ -364,7 +359,7 @@ static void rv64_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
> #endif
> @@ -376,7 +371,7 @@ static void rv64_sifive_e_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -389,7 +384,7 @@ static void rv64_thead_c906_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_11_0);
> + env->priv_ver = PRIV_VERSION_1_11_0;
>
> cpu->cfg.ext_zfh = true;
> cpu->cfg.mmu = true;
> @@ -423,7 +418,7 @@ static void rv128_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV128, 0);
> riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
> #endif
> @@ -436,7 +431,7 @@ static void rv32_base_cpu_init(Object *obj)
> set_misa(env, MXL_RV32, 0);
> riscv_cpu_add_user_properties(obj);
> /* Set latest version of privileged specification */
> - set_priv_version(env, PRIV_VERSION_1_12_0);
> + env->priv_ver = PRIV_VERSION_1_12_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> #endif
> @@ -446,7 +441,7 @@ static void rv32_sifive_u_cpu_init(Object *obj)
> {
> CPURISCVState *env = &RISCV_CPU(obj)->env;
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
> #endif
> @@ -458,7 +453,7 @@ static void rv32_sifive_e_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -471,7 +466,7 @@ static void rv32_ibex_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_11_0);
> + env->priv_ver = PRIV_VERSION_1_11_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -485,7 +480,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
> RISCVCPU *cpu = RISCV_CPU(obj);
>
> set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
> - set_priv_version(env, PRIV_VERSION_1_10_0);
> + env->priv_ver = PRIV_VERSION_1_10_0;
> cpu->cfg.mmu = false;
> #ifndef CONFIG_USER_ONLY
> set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
> @@ -1113,7 +1108,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> }
>
> if (priv_version >= PRIV_VERSION_1_10_0) {
> - set_priv_version(env, priv_version);
> + env->priv_ver = priv_version;
> }
>
> riscv_cpu_validate_misa_priv(env, &local_err);
> --
> 2.39.2
>
>
