[PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data

We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 118 ++--- 1 file changed, 58 insertions(+), 60

[PATCH v3 12/20] target/riscv: remove cpu->cfg.ext_s

Create a new "s" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVS. Instances of cpu->cfg.ext_s and similar are replaced with riscv_has_ext(env, RVS). Remove the old "s" property and 'ext_s' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 10/20] target/riscv: remove cpu->cfg.ext_e

Create a new "e" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVE. Instances of cpu->cfg.ext_e and similar are replaced with riscv_has_ext(env, RVE). Remove the old "e" property and 'ext_e' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 09/20] target/riscv: remove cpu->cfg.ext_i

Create a new "i" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVI. Instances of cpu->cfg.ext_i and similar are replaced with riscv_has_ext(env, RVI). Remove the old "i" property and 'ext_i' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 11/20] target/riscv: remove cpu->cfg.ext_m

Create a new "m" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVM. Instances of cpu->cfg.ext_m and similar are replaced with riscv_has_ext(env, RVM). Remove the old "m" property and 'ext_m' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 19/20] target/riscv: add RVG and remove cpu->cfg.ext_g

We're still have one RISCVCPUConfig MISA flag, 'ext_g'. We'll remove it the same way we did with the others: create a "g" RISCVCPUMisaExtConfig property, remove the old "g" property, remove all instances of 'cfg.ext_g' and use riscv_has_ext(env, RVG). The caveat is that we don't have RVG, so add i

[PATCH v3 16/20] target/riscv: remove cpu->cfg.ext_v

Create a new "v" RISCVCPUMisaExtConfig property that will update env->misa_ext* with RVV. Instances of cpu->cfg.ext_v and similar are replaced with riscv_has_ext(env, RVV). Remove the old "v" property and 'ext_v' from RISCVCPUConfig. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li

[PATCH v3 02/20] target/riscv: remove MISA properties from isa_edata_arr[]

The code that disables extensions if there's a priv version mismatch uses cpu->cfg.ext_N properties to do its job. We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split the MISA related verifications in a new function, removing it from isa_edata_arr[]. We're also erroring it out i

[PATCH v3 20/20] target/riscv/cpu.c: redesign register_cpu_props()

The function is now a no-op for all cpu_init() callers that are setting a non-zero misa value in set_misa(), since it's no longer used to sync cpu->cfg props with env->misa_ext bits. Remove it in those cases. While we're at it, rename the function to match what it's actually doing: create user pro

Re: Audio playback speed issue on sam460ex and pegasos2

Am 29.03.23 um 14:03 schrieb Rene Engel: After short tests with the command line -audiodev coreaudio,id=audio0,out.frequency=48000 the sound output runs in the correct speed. Tested with one and the same mp3 file under AmigaOs4.1 and MacOs with es1370 and ac97 on Pegasos 2 emulation This in

[PATCH v6 2/9] target/riscv/cpu.c: remove set_vext_version()

This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 7 +-- 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/ta

[PATCH v6 3/9] target/riscv/cpu.c: remove set_priv_version()

The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 29 - 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/riscv/cp

[PATCH v6 9/9] target/riscv: rework write_misa()

write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Our validation is done with riscv_cpu_validate_set_extensions(), but we need a small tweak first. When enabling RVG we're doing: env-

[PATCH v6 1/9] target/riscv/cpu.c: add riscv_cpu_validate_v()

The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(), after we've already set some extensions that are dependent on RVV. Let's put it in its own function and do it earlier. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwe

[PATCH v6 7/9] target/riscv/cpu.c: validate extensions before riscv_timer_init()

There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv/cpu.c | 11 --- 1 file cha

[PATCH v6 0/9] target/riscv: rework CPU extensions validation

Hi, This series contains changes proposed by Weiwei Li in v5. All patches are acked. Changes from v5: - patch 9: - remove ext_ifencei setting from rv64_thead_c906_cpu_init() - v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06740.html Daniel Henrique Barboza (9): target/ri

[PATCH v6 8/9] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init()

We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should a

[PATCH v6 5/9] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers

We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in r

[PATCH v6 4/9] target/riscv: add PRIV_VERSION_LATEST

All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at

[PATCH v6 6/9] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl()

Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza Reviewed-by: LIU Zhiwei Reviewed-by: Weiwei Li --- target/riscv

Re: [PATCH v6 0/9] target/riscv: rework CPU extensions validation

On 3/29/23 17:08, Daniel Henrique Barboza wrote: Hi, This series contains changes proposed by Weiwei Li in v5. All patches are acked. I forgot to mention: this series is based on: "[PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg" Daniel Changes from v5: - patch 9: - remove

Re: [RFC PATCH] tests/avocado: Test Xen guest support under KVM

Alex Bennée writes: > From: David Woodhouse > > Exercise guests with a few different modes for interrupt delivery. In > particular we want to cover: > > • Xen event channel delivery via GSI to the I/O APIC > • Xen event channel delivery via GSI to the i8259 PIC > • MSIs routed to PIRQ event

Re: [RFC PATCH 2/2] virtio-gpu: Add an option to connect all outputs on startup

On 2023/03/08 11:25, Damian Hobson-Garcia wrote: When multiple outputs are enabled using the "max_outputs" attribute, only the first connector appears as "Connected" in the guest DRM device. Additional connectors must be enabled from the host side UI frontend before they are usable by the guest.

Re: Audio playback speed issue on sam460ex and pegasos2

Am 29.03.23 um 21:20 schrieb BALATON Zoltan: On Tue, 28 Mar 2023, Volker Rümelin wrote: it seems your Mac uses a 48kHz sample rate, although QEMU requested a 44.1kHz sample rate. Could you add -audiodev coreaudio,id=audio0,out.frequency=48000 to your command line and test if the playback speed

Re: Audio playback speed issue on sam460ex and pegasos2

On Wed, 29 Mar 2023, Volker Rümelin wrote: Am 29.03.23 um 21:20 schrieb BALATON Zoltan: On Tue, 28 Mar 2023, Volker Rümelin wrote: it seems your Mac uses a 48kHz sample rate, although QEMU requested a 44.1kHz sample rate. Could you add -audiodev coreaudio,id=audio0,out.frequency=48000 to your

[RFC PATCH 0/4] eBPF RSS through QMP support.

This series of patches provides the ability to retrieve eBPF program through qmp, so management application may load bpf blob with proper capabilities. Now, virtio-net devices can accept eBPF programs and maps through properties as external file descriptors. Access to the eBPF map is direct throug

[RFC PATCH 1/5] ebpf: Added eBPF initialization by fds and map update.

Changed eBPF map updates through mmaped array. Mmaped arrays provide direct access to map data. It should omit using bpf_map_update_elem() call, which may require capabilities that are not present. Signed-off-by: Andrew Melnychenko --- ebpf/ebpf_rss-stub.c | 6 +++ ebpf/ebpf_rss.c | 120 +

[RFC PATCH 4/5] qmp: Added new command to retrieve eBPF blob.

Added command "request-ebpf". This command returns eBPF program encoded base64. The program taken from the skeleton and essentially is an ELF object that can be loaded in the future with libbpf. Signed-off-by: Andrew Melnychenko --- monitor/qmp-cmds.c | 17 + qapi/misc.json |

[RFC PATCH 5/5] ebpf: Updated eBPF program and skeleton.

Updated section name, so libbpf should init/gues proper program type without specifications during open/load. Signed-off-by: Andrew Melnychenko --- ebpf/rss.bpf.skeleton.h | 1469 --- tools/ebpf/rss.bpf.c|2 +- 2 files changed, 741 insertions(+), 730 d

[RFC PATCH 3/5] ebpf: Added declaration/initialization routines.

Now, the binary objects may be retrieved by id/name. It would require for future qmp commands that may require specific eBPF blob. Signed-off-by: Andrew Melnychenko --- ebpf/ebpf.c | 48 ebpf/ebpf.h | 25 + ebpf/e

[RFC PATCH 2/5] virtio-net: Added property to load eBPF RSS with fds.

eBPF RSS program and maps may now be passed during initialization. Initially was implemented for libvirt to launch qemu without permissions, and initialized eBPF program through the helper. Signed-off-by: Andrew Melnychenko --- hw/net/virtio-net.c| 77

Re: [PATCH v2 3/5] target/riscv: Sync cpu_pc before update badaddr

On 2023/3/29 23:33, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote: We should sync cpu_pc before storing it into badaddr when mis-aligned exception is triggered. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   target/riscv/insn_trans/trans_rvi.c.inc | 1 +   target/ri

Re: [PATCH v2 4/5] target/riscv: Add support for PC-relative translation

On 2023/3/30 00:27, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote:   static bool trans_auipc(DisasContext *ctx, arg_auipc *a)   { -    gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next); +    assert(ctx->pc_save != -1); +    if (tb_cflags(ctx->base.tb) & CF_PCREL) { +    TCG

Re: [PATCH v2 5/5] target/riscv: Add pointer mask support for instruction fetch

On 2023/3/30 00:36, Richard Henderson wrote: On 3/28/23 20:23, Weiwei Li wrote: Transform the fetch address in cpu_get_tb_cpu_state() when pointer mask for instruction is enabled. Enable PC-relative translation when J is enabled. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   t

Re: [PATCH v3 03/20] target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data

On 2023/3/30 01:28, Daniel Henrique Barboza wrote: We don't have MISA extensions in isa_edata_arr[] anymore. Remove the redundant 'multi_letter' field from isa_ext_data. Suggested-by: Weiwei Li Signed-off-by: Daniel Henrique Barboza --- Reviewed-by: Weiwei Li Weiwei Li target/riscv/cpu

Re: [PATCH v3] linux-user,bsd-user: preserve incoming order of environment variables in the target

On Wed, Mar 29, 2023, 9:00 AM Andreas Schwab wrote: > Do not reverse the order of environment variables in the target environ > array relative to the incoming environ order. Some testsuites depend on a > specific order, even though it is not defined by any standard. > > Signed-off-by: Andreas Sc

[PATCH v11 3/3] tpm: Add support for TPM device over I2C bus

From: Ninad Palsule Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added in the model to tempora

[PATCH v11 0/3] Add support for TPM devices over I2C bus

Hello, Incorporated review comments from Stefan. Please review. This drop adds support for the TPM devices attached to the I2C bus. It only supports the TPM2 protocol. You need to run it with the external TPM emulator like swtpm. I have tested it with swtpm. I have refered to the work done by zhd

[PATCH v11 1/3] docs: Add support for TPM devices over I2C bus

From: Ninad Palsule This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule Reviewed-by: Stefan Berger Reviewed-by: Cédric Le Goater Reviewed

[PATCH v11 2/3] tpm: Extend common APIs to support TPM TIS I2C

From: Ninad Palsule Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C support. The checksum calcu

[PATCH] target/riscv: Set opcode to env->bins for illegal/virtual instruction fault

decode_save_opc() will not work for generate_exception(), since 0 is passed to riscv_raise_exception() as pc in helper_raise_exception(), and bins will not be restored in this case. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvh.c.inc | 2 ++ 1 file

Re: [PATCH 1/2] tests/requirements.txt: bump up avocado-framework version to 101.0

Hi, On 2023-03-27 07:50:29, Kautuk Consul wrote: > Avocado version 101.0 has a fix to re-compute the checksum > of an asset file if the algorithm used in the *-CHECKSUM > file isn't the same as the one being passed to it by the > avocado user (i.e. the avocado_qemu python module). > In the earlier

Re: [PATCH for 8.1 v2 4/6] vdpa: return errno in vhost_vdpa_get_vring_group error

On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote: > > We need to tell in the caller, as some errors are expected in a normal > workflow. In particular, parent drivers in recent kernels with > VHOST_BACKEND_F_IOTLB_ASID may not support vring groups. In that case, > -ENOTSUP is returned. > > Th

Re: [PATCH for 8.1 v2 3/6] vdpa: add vhost_vdpa_set_dev_features_fd

On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote: > > This allows to set the features of a vhost-vdpa device from external > subsystems like vhost-net. It is used in subsequent patches to > negotiate features and probe for CVQ ASID isolation. > > Reviewed-by: Stefano Garzarella > Signed-off-b

Re: [PATCH for 8.1 v2 5/6] vdpa: move CVQ isolation check to net_init_vhost_vdpa

On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote: > > Evaluating it at start time instead of initialization time may make the > guest capable of dynamically adding or removing migration blockers. > > Also, moving to initialization reduces the number of ioctls in the > migration, reducing failur

Re: [PATCH for 8.1 v2 5/6] vdpa: move CVQ isolation check to net_init_vhost_vdpa

On Thu, Mar 30, 2023 at 2:20 PM Jason Wang wrote: > > On Fri, Mar 24, 2023 at 3:54 AM Eugenio Pérez wrote: > > > > Evaluating it at start time instead of initialization time may make the > > guest capable of dynamically adding or removing migration blockers. > > > > Also, moving to initialization

Re: [RFC PATCH 1/5] ebpf: Added eBPF initialization by fds and map update.

On Thu, Mar 30, 2023 at 8:33 AM Andrew Melnychenko wrote: > > Changed eBPF map updates through mmaped array. > Mmaped arrays provide direct access to map data. > It should omit using bpf_map_update_elem() call, > which may require capabilities that are not present. This requires kernel support, s

Re: [RFC PATCH 3/5] ebpf: Added declaration/initialization routines.

On Thu, Mar 30, 2023 at 8:33 AM Andrew Melnychenko wrote: > > Now, the binary objects may be retrieved by id/name. > It would require for future qmp commands that may require specific > eBPF blob. > > Signed-off-by: Andrew Melnychenko > --- > ebpf/ebpf.c | 48 +++

Re: [RFC PATCH 1/5] ebpf: Added eBPF initialization by fds and map update.

On Thu, Mar 30, 2023 at 2:53 PM Jason Wang wrote: > > On Thu, Mar 30, 2023 at 8:33 AM Andrew Melnychenko wrote: > > > > Changed eBPF map updates through mmaped array. > > Mmaped arrays provide direct access to map data. > > It should omit using bpf_map_update_elem() call, > > which may require ca

Re: [RFC PATCH 0/4] eBPF RSS through QMP support.

On Thu, Mar 30, 2023 at 8:33 AM Andrew Melnychenko wrote: > > This series of patches provides the ability to retrieve eBPF program > through qmp, so management application may load bpf blob with proper > capabilities. > Now, virtio-net devices can accept eBPF programs and maps through properties

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