On 3/29/23 17:08, Daniel Henrique Barboza wrote:
Hi, This series contains changes proposed by Weiwei Li in v5. All patches are acked.
I forgot to mention: this series is based on: "[PATCH v3 00/20] remove MISA ext_N flags from cpu->cfg" Daniel
Changes from v5: - patch 9: - remove ext_ifencei setting from rv64_thead_c906_cpu_init() - v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg06740.html Daniel Henrique Barboza (9): target/riscv/cpu.c: add riscv_cpu_validate_v() target/riscv/cpu.c: remove set_vext_version() target/riscv/cpu.c: remove set_priv_version() target/riscv: add PRIV_VERSION_LATEST target/riscv/cpu.c: add priv_spec validate/disable_exts helpers target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() target/riscv/cpu.c: validate extensions before riscv_timer_init() target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() target/riscv: rework write_misa() target/riscv/cpu.c | 330 +++++++++++++++++++++++++++------------------ target/riscv/cpu.h | 3 + target/riscv/csr.c | 47 +++---- 3 files changed, 221 insertions(+), 159 deletions(-)
