Hi Peter
On Tue, Mar 28, 2023 at 6:39 PM Peter Maydell wrote:
>
> The msys CI runners have started failing to compile with an EGL
> related error:
>
> https://gitlab.com/qemu-project/qemu/-/jobs/4015682307
>
> In file included from
> C:/GitLab-Runner/builds/qemu-project/qemu/msys64/mingw64/includ
On 29/03/2023 09.01, Marc-André Lureau wrote:
Hi Peter
On Tue, Mar 28, 2023 at 6:39 PM Peter Maydell wrote:
The msys CI runners have started failing to compile with an EGL
related error:
https://gitlab.com/qemu-project/qemu/-/jobs/4015682307
In file included from
C:/GitLab-Runner/builds/qem
On Wed, Mar 29, 2023 at 11:01:35AM +0400, Marc-André Lureau wrote:
> Hi Peter
>
> On Tue, Mar 28, 2023 at 6:39 PM Peter Maydell
> wrote:
> >
> > The msys CI runners have started failing to compile with an EGL
> > related error:
> >
> > https://gitlab.com/qemu-project/qemu/-/jobs/4015682307
> >
>
Hi Dorinda,
On Tue, Mar 28, 2023 at 5:08 PM Dorinda Bassey wrote:
>
> This commit adds a new audiodev backend to allow QEMU to use Pipewire as
> both an audio sink and source. This backend is available on most systems
>
> Add Pipewire entry points for QEMU Pipewire audio backend
> Add wrappers fo
On 29/03/2023 10.07, Daniel P. Berrangé wrote:
On Wed, Mar 29, 2023 at 11:01:35AM +0400, Marc-André Lureau wrote:
Hi Peter
On Tue, Mar 28, 2023 at 6:39 PM Peter Maydell wrote:
The msys CI runners have started failing to compile with an EGL
related error:
https://gitlab.com/qemu-project/qemu
On 2023/3/28 06:49, Daniel Henrique Barboza wrote:
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related verifications in a new function, removing
On 2023/3/29 01:35, Daniel Henrique Barboza wrote:
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs
On 28/03/2023 19.02, Philippe Mathieu-Daudé wrote:
On 20/3/23 17:58, Nathan Chancellor wrote:
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
On 23/2/23 17:19, Jiaxun Yang wrote:
145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps") con
On 2023/3/29 01:35, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Our validation is done with riscv_cpu_validate_set_extensions(), but we
need a small tw
This is a very rough and ready first pass at comparing gcovr's json
output between two different runs. At the moment it will give you a
file level diff between two runs but hopefully it wont be too hard to
extend to give better insight.
After generating the coverage results you run with something
On 2023/3/29 00:54, Irina Ryapolova wrote:
According to specification:
For Sv39x4, address bits of the guest physical address 63:41 must all be zeros,
or else a
guest-page-fault exception occurs.
Likewise for Sv48x4 and Sv57x4.
For Sv48x4 address bits 63:50 must all be zeros, or else a guest-
On 230214 1148, Mauro Matteo Cascella wrote:
> Hi Philippe,
>
> On Mon, Feb 13, 2023 at 7:26 PM Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Mauro,
> >
> > On 13/2/23 18:41, Mauro Matteo Cascella wrote:
> > > The guest can control the size of buf; an OOB write occurs when buf is 1
> > > or 2
> > >
On 230213 1841, Mauro Matteo Cascella wrote:
> The guest can control the size of buf; an OOB write occurs when buf is 1 or 2
> bytes long. Only fill in the buffer as long as there is enough space, throw
> away any data which doesn't fit.
>
> Signed-off-by: Mauro Matteo Cascella
Tested-by: Alexan
在 2023/3/29 上午3:59, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
+ func(mop, vd_ofs, vj_ofs, vk_ofs, 16, 16);
Oh, reading about ASXD and 256-bit vectors makes me wonder if it would
be better to plan ahead and have a function, or DisasContext member,
for the length of the vect
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 4 ++--
1 file changed, 2 ins
On Wed, 29 Mar 2023 at 09:20, Thomas Huth wrote:
> I'm not a fan of 'allow-failure: true' - that basically means nobody will
> look at the failing jobs, so we could rather disable the jobs by default
> instead (and just run them manually when you want to have a look at them).
Mmm; in fact I think
On 03/03/2023 17.07, Daniel P. Berrangé wrote:
Currently meson registers a single test that invokes an entire group of
I/O tests, hiding the test granularity from meson. There are various
downsides of doing this
* You cannot ask 'meson test' to invoke a single I/O test
* The meson test timeo
On Tue, Mar 28, 2023 at 19:14:26 +0200, Philippe Mathieu-Daudé wrote:
> This change adds set of boot tests on SBSA-ref machine:
>
> 1. boot firmware up to the EDK2 banner
> 2. boot Alpine Linux
>
> Prebuilt flash volumes are included, built using upstream documentation.
>
> To unify tests for AA
Do not reverse the order of envionment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab
---
linux-user/main.c | 7 ++-
1 file changed, 6 inse
On Wed, Mar 29, 2023 at 12:47:51PM +0200, Thomas Huth wrote:
> On 03/03/2023 17.07, Daniel P. Berrangé wrote:
> > Currently meson registers a single test that invokes an entire group of
> > I/O tests, hiding the test granularity from meson. There are various
> > downsides of doing this
> >
> > *
On 29/03/2023 13.18, Daniel P. Berrangé wrote:
On Wed, Mar 29, 2023 at 12:47:51PM +0200, Thomas Huth wrote:
On 03/03/2023 17.07, Daniel P. Berrangé wrote:
Currently meson registers a single test that invokes an entire group of
I/O tests, hiding the test granularity from meson. There are various
On Wed, 29 Mar 2023 at 05:24, Alex Bennée wrote:
>
> This is a very rough and ready first pass at comparing gcovr's json
> output between two different runs. At the moment it will give you a
> file level diff between two runs but hopefully it wont be too hard to
> extend to give better insight.
>
On 29/3/23 13:04, Andreas Schwab wrote:
Do not reverse the order of envionment variables in the target environ
"environment"
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab
On 3/28/23 23:11, John Snow wrote:
+# Is it a problem if we front-load this now and run it again later?
I would just move all the "pip install" bits after configure has called
out to git-submodule.sh.
+# --no-build-isolation was added to pip 10.0.
+# --no-use-pep517 was adde
The 'check' script will use "#!/usr/bin/env python3" by default
to locate python, but this doesn't work in distros which lack a
bare 'python3' binary like NetBSD.
We need to explicitly invoke 'check' by referring to the 'python'
variable in meson, which resolves to the detected python binary
that
Currently our NetBSD VM recipe requests instal of the python37 package
and explicitly tells QEMU to use that version of python. Since the
NetBSD base ISO was updated to version 9.3 though, the default system
python version is 3.9 which is sufficiently new for QEMU to rely on.
Rather than requesting
On Tue, Mar 28, 2023 at 05:11:19PM -0400, John Snow wrote:
> This patch changes how we detect and install meson.
>
> This patch creates a lightweight Python virtual environment using the
> user's configured $python that inherits system packages. If Meson is
> installed there and meets our minimum
On 3/28/23 23:11, John Snow wrote:
+# venv class is cute and toggles this off before post_setup,
+# but we need it to decide if we want to generate shims or not.
Ha, yeah that's a bug in the venv package. post_setup() can already run
with system_site_packages reverted to True.
On 3/29/23 00:19, Michael S. Tsirkin wrote:
Hmm I don't think we can reasonably make such a change for 8.0.
Seems too risky.
Also, I feel we want to have an internal (with "x-" prefix") flag to
revert to old behaviour, in case of breakage on some guests. and maybe
we want to keep old revision
On 29/3/23 14:45, Daniel P. Berrangé wrote:
The 'check' script will use "#!/usr/bin/env python3" by default
to locate python, but this doesn't work in distros which lack a
bare 'python3' binary like NetBSD.
We need to explicitly invoke 'check' by referring to the 'python'
variable in meson, whic
On 29/3/23 14:46, Daniel P. Berrangé wrote:
Currently our NetBSD VM recipe requests instal of the python37 package
and explicitly tells QEMU to use that version of python. Since the
NetBSD base ISO was updated to version 9.3 though, the default system
python version is 3.9 which is sufficiently n
On 3/29/23 00:03, Michael S. Tsirkin wrote:
On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote:
Currently i386 QEMU generates MADT revision 3, and reports
MADT revision 1. ACPI 6.3 introduces MADT revision 5.
For MADT revision 4, that introduces ARM GIC structures, which do
not ap
On 3/29/23 08:16, Eric DeVolder wrote:
On 3/29/23 00:03, Michael S. Tsirkin wrote:
On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote:
Currently i386 QEMU generates MADT revision 3, and reports
MADT revision 1. ACPI 6.3 introduces MADT revision 5.
For MADT revision 4, that intr
On 3/29/23 14:53, Daniel P. Berrangé wrote:
I would love to see a day where configure isn't involved in the
build process. Obviously we can't put this new logic into
meson as its a chicken & egg problem. Could we potentially
have your new python/scripts/mkvenv.py script be responsible
for settin
On Wed, Mar 29, 2023 at 03:27:53PM +0200, Paolo Bonzini wrote:
> On 3/29/23 14:53, Daniel P. Berrangé wrote:
> > I would love to see a day where configure isn't involved in the
> > build process. Obviously we can't put this new logic into
> > meson as its a chicken & egg problem. Could we potential
Nick,
> +case POWERPC_EXCP_HV_EMU:
> +env->spr[SPR_HEIR] = insn;
> +if (is_prefix_excp(env, insn)) {
> +uint32_t insn2 = ppc_ldl_code(env, env->nip + 4);
> +env->spr[SPR_HEIR] |= (uint64_t)insn2 << 32;
Are inst and inst2 in the right locations here? I t
On Tue, 28 Mar 2023 at 23:58, Richard Henderson
wrote:
>
> The following changes since commit d37158bb2425e7ebffb167d611be01f1e9e6c86f:
>
> Update version for v8.0.0-rc2 release (2023-03-28 20:43:21 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags
Thanks for posting this!
On 3/28/23 23:11, John Snow wrote:
This series is in RFC state; some notable things:
- So far, only meson is included in this setup.
- There's a ton of debugging prints everywhere. It's extremely chatty right now.
- Sphinx and qemu.qmp are not yet included in this venv.
What's the status of this patch ? It was acked 2 months ago but
AFAICT it was never merged.
On Mon, Jan 23, 2023 at 10:42:06PM +0200, Konstantin Kostiuk wrote:
> Reviewed-by: Konstantin Kostiuk
>
> On Mon, Jan 23, 2023 at 3:31 PM Kfir Manor wrote:
>
> > Signed-off-by: Kfir Manor
> > ---
> >
Add 16z069 Watchdog over MEN Chameleon BUS emulation.
Signed-off-by: Johannes Thumshirn
---
hw/watchdog/Kconfig | 5 +
hw/watchdog/meson.build | 1 +
hw/watchdog/wdt_z069.c | 218
3 files changed, 224 insertions(+)
create mode 100644 hw/watchdog
Add emulation of MEN Chameleon Hardware to Qemu.
This emulation is specifically designed to test the upstream Linux kernel
drivers when one has no access to the hardware.
The emulation consists of the bus itself, a PCI hardware target creating the
bus, MEN Micro Electronic's 8250 based UART via MC
Also ensure all pending AIO is complete.
Signed-off-by: Mark Syms
---
hw/block/dataplane/xen-block.c | 16
1 file changed, 16 insertions(+)
diff --git a/hw/block/dataplane/xen-block.c b/hw/block/dataplane/xen-block.c
index 734da42ea7..067f8e2f45 100644
--- a/hw/block/dataplane/
On 3/29/23 14:45, Daniel P. Berrangé wrote:
The 'check' script will use "#!/usr/bin/env python3" by default
to locate python, but this doesn't work in distros which lack a
bare 'python3' binary like NetBSD.
We need to explicitly invoke 'check' by referring to the 'python'
variable in meson, whic
On 3/29/23 14:46, Daniel P. Berrangé wrote:
Currently our NetBSD VM recipe requests instal of the python37 package
and explicitly tells QEMU to use that version of python. Since the
NetBSD base ISO was updated to version 9.3 though, the default system
python version is 3.9 which is sufficiently n
Do not reverse the order of environment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab
---
linux-user/main.c | 6 ++
1 file changed, 6 inse
Philippe Mathieu-Daudé writes:
> Both cpu_check_watchpoint() and cpu_watchpoint_address_matches()
> are specific to TCG system emulation. Declare them in "tcg-cpu-ops.h"
> to be sure accessing them from non-TCG code is a compilation error.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
Philippe Mathieu-Daudé writes:
> cpu_watchpoint_insert() calls error_report() which is declared
> in "qemu/error-report.h". When moving this code in commit 2609ec2868
> ("softmmu: Extract watchpoint API from physmem.c") we neglected to
> include this header. This works so far because it is indire
On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
> Do not reverse the order of environment variables in the target environ
> array relative to the incoming environ order. Some testsuites depend on a
> specific order, even though it is not defined by any standard.
>
> Signed-off-by:
The MEN Chameleon Bus (MCB) is an on-chip bus system exposing IP Cores of an
FPGA to a outside bus system like PCIe.
Signed-off-by: Johannes Thumshirn
---
MAINTAINERS | 6 ++
hw/Kconfig | 1 +
hw/mcb/Kconfig | 2 +
hw/mcb/mcb.c | 182 +++
Philippe Mathieu-Daudé writes:
> CPU watchpoints can be use by non-TCG accelerators.
>
> KVM uses them:
>
> $ git grep CPUWatchpoint|fgrep kvm
> target/arm/kvm64.c:1558:CPUWatchpoint *wp = find_hw_watchpoint(cs,
> debug_exit->far);
> target/i386/kvm/kvm.c:5216:static CPUWatchpoint
On 29/3/23 16:00, Daniel P. Berrangé wrote:
On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
Do not reverse the order of environment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not def
If the Xen PV guest VM sends a close whilst there is outstanding I/O
being processed that IO needs to be completed and drained before
unrealizing the rings or SEGVs will occurr when the I/O does complete
and tries to update an already unmapped grant entry.
Add PCI based MEN Chameleon Bus carrier emulation.
Signed-off-by: Johannes Thumshirn
---
hw/mcb/Kconfig | 6 +
hw/mcb/mcb-pci.c | 307 +
hw/mcb/meson.build | 1 +
3 files changed, 314 insertions(+)
create mode 100644 hw/mcb/mcb-pci.c
diff -
Add MEN z125 UART over MEN Chameleon Bus emulation.
Signed-off-by: Johannes Thumshirn
---
hw/char/Kconfig | 6 +++
hw/char/meson.build | 1 +
hw/char/serial-mcb.c | 115 +++
3 files changed, 122 insertions(+)
create mode 100644 hw/char/serial-mc
On Mär 29 2023, Daniel P. Berrangé wrote:
> On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
>> Do not reverse the order of environment variables in the target environ
>> array relative to the incoming environ order. Some testsuites depend on a
>> specific order, even though it is
On Wed, Mar 29, 2023 at 04:04:43PM +0200, Andreas Schwab wrote:
> On Mär 29 2023, Daniel P. Berrangé wrote:
>
> > On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
> >> Do not reverse the order of environment variables in the target environ
> >> array relative to the incoming environ
On 22/3/23 18:55, Titus Rwantare wrote:
Devices models calling pmbus_send_string can't be relied upon to
send a non-zero pointer. This logs an error and doesn't segfault.
Reviewed-by: Patrick Venture
Signed-off-by: Titus Rwantare
---
hw/i2c/pmbus_device.c | 7 +++
1 file changed, 7 inse
Signed-off-by: Marco Liebel
---
tests/docker/dockerfiles/debian-hexagon-cross.docker | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
b/tests/docker/dockerfiles/debian-hexagon-cross.docker
index 5308ccb8fe..b99d99f943 100644
On Wed, Mar 29, 2023, 4:00 PM Daniel P. Berrangé
wrote:
> On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
> > Do not reverse the order of environment variables in the target environ
> > array relative to the incoming environ order. Some testsuites depend on
> a
> > specific order
On Mär 29 2023, Philippe Mathieu-Daudé wrote:
> On 29/3/23 16:00, Daniel P. Berrangé wrote:
>> On Wed, Mar 29, 2023 at 03:55:13PM +0200, Andreas Schwab wrote:
>>> Do not reverse the order of environment variables in the target environ
>>> array relative to the incoming environ order. Some testsui
On 3/28/23 22:58, Bui Quang Minh wrote:
On 3/27/23 23:49, David Woodhouse wrote:
On Mon, 2023-03-27 at 23:35 +0700, Bui Quang Minh wrote:
On 3/27/23 23:22, David Woodhouse wrote:
On Mon, 2023-03-27 at 22:45 +0700, Bui Quang Minh wrote:
Maybe I'm misreading the patch, but to me it looks that
On 3/29/23 03:19, Weiwei Li wrote:
Function get_physical_address() translates both virtual address and
guest physical address, and the latter is 34-bits for Sv32x4. So we
should use vaddr type for 'addr' parameter.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_help
> -Original Message-
> From: qemu-devel-bounces+bcain=quicinc@nongnu.org bounces+bcain=quicinc@nongnu.org> On Behalf Of Marco Liebel
> Sent: Wednesday, March 29, 2023 9:21 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Marco Liebel (QUIC)
>
> Subject: [PATCH] Use hexagon
Do not reverse the order of environment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab
---
bsd-user/main.c | 10 +-
linux-user/main.c
On 3/29/23 05:32, liweiwei wrote:
On 2023/3/28 06:49, Daniel Henrique Barboza wrote:
The code that disables extensions if there's a priv version mismatch
uses cpu->cfg.ext_N properties to do its job.
We're aiming to not rely on cpu->cfg.ext_N props for MISA bits. Split
the MISA related veri
On 3/29/23 02:59, gaosong wrote:
在 2023/3/29 上午3:59, Richard Henderson 写道:
On 3/27/23 20:05, Song Gao wrote:
+ func(mop, vd_ofs, vj_ofs, vk_ofs, 16, 16);
Oh, reading about ASXD and 256-bit vectors makes me wonder if it would be better to plan
ahead and have a function, or DisasContext me
On 3/28/23 20:24, gaosong wrote:
I also think we could make use of (__typeof(Vd->E1(0))) instead of separately passing
the output type? It would appear to be less error-prone.
I will try this on v3.
Consider using local typedefs, e.g.
typedef __typeof(Vd->E1(0)) TD;
r~
On 3/29/23 21:53, Bui Quang Minh wrote:
On 3/28/23 22:58, Bui Quang Minh wrote:
On 3/27/23 23:49, David Woodhouse wrote:
On Mon, 2023-03-27 at 23:35 +0700, Bui Quang Minh wrote:
On 3/27/23 23:22, David Woodhouse wrote:
On Mon, 2023-03-27 at 22:45 +0700, Bui Quang Minh wrote:
Maybe I'm misr
On 3/28/23 20:23, Weiwei Li wrote:
We should sync cpu_pc before storing it into badaddr when mis-aligned
exception is triggered.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/insn_trans/trans_rvi.c.inc | 1 +
target/riscv/translate.c| 1 +
2 files c
On 3/28/23 12:02, Philippe Mathieu-Daudé wrote:
> On 20/3/23 17:58, Nathan Chancellor wrote:
>> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
>>> On 23/2/23 17:19, Jiaxun Yang wrote:
145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegi
On 23/3/23 11:05, Philippe Mathieu-Daudé wrote:
Hi Alex, Paolo,
On 7/3/23 22:21, Alex Bennée wrote:
Now we have removed any target specific bits from the core gdbstub
code we only need to build it twice. We have to jump a few meson hoops
to manually define the CONFIG_USER_ONLY symbol but it see
On 29/3/23 18:09, Rob Landley wrote:
On 3/28/23 12:02, Philippe Mathieu-Daudé wrote:
On 20/3/23 17:58, Nathan Chancellor wrote:
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
On 23/2/23 17:19, Jiaxun Yang wrote:
145e2198d749 ("hw/mips/gt64xxx_pci: Endian-swap using PC
On 29/3/23 17:00, Andreas Schwab wrote:
Do not reverse the order of environment variables in the target environ
array relative to the incoming environ order. Some testsuites depend on a
specific order, even though it is not defined by any standard.
Signed-off-by: Andreas Schwab
---
bsd-user/
It is pointless to build libgdb_user.fa in a system-only build
(or libgdb_softmmu.fa in a user-only build). Besides, in some
restricted build configurations, some APIs might be restricted /
not available. Example in a KVM-only builds where TCG is disabled:
$ ninja qemu-system-x86_64
[99/2187]
On 3/29/23 03:55, Thomas Huth wrote:
> On 28/03/2023 19.02, Philippe Mathieu-Daudé wrote:
>> On 20/3/23 17:58, Nathan Chancellor wrote:
>>> On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
On 23/2/23 17:19, Jiaxun Yang wrote:
> 145e2198d749 ("hw/mips/gt64xxx_pci:
Le 28/03/2023 à 14:22, Luca Bonissi a écrit :
On 28/03/23 13:55, Thomas Huth wrote:
On 28/03/2023 13.48, Luca Bonissi wrote:
--- qemu-20230327/linux-user/syscall_defs.h 2023-03-27 15:41:42.0
+0200
+++ qemu-20230327/linux-user/syscall_defs.h.new 2023-03-27
21:43:25.615115126 +020
On 3/28/23 20:23, Weiwei Li wrote:
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
-gen_set_gpri(ctx, a->rd, a->imm + ctx->base.pc_next);
+assert(ctx->pc_save != -1);
+if (tb_cflags(ctx->base.tb) & CF_PCREL) {
+TCGv target_pc = tcg_temp_new();
dest_gpr(s, a->r
On 3/29/23 11:07, Philippe Mathieu-Daudé wrote:
> On 29/3/23 18:09, Rob Landley wrote:
>> On 3/28/23 12:02, Philippe Mathieu-Daudé wrote:
>>> On 20/3/23 17:58, Nathan Chancellor wrote:
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
> On 23/2/23 17:19, Jiaxun Yan
Marco Liebel writes:
> Signed-off-by: Marco Liebel
> ---
> tests/docker/dockerfiles/debian-hexagon-cross.docker | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/docker/dockerfiles/debian-hexagon-cross.docker
> b/tests/docker/dockerfiles/debian-hexagon-cross.docke
On 3/28/23 20:23, Weiwei Li wrote:
Transform the fetch address in cpu_get_tb_cpu_state() when pointer
mask for instruction is enabled.
Enable PC-relative translation when J is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c| 4
target/risc
On 3/29/23 09:18, Philippe Mathieu-Daudé wrote:
It is pointless to build libgdb_user.fa in a system-only build
(or libgdb_softmmu.fa in a user-only build). Besides, in some
restricted build configurations, some APIs might be restricted /
not available. Example in a KVM-only builds where TCG is di
> -Original Message-
> From: Alex Bennée
> Sent: Wednesday, March 29, 2023 10:34 AM
> To: Marco Liebel (QUIC)
> Cc: Taylor Simpson ; qemu-devel@nongnu.org
> Subject: Re: [PATCH] Use hexagon toolchain version 16.0.0
>
> Marco Liebel writes:
>
> > Signed-off-by: Marco Liebel
> > ---
>
On Wed, Mar 29, 2023 at 08:14:37AM -0500, Eric DeVolder wrote:
>
>
> On 3/29/23 00:19, Michael S. Tsirkin wrote:
> > Hmm I don't think we can reasonably make such a change for 8.0.
> > Seems too risky.
> > Also, I feel we want to have an internal (with "x-" prefix") flag to
> > revert to old beha
On Wed, Mar 29, 2023 at 08:19:22AM -0500, Eric DeVolder wrote:
>
>
> On 3/29/23 08:16, Eric DeVolder wrote:
> >
> >
> > On 3/29/23 00:03, Michael S. Tsirkin wrote:
> > > On Tue, Mar 28, 2023 at 11:59:26AM -0400, Eric DeVolder wrote:
> > > > Currently i386 QEMU generates MADT revision 3, and rep
Philippe Mathieu-Daudé writes:
> It is pointless to build libgdb_user.fa in a system-only build
> (or libgdb_softmmu.fa in a user-only build). Besides, in some
> restricted build configurations, some APIs might be restricted /
> not available. Example in a KVM-only builds where TCG is disabled:
Daniel P. Berrangé writes:
> The 'check' script will use "#!/usr/bin/env python3" by default
> to locate python, but this doesn't work in distros which lack a
> bare 'python3' binary like NetBSD.
>
> We need to explicitly invoke 'check' by referring to the 'python'
> variable in meson, which re
Daniel P. Berrangé writes:
> Currently our NetBSD VM recipe requests instal of the python37 package
> and explicitly tells QEMU to use that version of python. Since the
> NetBSD base ISO was updated to version 9.3 though, the default system
> python version is 3.9 which is sufficiently new for
On 29/3/23 18:48, Rob Landley wrote:
On 3/29/23 11:07, Philippe Mathieu-Daudé wrote:
On 29/3/23 18:09, Rob Landley wrote:
On 3/28/23 12:02, Philippe Mathieu-Daudé wrote:
On 20/3/23 17:58, Nathan Chancellor wrote:
On Wed, Mar 08, 2023 at 12:33:38AM +0100, Philippe Mathieu-Daudé wrote:
On 23
When riscv_cpu_realize() starts we're guaranteed to have cpu->cfg.ext_N
properties updated. The same can't be said about env->misa_ext*, since
the user might enable/disable MISA extensions in the command line, and
env->misa_ext* won't caught these changes. The current solution is to
sync everything
Ever since RISCVCPUConfig got introduced users are able to set CPU extensions
in the command line. User settings are reflected in the cpu->cfg object
for later use. These properties are used in the target/riscv/cpu.c code,
most notably in riscv_cpu_validate_set_extensions(), where most of our
reali
Create a new "f" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVF. Instances of cpu->cfg.ext_f and similar are
replaced with riscv_has_ext(env, RVF).
Remove the old "f" property and 'ext_f' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "a" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVA. Instances of cpu->cfg.ext_a and similar are
replaced with riscv_has_ext(env, RVA).
Remove the old "a" property and 'ext_a' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "c" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVC. Instances of cpu->cfg.ext_c and similar are
replaced with riscv_has_ext(env, RVC).
Remove the old "c" property and 'ext_c' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
This CPU is enabling G via cfg.ext_g and, at the same time, setting
IMAFD in set_misa() and cfg.ext_icsr.
riscv_cpu_validate_set_extensions() is already doing that, so there's no
need for cpu_init() setups to worry about setting G and its extensions.
Signed-off-by: Daniel Henrique Barboza
Review
This function was created to move the sync between cpu->cfg.ext_N bit
changes to env->misa_ext* from the validation step to an ealier step,
giving us a guarantee that we could use either cpu->cfg.ext_N or
riscv_has_ext(env,N) in the validation.
We don't have any cpu->cfg.ext_N left that has an exi
Create a new "h" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVH. Instances of cpu->cfg.ext_h and similar are
replaced with riscv_has_ext(env, RVH).
Remove the old "h" property and 'ext_h' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "j" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVJ. Instances of cpu->cfg.ext_j and similar are
replaced with riscv_has_ext(env, RVJ).
Remove the old "j" property and 'ext_j' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Hi,
This new version has a new patch (3) that removes the 'multi_letter'
attribute from isa_ext_data that became redundant after the changes made
in patch 2. The change was proposed by Weiwei Li in the v2.
All patches but patch 3 are acked.
Changes from v2:
- patch 3 (new)
- remove 'multi_lett
Create a new "d" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVD. Instances of cpu->cfg.ext_d and similar are
replaced with riscv_has_ext(env, RVD).
Remove the old "d" property and 'ext_d' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Create a new "u" RISCVCPUMisaExtConfig property that will update
env->misa_ext* with RVU. Instances of cpu->cfg.ext_u and similar are
replaced with riscv_has_ext(env, RVU).
Remove the old "u" property and 'ext_u' from RISCVCPUConfig.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
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