[PATCH v6 24/25] target/riscv: Reorg access check in get_physical_address

We were effectively computing the protection bits twice, once while performing access checks and once while returning the valid bits to the caller. Reorg so we do this once. Move the computation of mxr close to its single use. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 69

[PATCH v6 08/25] accel/tcg: Add cpu_ld*_code_mmu

At least RISC-V has the need to be able to perform a read using execute permissions, outside of translation. Add helpers to facilitate this. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 9 +++ accel/tcg/cputlb.c | 48 ++ accel/tcg/user-

[PATCH v6 05/25] target/riscv: Add a tb flags field for vstart

From: LIU Zhiwei Once we mistook the vstart directly from the env->vstart. As env->vstart is not a constant, we should record it in the tb flags if we want to use it in translation. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li

[PATCH v6 10/25] target/riscv: Handle HLV, HSV via helpers

Implement these instructions via helpers, in expectation of determining the mmu_idx to use at runtime. This allows the permission check to also be moved out of line, which allows HLSX to be removed from TB_FLAGS. Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 6

[PATCH v6 13/25] target/riscv: Introduce mmuidx_priv

Use the priv level encoded into the mmu_idx, rather than starting from env->priv. We have already checked MPRV+MPP in riscv_cpu_mmu_index -- no need to repeat that. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 9 + target/riscv/cpu_helper.c | 6 +- 2 files change

[PATCH v6 14/25] target/riscv: Introduce mmuidx_2stage

Move and rename riscv_cpu_two_stage_lookup, to match the other mmuidx_* functions. Signed-off-by: Richard Henderson --- target/riscv/cpu.h| 1 - target/riscv/internals.h | 5 + target/riscv/cpu_helper.c | 17 ++--- 3 files changed, 11 insertions(+), 12 deletions(-) di

[PATCH v6 09/25] target/riscv: Use cpu_ld*_code_mmu for HLVX

Use the new functions to properly check execute permission for the read rather than read permission. Signed-off-by: Richard Henderson --- target/riscv/op_helper.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.

[PATCH v6 12/25] target/riscv: Introduce mmuidx_sum

In get_physical_address, we should use the setting passed via mmu_idx rather than checking env->mstatus directly. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 5 + target/riscv/cpu_helper.c | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv

[PATCH v6 22/25] target/riscv: Don't modify SUM with is_debug

If we want to give the debugger a greater view of memory than the cpu, we should simply disable the access check entirely, not simply for this one corner case. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/targe

[PATCH v6 19/25] target/riscv: Hoist pbmte and hade out of the level loop

These values are constant for every level of pte lookup. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 833ea6d3fa..00f70a3dd5 100644 -

[PATCH v6 11/25] target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT

We will enable more uses of this bit in the future. Signed-off-by: Richard Henderson --- target/riscv/internals.h | 6 -- target/riscv/cpu_helper.c | 2 +- target/riscv/op_helper.c | 2 +- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/internals.h b/target/risc

[PATCH v6 15/25] target/riscv: Move hstatus.spvp check to check_access_hlsv

The current cpu_mmu_index value is really irrelevant to the HLV/HSV lookup. Provide the correct priv level directly. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 8 +--- target/riscv/op_helper.c | 2 +- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/targ

[PATCH v6 07/25] target/riscv: Reduce overhead of MSTATUS_SUM change

From: Fei Wu Kernel needs to access user mode memory e.g. during syscalls, the window is usually opened up for a very limited time through MSTATUS.SUM, the overhead is too much if tlb_flush() gets called for every SUM change. This patch creates a separate MMU index for S+SUM, so that it's not ne

[PATCH v6 01/25] target/riscv: Extract virt enabled state from tb flags

From: LIU Zhiwei Virt enabled state is not a constant. So we should put it into tb flags. Thus we can use it like a constant condition at translation phase. Reported-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei Reviewed-by: Weiwei Li Message-Id: <20230324143

[PATCH v6 16/25] target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index

Incorporate the virt_enabled and MPV checks into the cpu_mmu_index function, so we don't have to keep doing it within tlb_fill and subroutines. This also elides a flush on changes to MPV. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 50 +--

[PATCH v6 02/25] target/riscv: Add a general status enum for extensions

From: LIU Zhiwei The pointer masking is the only extension that directly use status. The vector or float extension uses the status in an indirect way. Replace the pointer masking extension special status fields with the general status. Reviewed-by: Richard Henderson Signed-off-by: LIU Zhiwei

[PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups

This builds on Fei and Zhiwei's SUM and TB_FLAGS changes. * Reclaim 5 TB_FLAGS bits, since we nearly ran out. * Using cpu_mmu_index(env, true) is insufficient to implement HLVX properly. While that chooses the correct mmu_idx, it does not perform the read with execute permission.

[PATCH v6 06/25] target/riscv: Separate priv from mmu_idx

From: Fei Wu Currently it's assumed the 2 low bits of mmu_idx map to privilege mode, this assumption won't last as we are about to add more mmu_idx. Here an individual priv field is added into TB_FLAGS. Reviewed-by: Richard Henderson Signed-off-by: Fei Wu Message-Id: <20230324054154.414846-2-f

[PATCH v6 03/25] target/riscv: Encode the FS and VS on a normal way for tb flags

From: LIU Zhiwei Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal way. It will make it hard to change the tb flags layout. And even worse, if we want to keep tb flags for a same extension togather without a hole. Reviewed-by: Richard Henderson Signed-off-by: LIU Z

[PATCH v6 18/25] target/riscv: Hoist second stage mode change to callers

Move the check from the top of get_physical_address to the two callers, where passing mmu_idx makes no sense. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu

[PATCH v6 23/25] target/riscv: Merge checks for reserved pte flags

Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 850817edfd..82a7c5f9dd 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c

[PATCH v6 04/25] target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags

Merge with mstatus_{fs,vs}. We might perform a redundant assignment to one or the other field, but it's a trivial and saves 4 bits from TB_FLAGS. Signed-off-by: Richard Henderson --- target/riscv/cpu.h| 16 +++- target/riscv/cpu_helper.c | 34

[PATCH v6 17/25] target/riscv: Check SUM in the correct register

Table 9.5 "Effect of MPRV..." specifies that MPV=1 uses VS-level vsstatus.SUM instead of HS-level sstatus.SUM. For HLV/HSV instructions, the HS-level register does not apply, but the VS-level register presumably does, though this is not mentioned explicitly in the manual. However, it matches the

[PATCH v6 21/25] target/riscv: Suppress pte update with is_debug

The debugger should not modify PTE_A or PTE_D. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ce12dcec1d..b26840e46c 100644 --- a/target/riscv/cpu_helpe

[PATCH v6 25/25] target/riscv: Reorg sum check in get_physical_address

Implement this by adjusting prot, which reduces the set of checks required. This prevents exec to be set for U pages in MMUIdx_S_SUM. While it had been technically incorrect, it did not manifest as a bug, because we will never attempt to execute from MMUIdx_S_SUM. Signed-off-by: Richard Henderso

Re: [PATCH 6/8] target/riscv: Fix format for indentation

On 2023/3/24 20:38, Weiwei Li wrote: Fix identation problems, and try to use the same indentation strategy in the same file. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/arch_dump.c| 4 +- target/riscv/cpu.c | 4 +- targe

Re: [PATCH v1 00/11] *** add allwinner-r40 support ***

Hi, It's great that you are adding support for a new SoC/Board! On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > *** history *** > > # v1: 2023-03-21 > > The first version which add allwinner-r40 support, supported features: > > + ccu > + dram controller > + uart > + i2c and p

[PATCH 1/1] target/riscv: Convert env->virt to a bool env->virt_enabled

Currently we only use the env->virt to encode the virtual mode enabled status. Let's make it a bool type. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h| 2 +- target/riscv/cpu_bits.h | 3 --- target/riscv/cpu_helper.c | 6 +++--- target/riscv/machine.c| 6 +++--- target/riscv/tr

Re: [PATCH 0/8] target/riscv: Simplification for RVH related check and code style fix

On 2023/3/24 20:38, Weiwei Li wrote: This patchset tries to simplify the RVH related check and fix some code style problems, such as problems for indentation, multi-line comments and lines with over 80 characters. This patch set looks good to me, except a small comment on patch 6(target/ri

[PATCH v3] block: replace TABs with space

Bring the block files in line with the QEMU coding style, with spaces for indentation. This patch partially resolves the issue 371. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/371 Signed-off-by: Yeqi Fu --- block/bochs.c | 18 +++ block/file-posix.c | 126

[PATCH v6 20/25] target/riscv: Move leaf pte processing out of level loop

Move the code that never loops outside of the loop. Unchain the if-return-else statements. Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 234 +- 1 file changed, 127 insertions(+), 107 deletions(-) diff --git a/target/riscv/cpu_helper.c b/ta

Re: [PATCH v4 1/3] docs: Add support for TPM devices over I2C bus

On 3/25/23 00:37, Ninad Palsule wrote: This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule --- V2: Incorporated Stephen's review comme

Re: [PATCH v4 2/3] tpm: Extend common APIs to support TPM TIS I2C

On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C supp

Re: [PULL 0/8] Misc patches for QEMU 8.0-rc2

On Fri, 24 Mar 2023 at 15:36, Thomas Huth wrote: > > The following changes since commit 60ca584b8af0de525656f959991a440f8c191f12: > > Merge tag 'pull-for-8.0-220323-1' of https://gitlab.com/stsquad/qemu into > staging (2023-03-22 17:58:12 +) > > are available in the Git repository at: > >

Re: [PULL 0/1] QGA warning fix

On Wed, 22 Mar 2023 at 19:22, Konstantin Kostiuk wrote: > > From: Kostiantyn Kostiuk > > > The following changes since commit 9832009d9dd2386664c15cc70f6e6bfe062be8bd: > > Merge tag 'pull-riscv-to-apply-20230306' of > https://gitlab.com/palmer-dabbelt/qemu into staging (2023-03-07 12:53:00 >

Re: [PULL 0/2] xen queue

On Fri, 24 Mar 2023 at 14:56, Anthony PERARD wrote: > > The following changes since commit 60ca584b8af0de525656f959991a440f8c191f12: > > Merge tag 'pull-for-8.0-220323-1' of https://gitlab.com/stsquad/qemu into > staging (2023-03-22 17:58:12 +) > > are available in the Git repository at: >

Re: [PATCH v4 3/3] tpm: Add support for TPM device over I2C bus

On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added i

Re: [PATCH v4 3/3] tpm: Add support for TPM device over I2C bus

On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. Your v4 patches with my 2 patches for the test cases are here now: https://github.com/stefanb

Re: [PATCH v1 01/11] hw: arm: Add bananapi M2-Ultra and allwinner-r40 support

Hi, On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > Allwinner R40 (sun8i) SoC features a Quad-Core Cortex-A7 ARM CPU, > and a Mali400 MP2 GPU from ARM. It's also known as the Allwinner T3 > for In-Car Entertainment usage, A40i and A40pro are variants that > differ in applicabl

Re: [PATCH v1 02/11] hw/arm/allwinner-r40: add Clock Control Unit

Hi, On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > The CCU provides the registers to program the PLLs and the controls > most of the clock generation, division, distribution, synchronization > and gating. > > This commit adds support for the Clock Control Unit which emulates

Re: [PATCH v1 03/11] hw: allwinner-r40: Complete uart devices

Hi, On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > R40 has eight UARTs, support both 16450 and 16550 compatible modes. > > Signed-off-by: qianfan Zhao > --- > hw/arm/allwinner-r40.c | 32 > include/hw/arm/allwinner-r40.h | 7 +++

Re: [PATCH v1 04/11] hw: arm: allwinner-r40: Add 5 TWI controllers

Hi, On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > TWI(i2c) is designed to be used as an interface between CPU host and the > serial 2-Wire bus. It can support all standard 2-Wire transfer, can be > operated in standard mode(100kbit/s) or fast-mode, supporting data rate > up

Re: [PATCH v1 05/11] hw/misc: AXP221 PMU Emulation

Hi, On Tue, Mar 21, 2023 at 11:25 AM wrote: > > From: qianfan Zhao > > This patch adds minimal support for AXP-221 PMU and connect it to > bananapi M2U board. > > Signed-off-by: qianfan Zhao As I wrote in the RFC patch, I would suggest renaming the axp209.c file to axp2xx_pmu.c and extending i

Re: [PATCH v2 4/7] hw/ipmi: Refactor IPMI interface

On Fri, Mar 24, 2023 at 04:09:01PM -0700, Hao Wu wrote: > This patch refactors the IPMI interface so that it can be used by both > the BMC side and core-side simulation. This patch is hard to review because it does so many different things and they are all mixed up. It looks ok, but it's hard to

Re: [PATCH v2 2/7] docs/specs: IPMI device emulation: main processor

On Fri, Mar 24, 2023 at 04:08:59PM -0700, Hao Wu wrote: > From: Havard Skinnemoen > > This document is an attempt to briefly document the existing IPMI > emulation support on the main processor. It provides the necessary > background for the BMC-side IPMI emulation proposed by the next patch. >

[PATCH v5 2/3] tpm: Extend common APIs to support TPM TIS I2C

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C support. The checksum calculation is handled in t

[PATCH v5 3/3] tpm: Add support for TPM device over I2C bus

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added in the model to temporarily cache the data

[PATCH v5 1/3] docs: Add support for TPM devices over I2C bus

This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule --- V2: Incorporated Stephen's review comments - Added example in the document. --- V4

[PATCH v5 0/3] Add support for TPM devices over I2C bus

Hello, In V5, I have fixed issues reported by Stefan's test. This drop adds support for the TPM devices attached to the I2C bus. It only supports the TPM2 protocol. You need to run it with the external TPM emulator like swtpm. I have tested it with swtpm. I have refered to the work done by zhdan

Re: [PATCH v4 3/3] tpm: Add support for TPM device over I2C bus

On 3/25/23 11:46 AM, Stefan Berger wrote: On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. Your v4 patches with my 2 patches for the test cas

Re: [PATCH v4 1/3] docs: Add support for TPM devices over I2C bus

On 3/25/23 11:10 AM, Stefan Berger wrote: On 3/25/23 00:37, Ninad Palsule wrote: This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule

Re: [PATCH v4 2/3] tpm: Extend common APIs to support TPM TIS I2C

Hi Stefan, On 3/25/23 11:12 AM, Stefan Berger wrote: On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new che

Re: [PATCH v4 3/3] tpm: Add support for TPM device over I2C bus

Hi Stefan, On 3/25/23 11:44 AM, Stefan Berger wrote: On 3/25/23 00:37, Ninad Palsule wrote: Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the comm

[PATCH v6 0/3] Add support for TPM devices over I2C bus

Hello, I have incorporated review comments from Stefan. Please review. This drop adds support for the TPM devices attached to the I2C bus. It only supports the TPM2 protocol. You need to run it with the external TPM emulator like swtpm. I have tested it with swtpm. I have refered to the work d

[PATCH v6 2/3] tpm: Extend common APIs to support TPM TIS I2C

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. This commit includes changes for the common code. - Added support for the new checksum registers which are required for the I2C support. The checksum calculation is handled in t

[PATCH v6 1/3] docs: Add support for TPM devices over I2C bus

This is a documentation change for I2C TPM device support. Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. Signed-off-by: Ninad Palsule --- V2: Incorporated Stephen's review comments - Added example in the document. --- V4

[PATCH v6 3/3] tpm: Add support for TPM device over I2C bus

Qemu already supports devices attached to ISA and sysbus. This drop adds support for the I2C bus attached TPM devices. I2C model only supports TPM2 protocol. This commit includes changes for the common code. - Added I2C emulation model. Logic was added in the model to temporarily cache the data

Re: [PATCH for-8.0 00/11] tcg patch queue

Ping. On 3/22/23 08:07, Richard Henderson wrote: Posting pre-PR because I had to adjust Emilio's QTree patch [1], and added a new patch to avoid an assert that can be generated with incorrect -R reserved_va values vs the ARM commpage. r~ [1] https://gitlab.com/rth7680/qemu/-/jobs/3975817279#L9

Re: [PATCH v6 00/25] target/riscv: MSTATUS_SUM + cleanups

On 3/25/23 03:54, Richard Henderson wrote: This builds on Fei and Zhiwei's SUM and TB_FLAGS changes. * Reclaim 5 TB_FLAGS bits, since we nearly ran out. * Using cpu_mmu_index(env, true) is insufficient to implement HLVX properly. While that chooses the correct mmu_idx, it does

[PATCH v2 0/5] Support x2APIC mode with TCG accelerator

Hi everyone, This series implements x2APIC mode in userspace local APIC and the RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu and AMD iommu are adjusted to support x2APIC interrupt remapping. With this series, we can now boot Linux kernel into x2APIC mode with TCG accel

[PATCH v2 1/5] i386/tcg: implement x2APIC registers MSR access

This commit refactors apic_mem_read/write to support both MMIO access in xAPIC and MSR access in x2APIC. Signed-off-by: Bui Quang Minh --- hw/intc/apic.c | 79 ++-- hw/intc/trace-events | 4 +- include/hw/i386/apic.h |

[PATCH v2 3/5] apic, i386/tcg: add x2apic transitions

This commit adds support for x2APIC transitions when writing to MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to TCG_EXT_FEATURES. Signed-off-by: Bui Quang Minh --- hw/intc/apic.c | 50 hw/intc/apic_common.c| 7 ++

[PATCH v2 5/5] amd_iommu: report x2APIC support to the operating system

This commit adds XTSup configuration to let user choose to whether enable this feature or not. When XTSup is enabled, additional bytes in IRTE with enabled guest virtual VAPIC are used to support 32-bit destination id. Additionally, this commit changes to use IVHD type 0x11 in ACPI table for featu

[PATCH v2 4/5] intel_iommu: allow Extended Interrupt Mode when using userspace APIC

As userspace APIC now supports x2APIC, intel interrupt remapping hardware can be set to EIM mode when userspace local APIC is used. Signed-off-by: Bui Quang Minh --- hw/i386/intel_iommu.c | 11 --- 1 file changed, 11 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.

[PATCH v2 2/5] apic: add support for x2APIC mode

This commit extends the APIC ID to 32-bit long and remove the 255 max APIC ID limit in userspace APIC. The array that manages local APICs is now dynamically allocated based on the max APIC ID of created x86 machine. Also, new x2APIC IPI destination determination scheme, self IPI and x2APIC mode reg