On 24/02/2023 08.56, Sunil V L wrote:
On Fri, Feb 24, 2023 at 08:34:41AM +0100, Thomas Huth wrote:
Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
line option that should be replaced with the "acpi" machine parameter
nowadays.
Signed-off-by: Thomas Huth
---
docs/about/deprec
On 24/2/23 07:22, Thomas Huth wrote:
On 23/02/2023 21.23, Philippe Mathieu-Daudé wrote:
On 23/2/23 20:13, Thomas Huth wrote:
When handling pull requests in the staging branch, it often happens
that one of the job fails due to a problem, so that the pull request
can't be merged. Peter/Richard/St
On 24/02/2023 09.01, Philippe Mathieu-Daudé wrote:
On 24/2/23 07:22, Thomas Huth wrote:
On 23/02/2023 21.23, Philippe Mathieu-Daudé wrote:
On 23/2/23 20:13, Thomas Huth wrote:
When handling pull requests in the staging branch, it often happens
that one of the job fails due to a problem, so tha
On 23/2/23 00:27, Richard Henderson wrote:
This makes it easier to assign blame with perf.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 23/2/23 00:26, Richard Henderson wrote:
Write back the number of insns that we attempt to translate,
so that if we longjmp out we have a more accurate limit for
the next attempt. This results in fewer restarts when some
limit is consumed by few instructions.
Signed-off-by: Richard Henderson
On 2/23/23 20:57, Philippe Mathieu-Daudé wrote:
On 24/2/23 01:45, Richard Henderson wrote:
Change to match the recent change to probe_access_flags.
All existing callers updated to supply 0, so no change in behaviour.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h |
On 23/2/23 00:26, Richard Henderson wrote:
Just because the label reference count is more than 1 does
not mean we cannot remove a branch-to-next. By doing this
first, the label reference count may drop to 0, and then
the label itself gets removed as before.
Signed-off-by: Richard Henderson
---
On 24/2/23 09:03, Thomas Huth wrote:
On 24/02/2023 09.01, Philippe Mathieu-Daudé wrote:
On 24/2/23 07:22, Thomas Huth wrote:
On 23/02/2023 21.23, Philippe Mathieu-Daudé wrote:
On 23/2/23 20:13, Thomas Huth wrote:
When handling pull requests in the staging branch, it often happens
that one of
On 24/2/23 05:51, Akihiko Odaki wrote:
On 2023/02/23 21:59, Philippe Mathieu-Daudé wrote:
On 3/2/23 18:38, Philippe Mathieu-Daudé wrote:
On 2/2/23 17:01, Alex Bennée wrote:
Testing, docs, semihosting and plugin updates
-
On Fri, Feb 24, 2023 at 08:59:41AM +0100, Thomas Huth wrote:
> On 24/02/2023 08.56, Sunil V L wrote:
> > On Fri, Feb 24, 2023 at 08:34:41AM +0100, Thomas Huth wrote:
> > > Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
> > > line option that should be replaced with the "acpi" mach
On Mon, Feb 20, 2023 at 12:59:22PM +0100, Jesper Devantier wrote:
> From: Joel Granados
>
> In order to return the units_{read/written} required by the SMART log we
> need to shift the number of bytes value by BDRV_SECTORS_BITS and multiply
> by 1000. This is a prep patch that moves this adjustme
Optimize the virtio-balloon feature on the ARM platform by adding a variable to
keep track of the current hot-plugged pc-dimm size, instead of traversing the
virtual machine's memory modules to count the current RAM size during the
balloon inflation or deflation process. This variable can be u
On Fri, Feb 24, 2023 at 08:23:40AM +, Yangming wrote:
>
> Optimize the virtio-balloon feature on the ARM platform by adding a variable
> to keep track of the current hot-plugged pc-dimm size, instead of traversing
> the virtual machine's memory modules to count the current RAM size during th
On 11/23/22 19:17, Huanyu ZHAI wrote:
Subject: [PATCH] cpu/i386: update xsave components after CPUID filtering
On i386 platform, CPUID data are setup through three consecutive steps:
CPU model definition, expansion and filtering.
XSAVE components are enabled during the expansion stage, by che
This series adds the basic ACPI support for the RISC-V virt machine.
Currently only RINTC interrupt controller specification is approved by the
UEFI forum. External interrupt controller support in ACPI is in progress.
The basic infrastructure changes are mostly leveraged from ARM.
This adds supp
ACPI will be enabled by default. Add a switch to turn off
for testing and debug purposes.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 29 +
include/hw/riscv/virt.h | 2 ++
2 files changed, 31 insertions(+)
diff --git a/hw/riscv/
Initialize the ACPI tables if the acpi option is not
disabled.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index bcbacf4e63..126352d480 100644
--- a/hw/ris
ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields
in the RISCVVirtState structure and initialize with default values.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/riscv/virt.c | 5 +
include/hw/riscv/
Add basic ACPI infrastructure for RISC-V with below tables.
1) DSDT with below basic objects
- CPUs
- fw_cfg
2) FADT revision 6 with HW_REDUCED flag
3) XSDT
4) RSDP
Add this functionality in a new file virt-acpi-build.c and enable
bui
Add Multiple APIC Description Table (MADT) with the
RINTC structure for each cpu.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/riscv/virt-acpi-build.c | 44 ++
1 file changed, 44 insertions(+)
diff --git a/hw/riscv/vi
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
---
hw/riscv/virt-acpi-build.c | 76 ++
1 file changed, 76 insertions(+)
diff --git a/hw/riscv/virt-a
RISC-V ACPI related functionality for virt machine is added in
virt-acpi-build.c. Add the maintainer entry after moving the
ARM ACPI entry under the main ACPI entry.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
---
MAINTAINERS | 18 ++
On 24/02/2023 09.20, Sunil V L wrote:
On Fri, Feb 24, 2023 at 08:59:41AM +0100, Thomas Huth wrote:
On 24/02/2023 08.56, Sunil V L wrote:
On Fri, Feb 24, 2023 at 08:34:41AM +0100, Thomas Huth wrote:
Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
line option that should be repl
memmap needs to be exported outside of virt.c so that
modules like acpi can use it. Hence, add a pointer field
in RiscVVirtState structure and initialize it with the
memorymap.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/riscv/vir
On 15/02/2023 17.16, Philippe Mathieu-Daudé wrote:
isa_get_dma() returns a DMA channel handler from an ISABus.
To emphasize this, rename it as isa_bus_get_dma().
Mechanical change using:
$ sed -i -e 's/isa_get_dma/isa_bus_get_dma/g' \
$(git grep -l isa_get_dma)
Signed-off-by: Phili
On 15/02/2023 17.16, Philippe Mathieu-Daudé wrote:
isa_get_irq() was added in commit 3a38d437ca
("Add isa_reserve_irq()" Fri Aug 14 11:36:15 2009) as:
a temporary interface to be used to allocate ISA IRQs for
devices which have not yet been converted to qdev, and for
special cases
On Thu, Feb 23, 2023 at 04:24:43PM -0500, Stefan Hajnoczi wrote:
> On Thu, Feb 23, 2023 at 02:36:33AM -0500, Michael S. Tsirkin wrote:
> > On Wed, Feb 22, 2023 at 03:21:42PM -0500, Michael S. Tsirkin wrote:
> > > On Wed, Feb 22, 2023 at 08:25:19PM +0200, Anton Kuchin wrote:
> > > > On 22/02/2023 19
On 15/02/2023 17.16, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/audio/cs4231a.c | 5 +++--
hw/audio/gus.c | 5 +++--
hw/audio/sb16.c | 7 ---
hw/block/fdc-isa.c | 5 +++--
include/hw/timer/i8254.h | 3 ++-
5 files changed,
On Mon, Feb 20, 2023 at 12:59:24PM +0100, Jesper Devantier wrote:
> From: Klaus Jensen
>
> Add the mandatory Endurance Group identify data structures and log
> pages.
>
> For now, all namespaces in a subsystem belongs to a single Endurance
> Group.
>
> Signed-off-by: Klaus Jensen
> ---
> hw/n
On Thu, Feb 23, 2023 at 05:30:58PM -0300, Fabiano Rosas wrote:
>
> Hi Alex,
>
> > Daniel P. Berrangé writes:
> >
> >> On Thu, Feb 23, 2023 at 11:21:53AM -0300, Fabiano Rosas wrote:
> >>> I'm not sure if this was discussed previously, but I noticed we're not
> >>> pulling the images we push to th
Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
line option that should be replaced with the "acpi" machine parameter
nowadays.
Signed-off-by: Thomas Huth
---
v2: Fixed stypid copy-n-paste bug (Thanks to Sunil for spotting it!)
docs/about/deprecated.rst | 6 ++
softmmu/vl.
On Fri, Feb 24, 2023 at 10:05:43AM +0100, Thomas Huth wrote:
> Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
> line option that should be replaced with the "acpi" machine parameter
> nowadays.
>
> Signed-off-by: Thomas Huth
> ---
> v2: Fixed stypid copy-n-paste bug (Thanks to
On Thu, Feb 23, 2023 at 10:11:11PM +, Eldon Stegall wrote:
> On Thu, Feb 23, 2023 at 03:33:00PM +, Daniel P. Berrangé wrote:
> > IIUC, we already have available compute resources from a couple of
> > sources we could put into service. The main issue is someone to
> > actually configure them
On Fri, Feb 24, 2023 at 10:05:43 +0100, Thomas Huth wrote:
> Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
> line option that should be replaced with the "acpi" machine parameter
> nowadays.
>
> Signed-off-by: Thomas Huth
> ---
> v2: Fixed stypid copy-n-paste bug (Thanks to Su
On 2/23/23 21:23, Richard Henderson wrote:
On 2/23/23 14:19, Richard Henderson wrote:
On 2/23/23 13:44, Daniel Henrique Barboza wrote:
+ if (unlikely(flags & TLB_NOTDIRTY)) {
+ notdirty_write(env_cpu(env), addr, 1, full, retaddr);
That '1' should be 'size'. Fixed locally.
Hmph
On 2/24/23 04:09, Gavin Shan wrote:
On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
On 2/23/23 05:13, Gavin Shan wrote:
For arm64 and RiscV architecture, the driver (/base/arch_topology.c) is
used to populate the CPU topology in the Linux guest. It's required that
the CPUs in one socket
On 2/23/23 21:45, Richard Henderson wrote:
Change to match the recent change to probe_access_flags.
All existing callers updated to supply 0, so no change in behaviour.
Signed-off-by: Richard Henderson
---
Reviewed-by: Daniel Henrique Barboza
include/exec/exec-all.h | 2 +
Queued, thanks.
Paolo
On Feb 24 09:51, Joel Granados wrote:
> On Mon, Feb 20, 2023 at 12:59:24PM +0100, Jesper Devantier wrote:
> > From: Klaus Jensen
> >
> > Add the mandatory Endurance Group identify data structures and log
> > pages.
> >
> > For now, all namespaces in a subsystem belongs to a single Endurance
> >
On Feb 24 09:20, Joel Granados wrote:
> On Mon, Feb 20, 2023 at 12:59:22PM +0100, Jesper Devantier wrote:
> > From: Joel Granados
> >
> > In order to return the units_{read/written} required by the SMART log we
> > need to shift the number of bytes value by BDRV_SECTORS_BITS and multiply
> > by 1
On Thu, Feb 23, 2023 at 12:55:16AM +, Ackerley Tng wrote:
>
> "Kirill A. Shutemov" writes:
>
> > On Thu, Feb 16, 2023 at 12:41:16AM +, Ackerley Tng wrote:
> > > By default, the backing shmem file for a restrictedmem fd is created
> > > on shmem's kernel space mount.
>
> > > With this pa
On 24/2/23 10:05, Thomas Huth wrote:
Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
line option that should be replaced with the "acpi" machine parameter
nowadays.
Signed-off-by: Thomas Huth
---
v2: Fixed stypid copy-n-paste bug (Thanks to Sunil for spotting it!)
docs/abo
On 2/23/23 16:33, Daniel P. Berrangé wrote:
On Thu, Feb 23, 2023 at 03:28:37PM +, Ben Dooks wrote:
On Thu, Feb 23, 2023 at 12:56:56PM +, Peter Maydell wrote:
Hi; the project is out of gitlab CI pipeline minutes again.
In the absence of any other proposals, no more pull request
merges wi
Am 23. Februar 2023 19:40:03 UTC schrieb "Volker Rümelin" :
>Am 21.02.23 um 19:44 schrieb BALATON Zoltan:
>> This adds basic implementation of the AC'97 sound part used in VIA
>> south bridge chips. Not all features of the device is emulated, only
>> one playback channel is supported but this is
On Thu, 23 Feb 2023 at 23:01, Richard Henderson
wrote:
>
> On 2/22/23 01:01, Alex Bennée wrote:
> > This is a mandatory feature for Armv8.1 architectures but we don't
> > state the feature clearly in our emulation list. While checking verify
> > our cortex-a76 model matches up with the current TRM
On Fri, 24 Feb 2023 at 00:18, BALATON Zoltan wrote:
>
> Pixman can sometimes return false so add fallbacks for such cases and
> also add a property to disable pixman and always use the fallbacks
> which can be useful on platforms where pixman is broken or for testing
> different drawing methods.
>
On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote:
On 2/24/23 04:09, Gavin Shan wrote:
On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
On 2/23/23 05:13, Gavin Shan wrote:
For arm64 and RiscV architecture, the driver (/base/arch_topology.c) is
used to populate the CPU topology in the Linux
On 2/23/23 10:51 PM, Peter Maydell wrote:
On Thu, 23 Feb 2023 at 00:52, Gavin Shan wrote:
On 2/23/23 2:54 AM, Peter Maydell wrote:
But we might have to for other boards we add later. We shouldn't
put code in per-board if it's not really board specific.
Moreover, I think "we need the backup b
On 24/2/23 00:27, Richard Henderson wrote:
On 2/23/23 13:22, Philippe Mathieu-Daudé wrote:
On 24/2/23 00:01, Richard Henderson wrote:
On 2/22/23 01:01, Alex Bennée wrote:
This is a mandatory feature for Armv8.1 architectures but we don't
state the feature clearly in our emulation list. While c
On Fri, Feb 24, 2023 at 02:07:01PM +0530, Sunil V L wrote:
> RISC-V ACPI related functionality for virt machine is added in
> virt-acpi-build.c. Add the maintainer entry after moving the
> ARM ACPI entry under the main ACPI entry.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Bin Meng
> Acked-by:
On Fri, Feb 24, 2023 at 09:16:39PM +1100, Gavin Shan wrote:
> On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote:
> > On 2/24/23 04:09, Gavin Shan wrote:
> > > On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
> > > > On 2/23/23 05:13, Gavin Shan wrote:
> > > > > For arm64 and RiscV architecture,
QAPI seems designed to maintain such enums,
so convert QKbdModifier to be QAPI generated.
Besides, this is how QKeyCode is maintained.
Philippe Mathieu-Daudé (2):
ui/kbd-state: Rename QKbdModifier enum definitions
ui/kbd-state: QAPI'fy QKbdModifier
include/ui/kbd-state.h | 16 ---
Let QAPI maintain the QKbdModifier enum values.
Signed-off-by: Philippe Mathieu-Daudé
---
include/ui/kbd-state.h | 16
qapi/ui.json | 10 ++
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/include/ui/kbd-state.h b/include/ui/kbd-state.h
index 1
In order to QAPI'fy QKbdModifier in the next commit,
rename its definitions to a QAPI-ready format.
Mechanical change doing:
$ sed -i -e s/QKBD_MOD_/Q_KBD_MODIFIER_/g $(git grep -l QKBD_MOD_)
Signed-off-by: Philippe Mathieu-Daudé
---
include/ui/kbd-state.h | 16
ui/cocoa.m
On Wed, 22 Feb 2023 at 22:14, Richard Henderson
wrote:
>
> On 2/22/23 09:35, Aaron Lindsay wrote:
> > Signed-off-by: Aaron Lindsay
> > ---
> > +static Property arm_cpu_pauth2_property =
> > +DEFINE_PROP_BOOL("pauth2", ARMCPU, prop_pauth2, false);
> > +static Property arm_cpu_pauth_fpac_prope
On 23/02/2023 23:26, Jason Gunthorpe wrote:
> On Thu, Feb 23, 2023 at 03:33:09PM -0700, Alex Williamson wrote:
>> On Thu, 23 Feb 2023 16:55:54 -0400
>> Jason Gunthorpe wrote:
>>> On Thu, Feb 23, 2023 at 01:06:33PM -0700, Alex Williamson wrote:
>>> Or even better figure out how to get interrupt rem
On 2/24/23 01:08, Weiwei Li wrote:
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-
On 2/24/23 01:08, Weiwei Li wrote:
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/csr.c | 13 +
1 file changed, 9 insertions(+), 4 deletions
On 2/24/23 01:08, Weiwei Li wrote:
Add ext_svadu property
Add HADE field in *envcfg:
* menvcfg.HADE is read-only zero if Svadu is not implemented.
* henvcfg.HADE is read-only zero if menvcfg.HADE is zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henriq
On 2/24/23 01:08, Weiwei Li wrote:
menvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in S-mode and G-stage address translation.
henvcfg.PBMTE bit controls whether the Svpbmt extension is available
for use in VS-stage address translation.
Set *envcfg.PBMTE default t
On 2/24/23 01:08, Weiwei Li wrote:
When menvcfg.HADE is 1, hardware updating of PTE A/D bits is enabled
during single-stage address translation. When the hypervisor extension is
implemented, if menvcfg.HADE is 1, hardware updating of PTE A/D bits is
enabled during G-stage address translation.
On 2/24/23 01:08, Weiwei Li wrote:
Set it default true for backward compatibility
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
Reviewed-by: Daniel Henrique Barboza
target/riscv/cpu.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/cpu.c b/target/risc
On Fri, 24 Feb 2023 00:29:47 +
Fan Ni wrote:
> On Mon, Feb 20, 2023 at 11:46:46AM +, Jonathan Cameron wrote:
>
> > On Fri, 17 Feb 2023 06:08:57 -0500
> > Gregory Price wrote:
> >
> > > On Fri, Feb 17, 2023 at 04:16:17PM +, Jonathan Cameron via wrote:
> > > > On Tue, 31 Jan 2023
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
> henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
>
> Signed-off-by: Weiwei Li
> Signed-off-by: Junqiang Wang
> ---
> target/riscv/csr.c | 13 +
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> di
On Fri, 24 Feb 2023, Bernhard Beschow wrote:
Am 23. Februar 2023 19:40:03 UTC schrieb "Volker Rümelin" :
Am 21.02.23 um 19:44 schrieb BALATON Zoltan:
This adds basic implementation of the AC'97 sound part used in VIA
south bridge chips. Not all features of the device is emulated, only
one playb
On Fri, 24 Feb 2023, Peter Maydell wrote:
On Fri, 24 Feb 2023 at 00:18, BALATON Zoltan wrote:
Pixman can sometimes return false so add fallbacks for such cases and
also add a property to disable pixman and always use the fallbacks
which can be useful on platforms where pixman is broken or for
On 2023/2/24 20:19, Andrew Jones wrote:
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/csr.c | 13 +
1 file changed, 9 inse
On Wed, 22 Feb 2023 at 02:00, Richard Henderson
wrote:
>
> The following changes since commit 79b677d658d3d35e1e776826ac4abb28cdce69b8:
>
> Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
> staging (2023-02-21 11:28:31 +)
>
> are available in the Git repository at:
>
>
On Fri, 24 Feb 2023 14:06:58 +0530
Sunil V L wrote:
> Add Multiple APIC Description Table (MADT) with the
> RINTC structure for each cpu.
>
> Signed-off-by: Sunil V L
> Acked-by: Alistair Francis
> Reviewed-by: Andrew Jones
> ---
> hw/riscv/virt-acpi-build.c | 44
Make use of the --cache-from option from 'docker build' by including
build layers when building and then pulling a previously built image
before the next build.
This was previously done by the docker.py script, but got disabled due
to bad interactions with certain runners. See commit 6ddc3dc7a8
("
On 24/02/2023 11:25, Joao Martins wrote:
> On 23/02/2023 23:26, Jason Gunthorpe wrote:
>> On Thu, Feb 23, 2023 at 03:33:09PM -0700, Alex Williamson wrote:
>>> On Thu, 23 Feb 2023 16:55:54 -0400
>>> Jason Gunthorpe wrote:
On Thu, Feb 23, 2023 at 01:06:33PM -0700, Alex Williamson wrote:
Or
Our dockerfiles no longer reference layers from other qemu images so
we can now use 'docker build' on them.
Signed-off-by: Fabiano Rosas
---
.gitlab-ci.d/container-template.yml | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/.gitlab-ci.d/container-template.yml
b/.gitlab-
Turns out we were already pulling the image, but for forks we were
pulling from a different registry and for the main project we had
caching disabled due to a bug with docker/gitlab.
I've now replaced the usage of docker.py with a plain docker command
and reintroduced the caching.
I also removed
We're not using the COMMON_TAG and we cannot have a push to a
different registry than we pull from because that would get in the way
of forks testing their changes to a dockerfile.
Signed-off-by: Fabiano Rosas
---
.gitlab-ci.d/container-template.yml | 2 --
1 file changed, 2 deletions(-)
diff -
On Fri, 24 Feb 2023 14:06:59 +0530
Sunil V L wrote:
> RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
> Table (RHCT). Add this to the ACPI tables.
>
> Signed-off-by: Sunil V L
> Reviewed-by: Andrew Jones
> ---
> hw/riscv/virt-acpi-build.c | 76 ++
On Fri, 24 Feb 2023 10:05:43 +0100
Thomas Huth wrote:
> Similar to "-no-hpet", the "-no-acpi" switch is a legacy command
> line option that should be replaced with the "acpi" machine parameter
> nowadays.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Igor Mammedov
> ---
> v2: Fixed stypid cop
On Fri, 24 Feb 2023 at 12:46, Peter Maydell wrote:
>
> On Wed, 22 Feb 2023 at 02:00, Richard Henderson
> wrote:
> >
> > The following changes since commit 79b677d658d3d35e1e776826ac4abb28cdce69b8:
> >
> > Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into
> > staging (2023-0
Just for some motivation, this is what we want to make possible for more
people with QEMU 8.0: https://youtu.be/YY9RExl4VDI
This would need at least my SM502 patches and fixing the IRQ routing in
the VT8231 (this test was with my series for that, I'll ask testing
Bernhard's version the same wa
On 1/31/23 23:56, Taylor Simpson wrote:
static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
{
const target_ulong reg_mask_low = reg_immut_masks[rnum];
@@ -167,6 +120,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
}
tcg_temp_free(val32);
+tcg
On Wed, 22 Feb 2023 at 02:34, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Wed, 22 Feb 2023 at 02:34, Richard Henderson
wrote:
>
> M-profile doesn't have HCR_EL2. While we could test features
> before each call, zero is a generally safe return value to
> disable the code in the caller. This test is required to
> avoid an assert in arm_is_secure_below_el3.
>
> Signed
On Wed, 22 Feb 2023 at 02:34, Richard Henderson
wrote:
>
> In several places we use arm_is_secure_below_el3 and
> arm_is_el3_or_mon separately from arm_is_secure.
> These functions make no sense for m-profile, and
> would indicate prior incorrect feature testing.
>
> Signed-off-by: Richard Henders
Richard Henderson writes:
> On 2/22/23 01:01, Alex Bennée wrote:
>> This is a mandatory feature for Armv8.1 architectures but we don't
>> state the feature clearly in our emulation list. While checking verify
>> our cortex-a76 model matches up with the current TRM by breaking out
>> the long fo
On Wed, 22 Feb 2023 at 02:36, Richard Henderson
wrote:
>
> This was added in 7e98e21c098 as part of a reorg in which
> one of the argument had been legally NULL, and this caught
> actual instances. Now that the reorg is complete, this
> serves little purpose.
>
> Signed-off-by: Richard Henderson
Philippe Mathieu-Daudé writes:
> Now that the previous commit ("hw/mips/gt64xxx_pci: Don't
> endian-swap GT_PCI0_CFGADDR") fixed the issue accessing
> the GT64120 PCI config-address register on big-endian
> targets, we can enable this TuxRun test.
>
> Signed-off-by: Philippe Mathieu-Daudé
Ack
From: Christoph Muellner
The cmo.prefetch instructions are nops for QEMU (no emulation of the
memory hierarchy, no illegal instructions, no permission faults, no
traps).
Add a comment noting where they would be decoded in case cbo.prefetch
instructions become relevant in the future.
Co-develope
probe_access_flags() as it is today uses probe_access_full(), which in
turn uses probe_access_internal() with size = 0. probe_access_internal()
then uses the size to call the tlb_fill() callback for the given CPU.
This size param ('fault_size' as probe_access_internal() calls it) is
ignored by most
From: Christoph Muellner
The RISC-V base cache management operation (CBO) ISA extension has been
ratified. It defines three extensions: Cache-Block Management, Cache-Block
Prefetch and Cache-Block Zero. More information about the spec can be
found at [1].
Let's start by implementing the Cache-Bl
Hi,
This version has a change in patch 2, proposed by Weiwei Li, where we're
now triggering virt_instruction_fault before triggering illegal_insn
fault from S mode.
Richard already queued patch 1 is queued in tcg-next already. I'm still
including it here to allow for easier testing of the remain
From: Christoph Muellner
Zicbom is the Cache-Block Management extension defined in the already
ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1].
The extension contains three instructions: cbo.clean, cbo.flush and
cbo.inval. All of them must be implemented in the same group
On Fri, 24 Feb 2023, Peter Maydell wrote:
On Fri, 24 Feb 2023 at 00:18, BALATON Zoltan wrote:
Pixman can sometimes return false so add fallbacks for such cases and
also add a property to disable pixman and always use the fallbacks
which can be useful on platforms where pixman is broken or for t
On Wed, 22 Feb 2023 at 02:34, Richard Henderson
wrote:
>
> Integrate neighboring code from get_phys_addr_lpae which computed
> starting level, as it is easier to validate when doing both at the
> same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
> especially S2InvalidSL and S2Inco
Eldon Stegall writes:
> On Thu, Feb 23, 2023 at 03:33:00PM +, Daniel P. Berrangé wrote:
>> IIUC, we already have available compute resources from a couple of
>> sources we could put into service. The main issue is someone to
>> actually configure them to act as runners *and* maintain their
On Fri, 24 Feb 2023 21:16:39 +1100
Gavin Shan wrote:
> On 2/24/23 8:26 PM, Daniel Henrique Barboza wrote:
> > On 2/24/23 04:09, Gavin Shan wrote:
> >> On 2/24/23 12:18 AM, Daniel Henrique Barboza wrote:
> >>> On 2/23/23 05:13, Gavin Shan wrote:
> For arm64 and RiscV architecture, the d
On 1/31/23 23:56, Taylor Simpson wrote:
/* Called during packet commit when there are two scalar stores */
-void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int mmu_idx)
+void HELPER(probe_pkt_scalar_store_s0)(CPUHexagonState *env, int args)
{
-probe_store(env, 0, mmu_idx);
On Wed, 22 Feb 2023 at 02:35, Richard Henderson
wrote:
>
> With RME, SEL2 must also be present to support secure state.
> The NS bit is RES1 if SEL2 is not present.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Peter May
Hi Igor,
On Fri, Feb 24, 2023 at 01:53:43PM +0100, Igor Mammedov wrote:
> On Fri, 24 Feb 2023 14:06:58 +0530
> Sunil V L wrote:
>
> > Add Multiple APIC Description Table (MADT) with the
> > RINTC structure for each cpu.
> >
> > Signed-off-by: Sunil V L
> > Acked-by: Alistair Francis
> > Revie
On Wed, 22 Feb 2023 at 02:36, Richard Henderson
wrote:
>
> Test in_space instead of in_secure so that we don't switch
> out of Root space. Handle the output space change immediately,
> rather than try and combine the NSTable and NS bits later.
>
> Signed-off-by: Richard Henderson
> ---
> target
On Tue, 21 Feb 2023 23:04:57 +0700
Bui Quang Minh wrote:
> This commit refactors APIC registers read/write function to support both
> MMIO read/write in xAPIC mode and MSR read/write in x2APIC mode. Also,
> support larger APIC ID, self IPI, new IPI destination determination in
> x2APIC mode.
>
>
On 1/31/23 23:56, Taylor Simpson wrote:
The following improvements are made for predicated HVX instructions
During gen_commit_hvx, unconditionally move the "new" value into
the dest
Don't set slot_cancelled
Remove runtime bookkeeping of which registers were updated
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