Ping !
在 2023/1/12 下午2:11, Song Gao 写道:
For loongarch virt machine, add powerdown notification callback
and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add
acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this
patch.
Signed-off-by: Song Gao
---
hw/loongarch/acpi-build.c | 1
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Add suport to handle SOL_ALG packets via sendmsg() and recvmsg().
This allows emulated userspace to use encryption functionality.
Tested with the debian ell package with hppa guest on x86_64 host.
Signed-off-by: Helge Deller
---
linux-user/syscal
On Tue, Jan 31, 2023 at 5:57 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/30/23 22:00, Bin Meng wrote:
> > On Tue, Jan 31, 2023 at 1:16 AM Daniel Henrique Barboza
> > wrote:
> >>
> >>
> >>
> >> On 1/29/23 02:45, Bin Meng wrote:
> >>> On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza
> >>>
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
msg_controllen=40, msg_flags=0}, MS
On Mon, Jan 30, 2023 at 7:19 AM Alistair Francis wrote:
>
> On Thu, Jan 26, 2023 at 10:03 PM Bin Meng wrote:
> >
> > On Tue, Jan 24, 2023 at 9:42 AM Alistair Francis
> > wrote:
> > >
> > > On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote:
> > > >
> > > > On Mon, Jan 23, 2023 at 11:58 AM Alistai
On 27/01/2023 1:52, Alex Williamson wrote:
External email: Use caution opening links or attachments
On Thu, 26 Jan 2023 20:49:31 +0200
Avihai Horon wrote:
Pre-copy support allows the VFIO device data to be transferred while the
VM is running. This helps to accommodate VFIO devices that hav
On 30/01/2023 15.08, Akihiko Odaki wrote:
This change is derived from qtest for e1000e device.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c | 243 +++
On 31/01/2023 12.53, Bernhard Beschow wrote:
sysbus_add_io() just wraps memory_region_add_subregion() while also
obscuring where the memory is attached. So use
memory_region_add_subregion() directly and attach it to the existing
memory region s->mch.address_space_io which is set as an alias to
ge
Hi Bin,
On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti
> wrote:
> >
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm
On 31/01/2023 12.53, Bernhard Beschow wrote:
No need to repeat the descriptions.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Thomas Huth
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Suggested-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Fran
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
---
hw/riscv/virt.c | 19 ++-
1 file changed,
On 31/01/2023 12.53, Bernhard Beschow wrote:
The Q35_MASK macro is already defined by TYPE_Q35_HOST_DEVICE, so let
TYPE_ICH9_LPC_DEVICE have its own one to prevent potential name clash.
Ouch, good catch!
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 10 +-
1 file ch
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Signed-off-by: Alexandre Ghiti
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Reviewed-by:
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 4).
v9:
- Move valid_vm[i] up, Andrew
- Fixed expansion of the bitmap map, Bin
- Rename set_satp_mode_default into
On 31/01/2023 12.53, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_q35.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 83c57c6eb1..351ef25f69 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -218,7
Currently, the max satp mode is set with the only constraint that it must be
implemented in QEMU, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode wh
On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote:
>
> On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote:
> > RISC-V specifies multiple sizes for addressable memory and Linux probes for
> > the machine's support at startup via the satp CSR register (done in
> > csr.c:validate_vm).
>
On 2023/01/31 22:04, Thomas Huth wrote:
On 30/01/2023 15.08, Akihiko Odaki wrote:
This change is derived from qtest for e1000e device.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/fuzz/generic_fuzz_configs.h | 5 +
tests/qtest/igb-test.c
On 30/01/2023 05.44, Juan Quintela wrote:
Philippe Mathieu-Daudé wrote:
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Juan Quintela
I am assuming that you will pull this patches through tests tree, not
migration tree.
Otherwise, let me know.
I had so
On Sun, 29 Jan 2023, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index b0765d4ed8..2db54d1649 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -33,
On 31/01/2023 15.34, Akihiko Odaki wrote:
On 2023/01/31 22:04, Thomas Huth wrote:
On 30/01/2023 15.08, Akihiko Odaki wrote:
This change is derived from qtest for e1000e device.
Signed-off-by: Akihiko Odaki
---
MAINTAINERS | 2 +
tests/qtest/fuzz/generic_fuzz_c
On 1/31/23 14:34, Helge Deller wrote:
On 1/31/23 13:28, Laurent Vivier wrote:
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_
Le 31/01/2023 à 14:08, Helge Deller a écrit :
On 1/31/23 12:04, Laurent Vivier wrote:
Le 30/01/2023 à 23:11, Helge Deller a écrit :
On 1/30/23 10:26, Laurent Vivier wrote:
Le 27/01/2023 à 21:58, Helge Deller a écrit :
Make the strace look nicer for those two syscalls.
Signed-off-by: Helge De
Hi
On Tue, Jan 31, 2023 at 6:39 PM Daniel P. Berrangé
wrote:
> On Tue, Jan 31, 2023 at 06:31:39PM +0400, Marc-André Lureau wrote:
> > Hi
> >
> > On Mon, Jan 30, 2023 at 1:52 PM Bin Meng wrote:
> >
> > > At present there is no Windows support for 9p file system.
> > > This series adds initial Wi
On Tue, 31 Jan 2023, Akihiko Odaki wrote:
On 2023/01/31 8:58, BALATON Zoltan wrote:
On Sat, 28 Jan 2023, Akihiko Odaki wrote:
On 2023/01/23 8:28, BALATON Zoltan wrote:
On Thu, 19 Jan 2023, Akihiko Odaki wrote:
On 2023/01/15 3:11, BALATON Zoltan wrote:
On Sat, 14 Jan 2023, Akihiko Odaki wrote
On 2023/1/30 22:04, Juan Quintela wrote:
> Jiang Jiacheng wrote:
>> On 2023/1/30 12:28, Juan Quintela wrote:
>>> Jiang Jiacheng wrote:
To support query migration thread infomation, save and delete
thread information at thread creation and end.
Signed-off-by: Jiang Jiacheng
Hi
On Sun, Jan 15, 2023 at 5:10 PM Volker Rümelin wrote:
>
> Based-on: <3b1404eb-a7c5-f64c-3e47-1397c54c4...@t-online.de>
> ([PATCH 00/11] audio: more improvements)
>
Something didn't work with patchew
(https://patchew.org/QEMU/61bd351f-0683-7f58-b746-66c9578a7...@t-online.de/).
If you could reb
On 1/31/23 11:27, Alexander Ivanov wrote:
Set data_end to the end of the last cluster inside the image. In such a
way we can be sure that corrupted offsets in the BAT can't affect on the
image size. If there are no allocated clusters set image_end_offset by
data_end.
Signed-off-by: Alexander Iva
Hi Peter, Daniel,
Just a gentle reminder on this patch if it can be merged, and really sorry i
see now earlier reminders i sent were on v6[0/2] and somehow you were not CCed
on that earlier. You were CCed just on v6[1/2] and v6[2,2] so that's why
probably missed it.
Thanks
Manish Mishra
On
On Mon, Jan 30, 2023 at 06:30:16PM +, Daniel P. Berrangé wrote:
> On Mon, Jan 30, 2023 at 10:17:48AM -0500, Stefan Hajnoczi wrote:
> > On Mon, 30 Jan 2023 at 07:33, Daniel P. Berrangé
> > wrote:
> > >
> > > On Sun, Jan 29, 2023 at 06:39:49PM +0800, Sam Li wrote:
> > > > This patch extends vir
On Sun, 29 Jan 2023, Bernhard Beschow wrote:
This series is part of my work to bring the VIA south bridges to the PC machine
[1]. First it resolves a fixme in the device model by using the dedicated ACPI
interrupt register for SCI routing. It then enables the device model to switch
to ACPI. Final
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
On Mon, Jan 30, 2023 at 5:29 AM Bin Meng wrote:
>
> On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti
> wrote:
> >
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> nits: s/qemu/QEMU/g
Ok
>
> >
> > Bu
On 1/31/23 13:28, Laurent Vivier wrote:
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
On 31/01/2023 12.53, Bernhard Beschow wrote:
By using qdev_get_child_bus() we can eliminate ICH9LPCState::isa_bus and
spare the ich9_lpc variable in pc_q35, too.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 3 ---
hw/i386/pc_q35.c | 4 +---
hw/isa/lpc_ich9.c | 5 +
On 17/01/2023 09.07, Paolo Bonzini wrote:
In order to create a function that allows testing of invalid command
lines, extract the parts of qtest_init_without_qmp_handshake that do
not require any successful set up of sockets.
Signed-off-by: Paolo Bonzini
---
tests/qtest/libqtest.c | 103 +
On 17/01/2023 09.07, Paolo Bonzini wrote:
If a test aborts after qtest_wait_qemu() is called, the SIGABRT hooks are
still in place and waitpid() is called again. The second time it is called,
the process does not exist anymore and the system call fails.
Move the s->qemu_pid = -1 assignment to q
Hi
On Mon, Jan 30, 2023 at 1:52 PM Bin Meng wrote:
> At present there is no Windows support for 9p file system.
> This series adds initial Windows support for 9p file system.
>
> 'local' file system backend driver is supported on Windows,
> including open, read, write, close, rename, remove, etc
On 1/31/23 12:04, Laurent Vivier wrote:
Le 30/01/2023 à 23:11, Helge Deller a écrit :
On 1/30/23 10:26, Laurent Vivier wrote:
Le 27/01/2023 à 21:58, Helge Deller a écrit :
Make the strace look nicer for those two syscalls.
Signed-off-by: Helge Deller
---
v2: Use regpairs_aligned() and target
On 2023/1/30 22:03, Juan Quintela wrote:
> Jiang Jiacheng wrote:
>> On 2023/1/30 12:27, Juan Quintela wrote:
>>> Jiang Jiacheng wrote:
Introduce interface query-migrationthreads. The interface is use
with the migration thread name reported by qemu and returns with
migration thre
On Tue, Jan 31, 2023 at 08:29:08PM +0530, manish.mishra wrote:
> Hi Peter, Daniel,
>
> Just a gentle reminder on this patch if it can be merged, and really
> sorry i see now earlier reminders i sent were on v6[0/2] and somehow you
> were not CCed on that earlier. You were CCed just on v6[1/2] and
Le 31/01/2023 à 14:50, Helge Deller a écrit :
On 1/31/23 14:34, Helge Deller wrote:
On 1/31/23 13:28, Laurent Vivier wrote:
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
msg_controllen=40, msg_flags=0}, MS
On 17/01/2023 09.07, Paolo Bonzini wrote:
Test that invalid configurations do not cause a SIGSEGV, and cover a
valid configuration as well.
Signed-off-by: Paolo Bonzini
---
tests/qtest/libqtest.c| 28 +-
tests/qtest/libqtest.h| 12 ++
tests/qtest/
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Applications do call sendmsg() without any IOV, e.g.:
sendmsg(4, {msg_name=NULL, msg_namelen=0, msg_iov=NULL, msg_iovlen=0,
msg_control=[{cmsg_len=36, cmsg_level=SOL_ALG, cmsg_type=0x2}],
msg_controllen=40, msg_flags=0}, MS
Le 12/12/2022 à 18:34, Helge Deller a écrit :
Add suport to handle SOL_ALG packets via sendmsg() and recvmsg().
This allows emulated userspace to use encryption functionality.
Tested with the debian ell package with hppa guest on x86_64 host.
Signed-off-by: Helge Deller
---
linux-user/syscal
On 31/01/2023 12.53, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Thomas Huth
On 1/31/23 05:18, Thomas Huth wrote:
On 17/01/2023 09.07, Paolo Bonzini wrote:
Test that invalid configurations do not cause a SIGSEGV, and cover a
valid configuration as well.
Signed-off-by: Paolo Bonzini
---
tests/qtest/libqtest.c | 28 +-
tests/qtest/libqtest.h
Hi Everyone,
I hope everyone is doing great. We wanted to check why we do not expose support
for HyperV features in Qemu similar to what we do for normal CPU features via
query-cpu-defs or cpu-model-expansion QMP commands. This support is required
for live migration with HyperV features as hype
On 31/01/2023 12.53, Bernhard Beschow wrote:
sysbus_add_io() just wraps memory_region_add_subregion() while also
obscuring where the memory is attached. So use
memory_region_add_subregion() directly and attach it to the existing
memory region s->bus->address_space_io which is set as an alias to
g
On Thu, 19 Jan 2023, BALATON Zoltan wrote:
Currently -d guest_errors enables logging of different invalid actions
by the guest such as misusing hardware, accessing missing features or
invalid memory areas. The memory access logging can be quite verbose
which obscures the other messages enabled by
On Sun, 29 Jan 2023, Bernhard Beschow wrote:
According to the PCI specification, the hardware is not supposed to use
PCI_INTERRUPT_PIN for interrupt routing. Use the dedicated ACPI
Interrupt Select register for SCI routing instead.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 42
On 1/30/23 22:54, Paolo Bonzini wrote:
When ADCX is followed by ADOX or vice versa, the second instruction's
carry comes from EFLAGS. This is handled by this bit of gen_ADCOX:
tcg_gen_extract_tl(carry_in, cpu_cc_src,
ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1);
Unfortuna
On Sun, 29 Jan 2023, Bernhard Beschow wrote:
Adds missing functionality the real hardware supports.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 2189be6f20.
Hi
On Sat, Jan 21, 2023 at 1:47 PM Volker Rümelin wrote:
>
> A few patches from my audio patch queue.
>
> Patches 1 - 2:
> If a guest selects an unsupported sample rate, an error message is
> currently shown. The first patch takes care to suppress the error
> message and reports with the qemu_log
On 31/01/2023 12.53, Bernhard Beschow wrote:
The variable is redundant to "phb" and is never used by its real type.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_q35.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
Reviewed-by: Thomas Huth
On 1/31/23 11:27, Alexander Ivanov wrote:
We will add more and more checks so we need a better code structure in
parallels_co_check. Let each check performs in a separate loop in a
separate helper.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 81 ++--
On 1/31/23 11:27, Alexander Ivanov wrote:
Exclude out-of-image clusters from allocated and fragmented clusters
calculation.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c b/block/parallels.c
index f9
On Sun, 29 Jan 2023 at 17:10, Stefan Hajnoczi wrote:
>
> Hi Shreyansh, Gerd, and Laurent,
> The last virtio-sound RFC was sent in February last year. It was a
> spare time project. Understandably it's hard to complete the whole
> thing on weekends, evenings, etc. So I wanted to suggest relaunching
On 1/31/23 11:27, Alexander Ivanov wrote:
We will add more and more checks so we need a better code structure
in parallels_co_check. Let each check performs in a separate loop
in a separate helper.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 85
On 1/31/23 11:27, Alexander Ivanov wrote:
All the offsets in the BAT must be lower than the file size.
Fix the check condition for correct check.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/parallels.c b/bloc
On Tue, Jan 31, 2023 at 06:31:39PM +0400, Marc-André Lureau wrote:
> Hi
>
> On Mon, Jan 30, 2023 at 1:52 PM Bin Meng wrote:
>
> > At present there is no Windows support for 9p file system.
> > This series adds initial Windows support for 9p file system.
> >
> > 'local' file system backend driver
On 1/12/23 16:01, Alexander Ivanov wrote:
Cluster offsets must be unique among all the BAT entries. Find duplicate
offsets in the BAT and fix it by copying the content of the relevant
cluster to a newly allocated cluster and set the new cluster offset to the
duplicated entry.
Add host_cluster_in
On 1/12/23 16:01, Alexander Ivanov wrote:
If the check is called during normal work, tracking of the check must be
present in VM logs to have some clues if something going wrong with user's
data.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 18 +-
1 file changed, 9
On 1/12/23 16:01, Alexander Ivanov wrote:
Repair an image at opening if the image is unclean or out-of-image
corruption was detected.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 67 +--
1 file changed, 36 insertions(+), 31 deletions(-)
It was brought to my attention that this bug from 2018 was
still unresolved: 32 bit emulators like QEMU were given
64 bit hashes when running 32 bit emulation on 64 bit systems.
Reported-by: 罗勇刚(Yonggang Luo)
Suggested-by: Theodore Ts'o
Link: https://bugs.launchpad.net/qemu/+bug/1805913
Link
Jiang Jiacheng wrote:
> On 2023/1/30 22:03, Juan Quintela wrote:
>> Jiang Jiacheng wrote:
>>> On 2023/1/30 12:27, Juan Quintela wrote:
1st, it is an int enough for all architectures? I know that for linux
and friends it is, but not sure about windows and other weird systems.
From: Gregory Price
Defines are starting to exceed line length limits, align them for
cleanliness before making modifications.
Signed-off-by: Gregory Price
Signed-off-by: Jonathan Cameron
---
Changes since RFC v4:
Naming consistency improvements.
tests/qtest/cxl-test.c | 84 ++
Now we have some kernel code to test this against (and it looks good)
I'd like to propose this series for upstream following 3 other series
already proposed for inclusion:
a)
https://lore.kernel.org/linux-cxl/20230130143705.11758-1-jonathan.came...@huawei.com/
[PATCH v3 00/10] hw/cxl: CXL emul
From: Gregory Price
This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.
Two new properties have been added to cxl-type3 device initialization:
[volatile-memdev] and [persistent-memdev]
The existing [memdev] property has been deprecated
On Tue, Jan 31, 2023 at 04:38:46PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> Defines are starting to exceed line length limits, align them for
> cleanliness before making modifications.
>
> Signed-off-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
> Changes since RFC
On Tue, Jan 31, 2023 at 04:38:47PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> This commit enables each CXL Type-3 device to contain one volatile
> memory region and one persistent region.
>
> ... snip ...
>
I have no objections to the changes made. I'll test when I finish up a
fe
Add a new function print_raw_param64() to print 64-bit values in the
same way as print_raw_param(). This prevents that qemu_log() is used to
work around the problem that print_raw_param() can only print 32-bit
values when compiled for 32-bit targets.
Additionally convert the existing 64-bit users
From: Sergey Matyukevich
According to priviledged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.
Signed-off-by: S
On 1/12/23 16:01, Alexander Ivanov wrote:
Repair an image at opening if the image is unclean or out-of-image
corruption was detected.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 67 +--
1 file changed, 36 insertions(+), 31 deletions(-)
Stefan Hajnoczi writes:
> On Sun, 29 Jan 2023 at 17:10, Stefan Hajnoczi wrote:
>>
>> Hi Shreyansh, Gerd, and Laurent,
>> The last virtio-sound RFC was sent in February last year. It was a
>> spare time project. Understandably it's hard to complete the whole
>> thing on weekends, evenings, etc.
+ Den
Den, I remember we thought about that, and probably had a solution?
Another possible approach to get benefits from both modes is to switch to
blocking mode after first loop of copying. [*]
Hmm. Thinking about proposed solution it seems, that [*] is better. The main reason of
"write-bloc
On 31/01/23 8:47 pm, Peter Xu wrote:
On Tue, Jan 31, 2023 at 08:29:08PM +0530, manish.mishra wrote:
Hi Peter, Daniel,
Just a gentle reminder on this patch if it can be merged, and really
sorry i see now earlier reminders i sent were on v6[0/2] and somehow you
were not CCed on that earlier. Yo
Le 30/01/2023 à 18:28, ~vlaomao a écrit :
From: VlaoMao
Changing the address with a subsequent reboot makes this address permanent
until the vm is turned off
---
Signed-off-by: Vlao Mao
As the Signed-off-by is part of the commit message it must be set before the signature
signs ("---").
A
From: Christoph Müllner
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA
From: Christoph Müllner
This series introduces support for the T-Head vendor extensions,
which are implemented e.g. in the XuanTie C906 and XuanTie C910:
* XTheadBa
* XTheadBb
* XTheadBs
* XTheadCmo
* XTheadCondMov
* XTheadFMemIdx
* XTheadFmv
* XTheadMac
* XTheadMemIdx
* XTheadMemPair
* XTheadSyn
On Tue, Jan 24, 2023 at 9:44 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop,
> > +int shamt)
> > +{
> > +TCGv rd1 = dest_gpr(ctx, a->rd1);
> > +TCGv rd2
From: Christoph Müllner
This patch adds support for the XTheadCmo ISA extension.
To avoid interfering with standard extensions, decoder and translation
are in its own xthead* specific files.
Future patches should be able to easily add additional T-Head extension.
The implementation does not have
From: Christoph Müllner
This patch adds support for the XTheadBs ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA
From: Christoph Müllner
This patch adds the T-Head C906 to the list of known CPUs.
Selecting this CPUs will automatically enable the available
ISA extensions of the CPUs (incl. vendor extensions).
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
C
From: Christoph Müllner
This patch adds support for the T-Head MemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use single
From: Christoph Müllner
This patch adds support for the XTheadFmv ISA extension.
The patch uses the T-Head specific decoder and translation.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
target/riscv/cpu.c | 2 +
target/
From: Christoph Müllner
This patch adds support for the XTheadCondMov ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Fix inval
From: Christoph Müllner
There are no differences for floating point instructions in priv version 1.11
and 1.12. There is also no dependency for Zfh to priv version 1.12.
Therefore allow Zfh to be enabled for priv version 1.11.
Acked-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
ta
On Tue, Jan 24, 2023 at 10:26 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +++ b/target/riscv/cpu.h
> > @@ -27,6 +27,7 @@
> > #include "qom/object.h"
> > #include "qemu/int128.h"
> > #include "cpu_bits.h"
> > +#include "cpu_vendorid.h"
>
> I don't see that
From: Christoph Müllner
This patch adds support for the T-Head MAC instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use single de
From: Christoph Müllner
The XThead* extensions are maintained by T-Head and VRULL.
Adding a point of contact from both companies.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git
From: Christoph Müllner
This patch adds support for the XTheadSync ISA extension.
The patch uses the T-Head specific decoder and translation.
The implementation introduces a helper to execute synchronization tasks:
helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs.
Co-develop
From: Christoph Müllner
This patch adds support for the XTheadBb ISA extension.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: Philipp Tomsich
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA
On Tue, Jan 24, 2023 at 10:21 PM Richard Henderson
wrote:
>
> On 1/24/23 09:59, Christoph Muellner wrote:
> > +/* XTheadMemIdx */
> > +
> > +/*
> > + * Load with memop from indexed address and add (imm5 << imm2) to rs1.
> > + * If !preinc, then the load address is rs1.
> > + * If preinc, then the
From: Christoph Müllner
This patch adds support for the T-Head MemPair instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use singl
Anthony Perard recently reported some problems with Clang v6.0 from
Ubuntu Bionic (with regards to the -Wmissing-braces configure test).
Since we're not officially supporting that version of Ubuntu anymore,
we should better bump our minimum version check in the configure script
instead of using our
From: Christoph Müllner
This patch adds support for the T-Head FMemIdx instructions.
The patch uses the T-Head specific decoder and translation.
Co-developed-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Signed-off-by: Christoph Müllner
---
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Use singl
On 1/31/23 08:02, Thomas Huth wrote:
Anthony Perard recently reported some problems with Clang v6.0 from
Ubuntu Bionic (with regards to the -Wmissing-braces configure test).
Since we're not officially supporting that version of Ubuntu anymore,
we should better bump our minimum version check in th
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