Am 26.01.23 um 21:13 schrieb Stefan Hajnoczi:
> When a write request is converted into a write zeroes request by the
> detect-zeroes= feature, it is no longer associated with an I/O buffer.
> The BDRV_REQ_REGISTERED_BUF flag doesn't make sense without an I/O
> buffer and must be cleared because bdr
On Fri, 27 Jan 2023 at 00:58, Gerd Hoffmann wrote:
>
> Cc: Sergio Lopez
> Suggested-by: Stefan Hajnoczi
> Signed-off-by: Gerd Hoffmann
> ---
> docs/system/i386/microvm.rst | 52 +---
> 1 file changed, 19 insertions(+), 33 deletions(-)
Thank you!
Acked-by: Stef
Am 26/01/2023 um 18:24 schrieb Kevin Wolf:
> bdrv_open*() must not be called from coroutine context, amongst others
> because it modifies the block graph. However, some functions - in
> particular all .bdrv_co_create* implementations of image formats - do
> call it from coroutine context. This i
Add some documentation about the zpci device and how
to use it with pci devices on s390x.
Used source: Cornelia Huck's blog post
https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html
Signed-off-by: Sebastian Mitterle
---
v2: move section below 'Device support'
---
docs/system/
Hi,
> Scratch that, it is actually possible to configure private runners
> to pick up un-tagged jobs
>
> https://docs.gitlab.com/ee/ci/runners/configure_runners.html#runner-is-allowed-to-run-untagged-jobs
>
> i'm not sure what the prioritization is between shared and private
> runners when us
On 20/01/2023 13:13, David Woodhouse wrote:
From: David Woodhouse
Include basic support for setting HVM_PARAM_CALLBACK_IRQ to the global
vector method HVM_PARAM_CALLBACK_TYPE_VECTOR, which is handled in-kernel
by raising the vector whenever the vCPU's vcpu_info->evtchn_upcall_pending
flag is se
On 20/01/2023 13:13, David Woodhouse wrote:
From: David Woodhouse
This adds the basic structure for maintaining the port table and reporting
the status of ports therein.
Signed-off-by: David Woodhouse
---
hw/i386/kvm/xen_evtchn.c | 104 ++
hw/i386/kvm/x
On 27/01/2023 09.46, Sebastian Mitterle wrote:
Add some documentation about the zpci device and how
to use it with pci devices on s390x.
Thanks for tackling this! ... some comments below...
Used source: Cornelia Huck's blog post
https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s39
If this backpressure leads us to less waste of time & energy (close &
personal: faster make check), then I <3 gitlab!
On Sun, Jan 15, 2023 at 1:40 PM Or Ozeri wrote:
>
> v5: nit fixes
> v4: split to multiple commits
> add support for more than just luks-any in layered encryption
> nit fixes
> v3: further nit fixes suggested by @idryomov
> v2: nit fixes suggested by @idryomov
>
> Or Ozeri (3):
> block/rb
On Sun, Jan 15, 2023 at 1:40 PM Or Ozeri wrote:
>
> Starting from ceph Reef, RBD has built-in support for layered encryption,
> where each ancestor image (in a cloned image setting) can be possibly
> encrypted using a unique passphrase.
>
> A new function, rbd_encryption_load2, was added to librbd
On Thu, Jan 26, 2023 at 06:41:50PM +, Eldon Stegall wrote:
> As far as baremetal goes, I find authenticated IPXE scripts work well
> for a number of these scenarios, and permit very dynamic allocation of
> resources. I have been a fan of the ignition/coreos/fcos strategy for
> baremetal deploy
On Thu, 26 Jan 2023 21:57:35 +
Fan Ni wrote:
> On Wed, Jan 25, 2023 at 03:27:03PM +, Jonathan Cameron wrote:
>
> > The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> > Host Bridges if they have only a single root port. Instead, all accesses
> > directed to the hos
On Fri, Jan 27 2023, Sebastian Mitterle wrote:
> Add some documentation about the zpci device and how
> to use it with pci devices on s390x.
>
> Used source: Cornelia Huck's blog post
> https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html
>
> Signed-off-by: Sebastian Mitterle
Le 26/01/2023 à 23:12, Mark Cave-Ayland a écrit :
On 26/01/2023 12:52, Laurent Vivier wrote:
In linux-user mode, 'bkpt' generates an EXP_DEBUG exception to allow
QEMU gdb server to intercept and manage the operation with an external
debugger.
In softmmu mode, the instruction must generate an i
Resend as attachment as the previous version gots corrupted.From abea41b457aff4c04c3aa397b88847b66aaff1ad Mon Sep 17 00:00:00 2001
From: Bernhard Kauer
Date: Fri, 20 Jan 2023 21:33:04 +
Subject: [PATCH 2/2] target/i386: Change CR4 before CR0 in SVM
There is a dependency in cpu_x86_update_cr0(
Warner Losh writes:
[...]
> So I'm happy with it. Thanks for the cleanup and the time to answer my
> questions.
>
> Reviewed-by: Warner Losh
Thank *you* for reviewing my patch :)
if we used const16 == 0 we would crash qemu with the error:
../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed
This is a special case anyways as we can directly return cpu_gpr_d[r1]
as this is the most significant word an nothing is shifted.
Signed-off-by: Bastian K
we were sign extending the result of the load, while the instruction
clearly states that the result should be unsigned.
Signed-off-by: Bastian Koppelmann
---
target/tricore/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/tricore/translate.c b/target/tricore
if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the
right by 32 which is undefined behaviour. In this case the TriCore would
do nothing an just return the higher register cpu_reg_d[r1]. We fixed
that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower
register.
Sign
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
---
target/tricore/tran
we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.
Signed-off-by: Bastian Koppelmann
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
---
target/tricore/tran
Hi,
while resolving [1], I noticed a few more bugs in DEXTR and LD_BU_PREINC which
this patch series fixes.
I also included the solo patch [1] into this series.
Cheers,
Bastian
[1] https://gitlab.com/qemu-project/qemu/-/issues/653
[2]
https://lore.kernel.org/qemu-devel/20230113123759.677960-1
Philippe Mathieu-Daudé writes:
> On 19/1/23 12:41, Markus Armbruster wrote:
>> Philippe Mathieu-Daudé writes:
>>
>>> On 19/1/23 07:59, Markus Armbruster wrote:
This commit was created with scripts/clean-includes.
Signed-off-by: Markus Armbruster
>> [...]
>>
>>> Up to here:
>>>
>>> R
On Fri, Jan 27, 2023 at 10:24 AM Thomas Huth wrote:
>
> On 27/01/2023 09.46, Sebastian Mitterle wrote:
> > Add some documentation about the zpci device and how
> > to use it with pci devices on s390x.
>
> Thanks for tackling this! ... some comments below...
>
> > Used source: Cornelia Huck's blog
Richard Henderson writes:
> These will be used by some hosts, both 32 and 64-bit, to pass and
> return i128. Not yet used, because allocation is not yet enabled.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg-internal.h | 3 +
> tcg/tcg.c | 135 ++
On Fri, Jan 27, 2023 at 11:30 AM Cornelia Huck wrote:
>
> On Fri, Jan 27 2023, Sebastian Mitterle wrote:
>
> > Add some documentation about the zpci device and how
> > to use it with pci devices on s390x.
> >
> > Used source: Cornelia Huck's blog post
> > https://people.redhat.com/~cohuck/2018/02
Update register value per its P10 DD2 definition.
Signed-off-by: Frederic Barrat
---
include/hw/pci-host/pnv_phb4.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 761525686e..28d61b96c7 100644
--- a/includ
The name is for the region mapping the PHB xscom registers. It was
apparently a bad cut-and-paste from the per-stack pci xscom area just
above, so we had two regions with the same name.
Signed-off-by: Frederic Barrat
---
hw/pci-host/pnv_phb4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
Remove unused structure member 'system_memory'.
Signed-off-by: Frederic Barrat
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 1f3237c9d5..17aef08f91 100644
--- a/include/hw/pci-host/pnv
Pretty simple PCI-related cleanup for powernv
Frederic Barrat (4):
ppc/pnv/pci: Cleanup PnvPHBPecState structure
ppc/pnv/pci: Remove duplicate definition of PNV_PHB5_DEVICE_ID
ppc/pnv/pci: Update PHB5 version register
ppc/pnv/pci: Fix PHB xscom registers memory region name
hw/pci-host/pn
PNV_PHB5_DEVICE_ID is defined in two different headers. The definition
in hw/pci-host/pnv_phb4.h was left out in a previous rework.
Remaining definition is in hw/pci-host/pnv_phb.h.
Signed-off-by: Frederic Barrat
---
include/hw/pci-host/pnv_phb4.h | 1 -
1 file changed, 1 deletion(-)
diff --gi
Add some documentation about the zpci device and how
to use it with pci devices on s390x.
Used source: Cornelia Huck's blog post
https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html
Signed-off-by: Sebastian Mitterle
Reviewed-by: C??dric Le Goater
---
v3: add info zpci is auto
Am 26.01.2023 um 15:28 hat Peter Maydell geschrieben:
> On Thu, 26 Jan 2023 at 14:25, Stefan Hajnoczi wrote:
> >
> > Are you batching pull requests? I used that approach last release
> > cycle. CI takes so long to run that I didn't want to run it for every
> > pull request. Batching worked well ov
On Fri, Jan 27, 2023 at 01:39:08PM +0100, Kevin Wolf wrote:
> Am 26.01.2023 um 15:28 hat Peter Maydell geschrieben:
> > On Thu, 26 Jan 2023 at 14:25, Stefan Hajnoczi wrote:
> > >
> > > Are you batching pull requests? I used that approach last release
> > > cycle. CI takes so long to run that I did
On Thu, Jan 26, 2023 at 10:42:31AM +, Bernhard Beschow wrote:
>
>
> Am 25. Januar 2023 16:52:34 UTC schrieb Igor Mammedov :
> >On Sat, 21 Jan 2023 16:19:34 +0100
> >Bernhard Beschow wrote:
> >
> >> This series factors out AcpiCpuAmlIfClass::madt_cpu from AcpiDeviceIfClass.
> >> By letting th
On Fri, Jan 27 2023, Sebastian Mitterle wrote:
> Add some documentation about the zpci device and how
> to use it with pci devices on s390x.
>
> Used source: Cornelia Huck's blog post
> https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html
>
> Signed-off-by: Sebastian Mitterle
On Fri, 27 Jan 2023 at 12:39, Kevin Wolf wrote:
>
> Am 26.01.2023 um 15:28 hat Peter Maydell geschrieben:
> > On Thu, 26 Jan 2023 at 14:25, Stefan Hajnoczi wrote:
> > >
> > > Are you batching pull requests? I used that approach last release
> > > cycle. CI takes so long to run that I didn't want
On Fri, 27 Jan 2023 at 13:11, Peter Maydell wrote:
>
> On Fri, 27 Jan 2023 at 12:39, Kevin Wolf wrote:
> >
> > Am 26.01.2023 um 15:28 hat Peter Maydell geschrieben:
> > > On Thu, 26 Jan 2023 at 14:25, Stefan Hajnoczi wrote:
> > > >
> > > > Are you batching pull requests? I used that approach las
On Mon, Jan 16, 2023 at 03:06:44PM +0800, Jason Wang wrote:
> On Mon, Jan 16, 2023 at 7:30 AM Viktor Prutyanov wrote:
> >
> > On Tue, Nov 29, 2022 at 11:10 AM Jason Wang wrote:
> > >
> > > Hi All:
> > >
> > > According to ATS, device should work if ATS is disabled. This is not
> > > correctly imp
On Mon, Jan 16, 2023 at 04:11:23PM +0200, Avihai Horon wrote:
> Update to commit 1b929c02afd3 ("Linux 6.2-rc1").
>
> Signed-off-by: Avihai Horon
Reviewed-by: Michael S. Tsirkin
> ---
> include/standard-headers/drm/drm_fourcc.h | 63 +++-
> include/standard-headers/linux/ethtool.h |
On Sun, Jan 15, 2023 at 07:49:51PM -0500, Chuck Zmudzinski wrote:
> The current reserved slot check in do_pci_register_device(), added with
> commit 8b8849844fd6
add ("subject here") please
> ,is done even if the pci device being added is
> configured manually for a particular slot. The new prope
On Fri, 6 Jan 2023 00:38:22 -0800
Lei Wang wrote:
> Parameter "uint32_t bit" is not used in function feature_word_description(),
> so remove it.
>
> Signed-off-by: Lei Wang
Reviewed-by: Igor Mammedov
> ---
> target/i386/cpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
On Tue, Jan 17, 2023 at 02:56:50PM +, Raphael Norwitz wrote:
> I’m confused by this “one time request” path.
>
> MST - why do we classify SET_MEM_TABLE as a one time request if we send it on
> every hot-add/hot-remove.
>
> In particular I’m tripping over the following in vhost_user_write:
>
Richard Henderson writes:
> We are about to allow passing Int128 to/from tcg helper functions,
> but libffi doesn't support __int128_t, so use the structure.
>
> In order for atomic128.h to continue working, we must provide
> a mechanism to frob between real __int128_t and the structure.
> Prov
Richard Henderson writes:
> Fill in the parameters for the host ABI for Int128.
> Adjust tcg_target_call_oarg_reg for _WIN64, and
> tcg_out_call for i386 sysv. Allow TCG_TYPE_V128
> stores without AVX enabled.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Vi
Richard Henderson writes:
> We expect the backend to require register pairs in
> host-endian ordering, thus for big-endian the first
> register of a pair contains the high part.
> We were forcing R0 to contain the low part for calls.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Ric
Richard Henderson writes:
> Fill in the parameters for libffi for Int128.
> Adjust the interpreter to allow for 16-byte return values.
> Adjust tcg_out_call to record the return value length.
>
> Call parameters are no longer all the same size, so we
> cannot reuse the same call_slots array for
On 1/27/23 09:46, Sebastian Mitterle wrote:
Add some documentation about the zpci device and how
to use it with pci devices on s390x.
Used source: Cornelia Huck's blog post
https://people.redhat.com/~cohuck/2018/02/19/notes-on-pci-on-s390x.html
Signed-off-by: Sebastian Mitterle
Reviewed-by:
On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote:
>
> Also, why didn't you move sys/resource.h and other such files
> to os-dep.h? I'm struggling to understand the rules around what
> is or isn't included where?
The rough rule of thumb is that if some OS needs a compatibility
fixup or workaround f
On Fri, Jan 27, 2023 at 02:54:30PM +, Peter Maydell wrote:
> On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote:
> >
> > Also, why didn't you move sys/resource.h and other such files
> > to os-dep.h? I'm struggling to understand the rules around what
> > is or isn't included where?
>
> The rough
Although the VM type does not affect values probed from the scratch vCPU
at the moment, it could later. Ensure we specify the right type when
creating the temporary VM.
Signed-off-by: Jean-Philippe Brucker
---
Does the PA size need changing as well?
---
target/arm/kvm.c | 5 -
1 file changed
The Arm Realm Management Extension (RME), part of the Arm Confidential
Computing Architecture (CCA), enables running confidential virtual
machines in a new "Realm" security state. While the host still manages
the resources of a guest running in a Realm, it cannot access them.
This series adds some
The Realm configuration takes a SVE enable and vector length parameter.
We cannot reuse the -cpu SVE parameters for this because that
information is needed at Realm Descriptor creation which must happen
before VCPU creation.
Signed-off-by: Jean-Philippe Brucker
---
qapi/qom.json| 5 +++
When using the Arm RME, register the images to be loaded into Realm
memory at boot. Two operations are needed for each image:
(1) INIT_IPA_REALM: mark the load addresses (IPA) as RAM with
RMI_RTT_INIT_RIPAS.
(2) POPULATE_REALM: move the page into the Realm with RMI_DATA_CREATE.
Its content
Add a new RmeGuest object, inheriting from ConfidentialGuestSupport, to
support the Arm Realm Management Extension (RME). It is instantiated by
passing on the command-line:
-M virt,confidential-guest-support=
-object guest-rme,id=[,options...]
This is only the skeleton. Support will be added
KVM does not support creating read-only mappings for realms at the
moment. Add an arch helper to detect whether read-only mappings are
supported.
Device ROM and flash normally use read-only mappings. Device ROM seems
limited to legacy use and does not need to be trusted by the guest, so
trapping r
The machine code calls kvm_arm_rme_vm_type() to get the VM flag and
kvm_arm_rme_init() to issue KVM hypercalls in the required order:
* create the realm descriptor early,
* finalize the REC (vCPU) after the registers are reset,
* load images into Realm RAM (in another patch),
* activate the realm
The confidential guest support in KVM limits the number of registers
that we can read and write. Split the get/put_registers function to
prepare for it.
Signed-off-by: Jean-Philippe Brucker
---
target/arm/kvm64.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(
A realm cannot be reset, it must be recreated from scratch. The RMM
specification defines states of a Realm as NEW -> ACTIVE -> SYSTEM_OFF,
after which the Realm can only be destroyed. A PCSI_SYSTEM_RESET call,
which normally reboots the system, puts the Realm in SYSTEM_OFF state.
QEMU does not su
When confidential-guest-support is enabled for the virt machine, call
the RME init function, and add the RME flag to the VM type.
* The Realm differentiates non-secure from realm memory using the upper
GPA bit. Reserve that bit when creating the memory map, to make sure
that device MMIO locate
The target code calls kvm_arm_vcpu_init() to mark the vCPU as part of a
realm. RME support does not use the register lists, because the host can
only set the boot PC and registers x0-x7. The rest is private to the
Realm and saved/restored by the RMM.
Signed-off-by: Jean-Philippe Brucker
---
targ
Dear QEMU, KVM, and rust-vmm communities,
QEMU will apply for Google Summer of Code 2023
(https://summerofcode.withgoogle.com/) and has been accepted into
Outreachy May 2023 (https://www.outreachy.org/). You can now
submit internship project ideas for QEMU, KVM, and rust-vmm!
Please reply to this
This option selects which measurement algorithm to use for attestation.
Supported values are sha256 and sha512.
Signed-off-by: Jean-Philippe Brucker
---
qapi/qom.json| 14 -
target/arm/kvm-rme.c | 71
2 files changed, 84 insertions(+),
Copy the KVM definitions for Arm RME from the development branch.
Don't merge, they will be added from the periodic Linux header sync.
Signed-off-by: Jean-Philippe Brucker
---
linux-headers/asm-arm64/kvm.h | 63 +++
linux-headers/linux/kvm.h | 21 +---
The Realm Personalization Value (RPV) is provided by the user to
distinguish Realms that have the same initial measurement.
The user provides a 512-bit hexadecimal number.
Signed-off-by: Jean-Philippe Brucker
---
qapi/qom.json| 5 ++-
target/arm/kvm-rme.c | 72 +
Initialize the GPA space and populate it with boot images (kernel,
initrd, firmware, etc). Populating has to be done at VM start time,
because the images are loaded during reset by rom_reset()
Signed-off-by: Jean-Philippe Brucker
---
target/arm/kvm_arm.h | 6
target/arm/kvm-rme.c | 79
Pass the num_cntrs parameter to Realm creation. These parameters
contribute to the initial Realm measurement.
Signed-off-by: Jean-Philippe Brucker
---
qapi/qom.json| 5 -
target/arm/kvm-rme.c | 21 -
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a
Pass the num_bps and num_wps parameters to Realm creation. These
parameters contribute to the initial Realm measurement.
Signed-off-by: Jean-Philippe Brucker
---
qapi/qom.json| 8 +++-
target/arm/kvm-rme.c | 34 +-
2 files changed, 40 insertions(+), 2
On 26.01.23 22:01, Richard Henderson wrote:
On 1/26/23 01:27, David Hildenbrand wrote:
static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
@@ -5419,6 +5410,14 @@ static void prep_r1_P(DisasContext *s, DisasOps *o)
}
#define SPEC_prep_r1_P SPEC_r1_even
+static void prep_r1_D64(Dis
On 1/27/23 13:28, Frederic Barrat wrote:
PNV_PHB5_DEVICE_ID is defined in two different headers. The definition
in hw/pci-host/pnv_phb4.h was left out in a previous rework.
Remaining definition is in hw/pci-host/pnv_phb.h.
> Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Tha
On 1/27/23 13:28, Frederic Barrat wrote:
Remove unused structure member 'system_memory'.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/pci-host/pnv_phb4.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4.h b/inc
On 1/27/23 13:28, Frederic Barrat wrote:
Update register value per its P10 DD2 definition.
Signed-off-by: Frederic Barrat
Indeed :
mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
include/hw/pci-host/pnv_phb4.h | 2 +-
1 f
On 1/27/23 13:28, Frederic Barrat wrote:
The name is for the region mapping the PHB xscom registers. It was
apparently a bad cut-and-paste from the per-stack pci xscom area just
above, so we had two regions with the same name.
Signed-off-by: Frederic Barrat
Reviewed-by: Cédric Le Goater
Tha
Rather than using get_system_io() as the parent memory region, use
s->bus->address_space_io which is set up as an alias in the pc machine.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/i440fx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/i440fx.c b/hw/p
On Thu, Jan 19, 2023 at 03:14:07PM +0800, zhenwei pi wrote:
> v2 -> v3:
> - rebase code against the lastest commist: fb7e7990342e59cf67d
> - document the missing fields in qapi/cryptodev.json
> - rework statistics part: use 'query-stats' command instead of
> 'query-cryptodev'(cryptodev: Support q
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index ee9d9a4175..5bde4533cc 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -241,7 +241,7 @@
The Q35_MASK macro is already defined by TYPE_Q35_HOST_DEVICE, so let
TYPE_ICH9_LPC_DEVICE have its own one to prevent potential name
collisions.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/ich9.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/hw/i
No need to repeat the descriptions.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_piix.c | 2 +-
hw/i386/pc_q35.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index df64dd8dcc..ee9d9a4175 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i3
Rather than using get_system_io() as the parent memory region, use
s->mch.address_space_io which is set up as an alias in the q35 machine.
Signed-off-by: Bernhard Beschow
---
hw/pci-host/q35.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-ho
This series contains some random trivial cleanups I came across when working on
the PC machines. It consists of reducing the usage of global variables and
eliminating some redundancies.
Testing done:
* `make check`
* `qemu-system-x86_64 -M q35 -m 2G -cdrom \
manjaro-kde-21.3.2-220704-linux515.i
The variable is redundant to "phb" and is never used by its real type.
Signed-off-by: Bernhard Beschow
---
hw/i386/pc_q35.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 83c57c6eb1..dc94ce1081 100644
--- a/h
Going through pc_memory_init() seems quite complicated for a simple
assignment.
Signed-off-by: Bernhard Beschow
---
include/hw/i386/pc.h | 1 -
hw/i386/pc.c | 2 --
hw/i386/pc_piix.c| 4 ++--
hw/i386/pc_q35.c | 5 ++---
4 files changed, 4 insertions(+), 8 deletions(-)
diff --git
On Fri, Jan 27, 2023 at 10:01:49AM +, Jonathan Cameron wrote:
> On Thu, 26 Jan 2023 21:57:35 +
> Fan Ni wrote:
>
> > On Wed, Jan 25, 2023 at 03:27:03PM +, Jonathan Cameron wrote:
> >
> > > The CXL r3.0 specification allows for there to be no HDM decoders on CXL
> > > Host Bridges if
Richard Henderson writes:
> Fill in the parameters for the host ABI for Int128 for
> those backends which require no extra modification.
>
> Reviewed-by: Daniel Henrique Barboza
> Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
Richard Henderson writes:
> This enables allocation of i128. The type is not yet
> usable, as we have not yet added data movement ops.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Richard Henderson
> ---
> include/tcg/tcg.h | 32 +
> tcg/tcg.c | 6
[[ cc list trimmed to just qemu-devel ]]
On Fri, Jan 27, 2023 at 8:18 AM Stefan Hajnoczi wrote:
> Dear QEMU, KVM, and rust-vmm communities,
> QEMU will apply for Google Summer of Code 2023
> (https://summerofcode.withgoogle.com/) and has been accepted into
> Outreachy May 2023 (https://www.outre
On 1/25/23 21:22, Eugenio Perez Martin wrote:
Caution: This message originated from an External Source. Use proper caution
when opening attachments, clicking links, or responding.
On Wed, Jan 25, 2023 at 4:20 PM David Edmondson
wrote:
On Tuesday, 2023-01-24 at 17:11:59 +01, Eugenio Pérez w
On Fri, 27 Jan 2023 17:02:36 +
Fan Ni wrote:
> On Fri, Jan 27, 2023 at 10:01:49AM +, Jonathan Cameron wrote:
>
> > On Thu, 26 Jan 2023 21:57:35 +
> > Fan Ni wrote:
> >
> > > On Wed, Jan 25, 2023 at 03:27:03PM +, Jonathan Cameron wrote:
> > >
> > > > The CXL r3.0 specificat
The HSTR_EL2 register is not supposed to have an effect unless EL2 is
enabled in the current security state. We weren't checking for this,
which meant that if the guest set up the HSTR_EL2 register we would
incorrectly trap even for accesses from Secure EL0 and EL1.
Add the missing checks. (Other
This series implements the FEAT_FGT fine-grained traps architectural
feature. The bulk of this is new system registers HFGRTR_EL2, HFGWTR_EL2,
HFGITR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, which have bits that enable
trapping of system register and system instruction accesses on a
fine-grained basis (typic
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 0..11.
Signed-off-by: Peter Maydell
---
The annotation of the cpreg definitions is split into multiple
patches for ease of review, 12 bits or so at a time.
---
target/arm/cpregs.h | 14 ++
target/arm/helpe
Define the system registers which are provided by the
FEAT_FGT fine-grained trap architectural feature:
HFGRTR_EL2, HFGWTR_EL2, HDFGRTR_EL2, HDFGWTR_EL2, HFGITR_EL2
All these registers are a set of bit fields, where each bit is set
for a trap and clear to not trap on a particular system register
Mark up the sysreg definitions for the registers trapped
by HFGRTR/HFGWTR bits 36..63.
Of these, some correspond to RAS registers which we implement as
always-UNDEF: these don't need any extra handling for FGT because the
UNDEF-to-EL1 always takes priority over any theoretical
FGT-trap-to-EL2.
Bi
The encodings 0,0,C7,C9,0 and 0,0,C7,C9,1 are AT SP1E1RP and AT
S1E1WP, but our ARMCPRegInfo definitions for them incorrectly name
them AT S1E1R and AT S1E1W (which are entirely different
instructions). Fix the names.
(This has no guest-visible effect as the names are for debug purposes
only.)
S
Mark up the sysreg definitions for the system instructions
trapped by HFGITR bits 12..17. These bits cover AT address
translation instructions.
Signed-off-by: Peter Maydell
---
target/arm/cpregs.h | 6 ++
target/arm/helper.c | 6 ++
2 files changed, 12 insertions(+)
diff --git a/target/
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64). We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should
Mark up the sysreg definitions for the registers trapped
by HDFGRTR/HDFGWTR bits 12..x.
Bits 12..22 and bit 58 are for PMU registers.
The remaining bits in HDFGRTR/HDFGWTR are for traps on
registers that are part of features we don't implement:
Bits 23..32 and 63 : FEAT_SPE
Bits 33..48 : FEAT_ET
The semantics of HSTR_EL2 require that it traps cpreg accesses
to EL2 for:
* EL1 accesses
* EL0 accesses, if the access is not UNDEFINED when the
trap bit is 0
(You can see this in the I_ZFGJP priority ordering, where HSTR_EL2
traps from EL1 to EL2 are priority 12, UNDEFs are priority 13, and
FEAT_FGT also implements an extra trap bit in the MDCR_EL2 and
MDCR_EL3 registers: bit TDCC enables trapping of use of the Debug
Comms Channel registers OSDTRRX_EL1, OSDTRTX_EL1, MDCCSR_EL0,
MDCCINT_EL0, DBGDTR_EL0, DBGDTRRX_EL0 and DBGDTRTX_EL0 (and their
AArch32 equivalents). This trapping is in
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