Hi Bernhard,
On 22/1/23 18:07, Bernhard Beschow wrote:
A MemoryRegion has an addr attribute which gets set to the same values
as the redundant io_addr attributes.
Signed-off-by: Bernhard Beschow
---
include/hw/acpi/ich9.h | 1 -
include/hw/acpi/piix4.h | 2 --
hw/acpi/ich9.c |
On 22/1/23 18:07, Bernhard Beschow wrote:
Signed-off-by: Bernhard Beschow
---
hw/acpi/core.c | 5 +
hw/acpi/piix4.c | 3 ---
hw/acpi/trace-events | 8
3 files changed, 9 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 20/01/2023 19.48, Fabiano Rosas wrote:
Now that the cortex-a15 is under CONFIG_TCG, use as default CPU for a
KVM-only build the 'max' cpu.
Note that we cannot use 'host' here because the qtests can run without
any other accelerator (than qtest) and 'host' depends on KVM being
enabled.
Signed
On 1/18/23 09:11, Richard Henderson wrote:
Adjust the constraints to allow any int32_t for immediate
addition. Split immediate adds into addu16i + addi, which
covers quite a lot of the immediate space. For the hole in
the middle, load the constant into TMP0 instead.
Signed-off-by: Richard Hend
On 1/18/23 09:11, Richard Henderson wrote:
Split out a helper function, tcg_out_setcond_int, which
does not always produce the complete boolean result, but
returns a set of flags to do so.
Accept all int32_t as constant input, so that LE/GT can
adjust the constant to LT.
Signed-off-by: Richard
On Thu, 19 Jan 2023 18:24:22 +0100
Greg Kurz wrote:
> The nested event loop was introduced in QEMU 6.0 to allow servicing
> of requests coming from the slave channel while waiting for an ack
> from the back-end on the master socket. It turns out this is fragile
> and breaks if the servicing of th
On 30/12/22 23:07, Jason A. Donenfeld wrote:
The setup_data links are appended to the compressed kernel image. Since
the kernel image is typically loaded at 0x10, setup_data lives at
`0x10 + compressed_size`, which does not get relocated during the
kernel's boot process.
The kernel typic
On 18/1/23 02:11, Richard Henderson wrote:
Take the w^x split into account when computing the
pc-relative distance to an absolute pointer.
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philippe Mathi
On 18/1/23 02:11, Richard Henderson wrote:
Regenerate with ADDU16I included:
$ cd loongarch-opcodes/scripts/go
$ go run ./genqemutcgdefs > $QEMU/tcg/loongarch64/tcg-insn-defs.c.inc
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-insn-defs.c.inc | 10 +-
1 file chang
On 21/1/23 21:35, BALATON Zoltan wrote:
Some small trivial clean ups I've found while looking at this file.
BALATON Zoltan (3):
hw/display/sm501: Remove parenthesis around consant macro definitions
hw/display/sm501: Remove unneeded casts from void pointer
hw/display/sm501: Code style fi
From: Daniel P. Berrangé
Currently the -audiodev accepts any audiodev type regardless of what is
built in to QEMU. An error only occurs later at runtime when a sound
device tries to use the audio backend.
With this change QEMU will immediately reject -audiodev args that are
not compiled into the
On 1/18/23 09:11, Richard Henderson wrote:
The old implementation replaces two insns, swapping between
b
nop
and
pcaddu18i tmp,
jirl zero, tmp, & 0x
There is a race condition in which a thread could be stopped at
the jirl, i.e. with the top
On 20/1/23 16:54, Evgeny Iakovlev wrote:
UART should be enabled in general and have RX enabled specifically to be
able to receive data from peripheral device. Same goes for transmitting
data to peripheral device and a TXE flag.
Check if UART CR register has EN and RXE or TXE bits enabled before
From: Daniel P. Berrangé
Way back in QEMU 4.0, the -audiodev command line option was introduced
for configuring audio backends. This CLI option does not use QemuOpts
so it is not visible for introspection in 'query-command-line-options',
instead using the QAPI Audiodev type. Unfortunately there
Here's a respin from Daniel's audiodev introspection patches from
2021. I've rebased them to the current master branch and addressed
the review comments from v1.
The Audiodev QAPI type is not introspectable via query-qmp-schema as
nothing in QMP uses it. "-audiodev" is not introspectable via
query
On 18/1/23 02:11, Richard Henderson wrote:
Reuse the decodetree based disassembler from
target/loongarch/ for tcg/loongarch64/.
The generation of decode-insns.c.inc into ./libcommon.fa.p/ could
eventually result in conflict, if any other host requires the same
trick, but this is good enough for
This patch adds support for gl=on and port != 0. In other words,
with this option enabled, it should be possible to stream the
content associated with the dmabuf to a remote client.
Here is the flow of things from the Qemu side:
- Call gl_scanout (to update the fd) and gl_draw_async just like
in
This patch series adds options to select a preferred codec and also
to forward a dmabuf directly to the encoder module that is part of
the Spice server. Currently, gstreamer:h264 is the only combination
tested but additional work is ongoing to test other combinations.
Tested with: -device virtio-
On 20.01.23 14:47, Daniil Tatianin wrote:
This series introduces new qemu_prealloc_mem_with_timeout() api,
which allows limiting the maximum amount of time to be spent on memory
preallocation. It also adds prealloc statistics collection that is
exposed via an optional timeout handler.
This new a
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax. In addition, it prevents cpus to boot in a
satp mode they do not support (see patch 5).
v6:
- Remove the valid_vm check in validate_vm and add it to the finalize function
so that map already conta
This array is actually used as a boolean so swap its current char type
to a boolean and at the same time, change the type of validate_vm to
bool since it returns valid_vm_1_10_[32|64].
Signed-off-by: Alexandre Ghiti
---
target/riscv/csr.c | 21 +++--
1 file changed, 11 insertions
RISC-V specifies multiple sizes for addressable memory and Linux probes for
the machine's support at startup via the satp CSR register (done in
csr.c:validate_vm).
As per the specification, sv64 must support sv57, which in turn must
support sv48...etc. So we can restrict machine support by simply
The 'mmu-type' should reflect what the hardware is capable of so use the
new satp_mode field in RISCVCPUConfig to do that.
Signed-off-by: Alexandre Ghiti
---
hw/riscv/virt.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
Giving users an option to choose a particular codec will enable
them to make an appropriate decision based on their hardware and
use-case.
Cc: Gerd Hoffmann
Cc: Marc-André Lureau
Cc: Dongwon Kim
Signed-off-by: Vivek Kasireddy
---
qemu-options.hx | 5 +
ui/spice-core.c | 14 ++
On 20/01/2023 17.31, Peter Xu wrote:
Commit d9e474ea56 overlooked the case where the target psize is even larger
than the host psize. One example is Alpha has 8K page size and migration
will start to crash the source QEMU when running Alpha migration on x86.
Fix it by detecting that case and se
Currently, the max satp mode is set with the only constraint that it must be
implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
But we actually need to add another level of constraint: what the hw is
actually capable of, because currently, a linux booting on a sifive-u54
boots in sv57 mode wh
On 20/1/23 19:48, Fabiano Rosas wrote:
The migration tests are currently broken for an aarch64 host because
the tests pass no 'machine' and 'cpu' options on the QEMU command
line. Most other architectures define a default value in QEMU for
these options, but arm does not.
There was some discuss
On 20/1/23 13:22, Bernhard Beschow wrote:
Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow :
Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé"
:
On 9/1/23 18:23, Bernhard Beschow wrote:
This series consolidates the implementations of the PIIX3 and PIIX4 south
bridges an
One can extract the DeviceState pointer from the Object pointer, so pass
the Object for future commits to access other fields of Object.
No functional changes intended.
Reviewed-by: Alistair Francis
Reviewed-by: Frank Chang
Reviewed-by: Andrew Jones
Signed-off-by: Alexandre Ghiti
---
target/
On 23/1/23 09:39, Thomas Huth wrote:
From: Daniel P. Berrangé
Way back in QEMU 4.0, the -audiodev command line option was introduced
for configuring audio backends. This CLI option does not use QemuOpts
so it is not visible for introspection in 'query-command-line-options',
instead using the QA
On Mon, Jan 23, 2023 at 10:03:21AM +0100, Alexandre Ghiti wrote:
> This array is actually used as a boolean so swap its current char type
> to a boolean and at the same time, change the type of validate_vm to
> bool since it returns valid_vm_1_10_[32|64].
>
> Signed-off-by: Alexandre Ghiti
Sugge
On Fri, 20 Jan 2023 14:41:05 -0800
Dan Williams wrote:
> Gregory Price wrote:
> > On Fri, Jan 20, 2023 at 09:38:13AM -0800, Dan Williams wrote:
> > > As it stands currently that dax device and the cxl device are not
> > > related since a default dax-device is loaded just based on the presence
>
Hi Markus,
On 20/1/23 08:01, Markus Armbruster wrote:
PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined
in pnv.h. Many users of the header don't actually need them. One
instance is this inclusion loop: hw/ppc/pnv_homer.h includes
hw/ppc/pnv.h for typedef PnvChip, and vice ve
Philippe Mathieu-Daudé writes:
> Hi Markus,
>
> On 20/1/23 08:01, Markus Armbruster wrote:
>> PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined
>> in pnv.h. Many users of the header don't actually need them. One
>> instance is this inclusion loop: hw/ppc/pnv_homer.h includes
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Mon, Jan 23, 2023 at 10:03:23AM +0100, Alexandre Ghiti wrote:
> The 'mmu-type' should reflect what the hardware is capable of so use the
> new satp_mode field in RISCVCPUConfig to do that.
>
> Signed-off-by: Alexandre Ghiti
> ---
> hw/riscv/virt.c | 19 ++-
> 1 file changed, 1
Hi,
> Here is the flow of things from the Qemu side:
> - Call gl_scanout (to update the fd) and gl_draw_async just like
> in the local display case.
Ok.
> - Additionally, create an update with the cmd set to QXL_CMD_DRAW
> to trigger the creation of a new drawable (associated with the fd)
On 1/22/23 19:53, Alistair Francis wrote:
On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza
wrote:
Conor,
Thanks for the Icicle-kit walk-through! I'll not claim that I fully understood
it,
but I understood enough to handle the situation ATM.
Without this change, this is where the F
On 1/23/23 00:57, Alistair Francis wrote:
From: Alistair Francis
If the CSRs and CSR instructions are disabled because the Zicsr
extension isn't enabled then we want to make sure we don't run any CSR
instructions in the boot ROM.
This patches removes the CSR instructions from the reset-vec
On 06/01/2023 15.21, Anthony PERARD wrote:
From: Anthony PERARD
With "clang 6.0.0-1ubuntu2" on Ubuntu Bionic, the test with build
fine, but clang still suggest braces around the zero initializer in a
few places, where there is a subobject. Expand test to include a sub
struct which doesn't build
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote:
...
> +/* Sets the satp mode to the max supported */
> +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit)
> +{
nit: When passing in the cpu object pointer there's no need to also pass
is_32_bit, we can just use it from
On Mon, 23 Jan 2023 at 10:27, WANG Xuerui wrote:
>
> From: WANG Xuerui
>
> This patch adds a "loongarch64ow-linux-user" target and a
> corresponding "qemu-loongarch64ow" binary, for supporting user-mode
> emulation of old-world LoongArch applications in the wild.
>
> Although the old-world LoongA
On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable o
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> Part 1/4: Convert memory & machine options.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Dr. David Alan Gilbert
> ---
> tests/qtest/migration-test.c | 24 ++--
> 1 file changed, 14 insertions(+), 10 deletions(
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> Part 3/4: Convert accelerator options.
>
> Reviewed-by: Richard Henderson
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tests/qtest/migration-test.c | 15 +--
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/
On Fri, Jan 06, 2023 at 03:21:10PM +0100, Anthony PERARD via wrote:
> From: Anthony PERARD
>
> With "clang 6.0.0-1ubuntu2" on Ubuntu Bionic, the test with build
> fine, but clang still suggest braces around the zero initializer in a
> few places, where there is a subobject. Expand test to include
On 26.12.22 23:03, Vladimir Sementsov-Ogievskiy wrote:
Unfortunately Coverity doesn't follow the logic aroung "len" and "l"
variables in stacks finishing with flatview_{read,write}_continue() and
generate a lot of OVERRUN false-positives. When small buffer (2 or 4
bytes) is passed to mem read/wri
On Sat, Jan 21, 2023 at 10:47:31AM +0100, Volker Rümelin wrote:
> Use g_malloc0() as a direct replacement for audio_calloc().
>
> Since the type of the parameter n_bytes of the function g_malloc0()
> is unsigned, the type of the variables voice_size_out and
> voice_size_in has been changed to size
On Sat, Jan 21, 2023 at 10:47:32AM +0100, Volker Rümelin wrote:
> Replace audio_calloc() with the equivalent g_new0().
>
> With a n_structs argument >= 1, g_new0() never returns NULL.
> Also remove the unnecessary NULL checks.
>
> Signed-off-by: Volker Rümelin
> ---
> audio/audio_template.h | 2
On Mon, Jan 23, 2023 at 10:20:29AM +0100, Philippe Mathieu-Daudé wrote:
> On 23/1/23 09:39, Thomas Huth wrote:
> > From: Daniel P. Berrangé
> >
> > Way back in QEMU 4.0, the -audiodev command line option was introduced
> > for configuring audio backends. This CLI option does not use QemuOpts
> >
On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
>
> On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > Currently, the max satp mode is set with the only constraint that it must be
> > implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
> >
> > But we actually need to add
On 1/23/23 18:47, Peter Maydell wrote:
On Mon, 23 Jan 2023 at 10:27, WANG Xuerui wrote:
From: WANG Xuerui
This patch adds a "loongarch64ow-linux-user" target and a
corresponding "qemu-loongarch64ow" binary, for supporting user-mode
emulation of old-world LoongArch applications in the wild.
From: WANG Xuerui
This patch adds a "loongarch64ow-linux-user" target and a
corresponding "qemu-loongarch64ow" binary, for supporting user-mode
emulation of old-world LoongArch applications in the wild.
Although the old-world LoongArch is already being (slowly) phased out,
there are already a nu
On Mon, Jan 23, 2023 at 11:37 AM Philipp Tomsich
wrote:
>
> On Mon, 23 Jan 2023 at 02:29, Alistair Francis wrote:
> >
> > On Sat, Jan 21, 2023 at 12:36 PM Philipp Tomsich
> > wrote:
> > >
> > > The Zicond standard extension implements the same instruction
> > > semantics as XVentanaCondOps, alth
On Mon, Jan 23, 2023 at 8:19 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/22/23 19:53, Alistair Francis wrote:
> > On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza
> > wrote:
> >>
> >> Conor,
> >>
> >> Thanks for the Icicle-kit walk-through! I'll not claim that I fully
> >> understood i
On Mon, Jan 23, 2023 at 8:25 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 1/23/23 00:57, Alistair Francis wrote:
> > From: Alistair Francis
> >
> > If the CSRs and CSR instructions are disabled because the Zicsr
> > extension isn't enabled then we want to make sure we don't run any CSR
> > instru
On 1/23/23 00:57, Alistair Francis wrote:
From: Alistair Francis
If the CSRs and CSR instructions are disabled because the Zicsr
extension isn't enabled then we want to make sure we don't run any CSR
instructions in the boot ROM.
This patches removes the CSR instructions from the reset-vec
* Philippe Mathieu-Daudé (phi...@linaro.org) wrote:
> +David / Juan / Peter for migration and timers.
>
> On 20/1/23 13:01, Daniel Henrique Barboza wrote:
> > At this moment any migration with the RISC-V sifive_u machine
> > fails with the following error:
> >
> > qemu-system-riscv64: ../hw/sd/sd
On 23/1/23 11:07, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
Hi Markus,
On 20/1/23 08:01, Markus Armbruster wrote:
PnvChipClass, PnvChip, Pnv8Chip, Pnv9Chip, and Pnv10Chip are defined
in pnv.h. Many users of the header don't actually need them. One
instance is this inclusion l
On Sun, Jan 22, 2023 at 08:21:30PM -0800, Eric Biggers wrote:
> Hi Michael,
>
> On Tue, Jan 10, 2023 at 12:50:42PM -0500, Michael S. Tsirkin wrote:
> > On Tue, Jan 10, 2023 at 04:34:49PM +0100, Jason A. Donenfeld wrote:
> > > Hi Michael,
> > >
> > > Could you queue up this patch and mark it as a
Until now, testing using CXL has relied up always using two root ports
below a host bridge, to work around a current assumption in the Linux
kernel support that, in the single root port case, the implementation will
use the allowed passthrough decoder implementation choice. If that choice
is made a
The CXL r3.0 specification allows for there to be no HDM decoders on CXL
Host Bridges if they have only a single root port. Instead, all accesses
directed to the host bridge (as specified in CXL Fixed Memory Windows)
are assumed to be routed to the single root port.
Linux currently assumes this im
These two helpers enable host bridges to operate differently depending on
the number of downstream ports, in particular if there is only a single
port.
Useful for CXL where HDM address decoders are allowed to be implicit in
the host bridge if there is only a single root port.
Signed-off-by: Jonat
Reviewed-by: Konstantin Kostiuk
On Sun, Jan 22, 2023 at 5:33 PM Kfir Manor wrote:
> ---
> qga/commands-posix.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/qga/commands-posix.c b/qga/commands-posix.c
> index ebd33a643c..aab9d3bd50 100644
> --- a/qga/commands-po
Hi Kfir,
You missed adding the Signed-off-by line to the patch.
Please resend.
Best Regards,
Konstantin Kostiuk.
On Sun, Jan 22, 2023 at 5:33 PM Kfir Manor wrote:
> ---
> qga/commands-posix.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/qga/commands-posix.c b
On 23/1/23 12:11, Daniel P. Berrangé wrote:
On Mon, Jan 23, 2023 at 10:20:29AM +0100, Philippe Mathieu-Daudé wrote:
On 23/1/23 09:39, Thomas Huth wrote:
From: Daniel P. Berrangé
Way back in QEMU 4.0, the -audiodev command line option was introduced
for configuring audio backends. This CLI opt
On Mon, Jan 23, 2023 at 6:12 AM Michael S. Tsirkin wrote:
>
> On Sun, Jan 22, 2023 at 08:21:30PM -0800, Eric Biggers wrote:
> > Hi Michael,
> >
> > On Tue, Jan 10, 2023 at 12:50:42PM -0500, Michael S. Tsirkin wrote:
> > > On Tue, Jan 10, 2023 at 04:34:49PM +0100, Jason A. Donenfeld wrote:
> > > >
After recent header file inclusion rework the build fails when the blkio
module is enabled:
../block/blkio.c: In function ‘blkio_detach_aio_context’:
../block/blkio.c:321:24: error: implicit declaration of function
‘bdrv_get_aio_context’; did you mean ‘qemu_get_aio_context’?
[-Werror=implicit-fu
On Fri, 6 Jan 2023 at 19:45, Richard Henderson
wrote:
>
> Do not encode the pointer as a constant in the opcode stream.
> This pointer is specific to the cpu that first generated the
> translation, which runs into problems with both hot-pluggable
> cpus and user-only threads, as cpus are removed.
Signed-off-by: Kfir Manor
---
qga/commands-posix.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/qga/commands-posix.c b/qga/commands-posix.c
index ebd33a643c..aab9d3bd50 100644
--- a/qga/commands-posix.c
+++ b/qga/commands-posix.c
@@ -880,7 +880,9 @@ static bool build_g
On Fri, 6 Jan 2023 at 19:45, Richard Henderson
wrote:
>
> Here's a short-to-medium term alternative to moving all of the ARMCPU
> cp_regs hash table to the ARMCPUClass, so that we're no longer leaving
> dangling pointers to freed objects encoded in the compiled
> TranslationBlocks. (I still think
On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote:
> On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote:
> >
> > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> > > Currently, the max satp mode is set with the only constraint that it must
> > > be
> > > implement
Thomas Huth writes:
> On 20/01/2023 20.44, Fabiano Rosas wrote:
>> These leaks can be avoided:
>>
>> 759 bytes in 61 blocks are still reachable in loss record 56 of 60
>> at 0x4034744: malloc (in
>> /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
>> by 0x4A88518: g_malloc (in /
On 1/23/23 11:57 AM, David Hildenbrand wrote:
On 20.01.23 14:47, Daniil Tatianin wrote:
This series introduces new qemu_prealloc_mem_with_timeout() api,
which allows limiting the maximum amount of time to be spent on memory
preallocation. It also adds prealloc statistics collection that is
expos
Signed-off-by: Kfir Manor
---
qga/commands-posix.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/qga/commands-posix.c b/qga/commands-posix.c
index ebd33a643c..aab9d3bd50 100644
--- a/qga/commands-posix.c
+++ b/qga/commands-posix.c
@@ -880,7 +880,9 @@ static bool build_g
From: Richard Henderson
During the conversion, the test against get_phys_addr_lpae got inverted,
meaning that successful translations went to the 'failed' label.
Cc: qemu-sta...@nongnu.org
Fixes: f3639a64f60 ("target/arm: Use softmmu tlbs for page table walking")
Resolves: https://gitlab.com/qem
mu-arm.git
tags/pull-target-arm-20230123
for you to fetch changes up to 3b07a936d3bfe97b07ddffcfbb532985a88033dd:
target/arm: Look up ARMCPRegInfo at runtime (2023-01-23 13:32:38 +)
target-arm queue:
* Widen cnthctl_el2 t
On 1/17/23 11:53, Eugenio Pérez wrote:
VHOST_BACKEND_F_IOTLB_ASID is the feature bit, not the bitmask. Since
the device under test also provided VHOST_BACKEND_F_IOTLB_MSG_V2 and
VHOST_BACKEND_F_IOTLB_BATCH, this went unnoticed.
Fixes: c1a1008685 ("vdpa: always start CVQ in SVQ mode if possible")
From: Richard Henderson
Move arm_reset_sve_state() calls to aarch64_set_svcr().
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230112102436.1913-5-phi...@linaro.org
Message-Id: <20230112004322.161330-1-richard.hender...@linaro.o
From: David Reiss
BASEPRI, FAULTMASK, and their _NS equivalents only exist on devices with
the Main Extension. However, the MRS instruction did not check this,
and the MSR instruction handled it inconsistently (warning BASEPRI, but
silently ignoring writes to BASEPRI_NS). Unify this behavior an
From: Richard Henderson
Unify the two helper_set_pstate_{sm,za} in this function.
Do not call helper_* functions from svcr_write.
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230112102436.1913-8-phi...@linaro.org
Message-Id: <
From: Richard Henderson
Do not encode the pointer as a constant in the opcode stream.
This pointer is specific to the cpu that first generated the
translation, which runs into problems with both hot-pluggable
cpus and user-only threads, as cpus are removed. It's also a
potential correctness issue
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230112102436.1913-7-phi...@linaro.org
Message-Id: <20230112004322.161330-1-richard.hender...@linaro.org>
[PMD: Split patch in multiple tiny steps]
Signed-off-
From: Philippe Mathieu-Daudé
ARM_SBCON_I2C() macro and ArmSbconI2CState typedef are
already declared via the QOM DECLARE_INSTANCE_CHECKER()
macro in "hw/i2c/arm_sbcon_i2c.h". Drop the VERSATILE_I2C
declarations from versatile_i2c.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Hen
From: Philippe Mathieu-Daudé
Define TYPE_GPIO_I2C in the public "hw/i2c/bitbang_i2c.h"
header and use it in hw/arm/musicpal.c.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Message-id: 20230111085016.44551-2-phi...@linaro.org
Signed-off-by: Peter
From: Philippe Mathieu-Daudé
In order to rename TYPE_VERSATILE_I2C as TYPE_ARM_SBCON_I2C
(the formal ARM naming), start renaming its state.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230110082508.24038-3-phi...@linaro.org
Signed-off-by: Peter Maydell
--
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230110082508.24038-2-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/i2c/versatile_i2c.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/i2c/versati
From: Evgeny Iakovlev
Qemu doesn't implement Debug Communication Channel, as well as the rest
of external debug interface. However, Microsoft Hyper-V in tries to
access some of those registers during an EL2 context switch.
Since there is no architectural way to not advertise support for external
From: Richard Henderson
Move the ri == NULL case to the top of the function and return.
This allows the else to be removed and the code unindented.
Signed-off-by: Richard Henderson
Reviewed-by: Alex Bennée
Message-id: 20230106194451.1213153-2-richard.hender...@linaro.org
Reviewed-by: Peter May
On Mon, Jan 23, 2023 at 04:30:03PM +0300, Daniil Tatianin wrote:
> On 1/23/23 11:57 AM, David Hildenbrand wrote:
> > On 20.01.23 14:47, Daniil Tatianin wrote:
> > > This series introduces new qemu_prealloc_mem_with_timeout() api,
> > > which allows limiting the maximum amount of time to be spent on
From: Philippe Mathieu-Daudé
This device model started with the Versatile board, named
TYPE_VERSATILE_I2C, then ended up renamed TYPE_ARM_SBCON_I2C
as per the official "ARM SBCon two-wire serial bus interface"
description from:
https://developer.arm.com/documentation/dui0440/b/programmer-s-refere
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Message-id: 20230111085016.44551-3-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/i2c/bitbang_i2c.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
d
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230112102436.1913-4-phi...@linaro.org
Message-Id: <20230112004322.161330-1-richard.hender...@linaro.org>
[PMD: Split patch in multiple tiny steps]
Signed-off-
From: Philippe Mathieu-Daudé
Convert the remaining DPRINTF debug macro uses to tracepoints.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Message-id: 20230111085016.44551-6-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/i2c/bitbang_i2c.c
In v7m_exception_taken(), for v8M we set the EXC_RETURN.ES bit if
either the exception targets Secure or if the CPU doesn't implement
the Security Extension. This is incorrect: the v8M Arm ARM specifies
that the ES bit should be RES0 if the Security Extension is not
implemented, and the pseudocode
Hi Connie,
On 1/11/23 17:13, Cornelia Huck wrote:
> Introduce a new cpu feature flag to control MTE support. To preserve
> backwards compatibility for tcg, MTE will continue to be enabled as
> long as tag memory has been provided.
>
> If MTE has been enabled, we need to disable migration, as we do
On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote:
> Currently, the max satp mode is set with the only constraint that it must be
> implemented in qemu, i.e. set in valid_vm_1_10_[32|64].
>
> But we actually need to add another level of constraint: what the hw is
> actually capable o
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Fabiano Rosas
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230112102436.1913-3-phi...@linaro.org
Message-Id: <20230112004322.161330-1-richard.hender...@linaro.org>
[PMD: Split patch in multiple tiny steps]
Signed-off-
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Acked-by: Corey Minyard
Message-id: 20230111085016.44551-4-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/i2c/bitbang_i2c.c | 23 +++
1 file changed, 15 insertions(+),
1 - 100 of 312 matches
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