Re: [PATCH 0/8] hw/cxl: CXL emulation cleanups and minor fixes for upstream

On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote: > > Just to check, are these different from the on stack problem you reported > previously? Doesn't look like the fix for that has made it upstream yet. > > What kernel are you running? > > The prior issue I saw was related to

[PATCH 9/9] audio: remove support for QEMU_AUDIO_ env variables

All user created devices and the builtin pcspk can be given a audiodev property. A few devices using audiodevs though cannot be configured directly as they are built-in devices created programmatically by the machine type. To enable those to continue to be used we leave in the logic that picks the

[PULL 28/46] mips: Always include nanomips disassembler

From: Paolo Bonzini Since the nanomips disassembler is not C++ code anymore, it need not depend on link_language == cpp. Always include it and remove the CONFIG_NANOMIPS_DIS symbol. Cc: Philippe Mathieu-Daudé Signed-off-by: Paolo Bonzini Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Danie

[PULL 23/46] hw/mips/malta: Merge common BL code as bl_setup_gt64120_jump_kernel()

Merge common code shared between write_bootloader() and write_bootloader_nanomips() into bl_setup_gt64120_jump_kernel(). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20221211204533.85359-12-phi...@linaro.org> --- hw/mips/malta.c | 155 +--

[PULL 09/46] hw/mips/malta: Explicit GT64120 endianness upon device creation

Propagate the controller endianess from the machine, setting the "cpu-little-endian" property. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221209151533.69516-6-phi...@linaro.org> Reviewed-by: Richard Henderson --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

[PATCH 1/7] hw/pci/aer: Implement PCI_ERR_UNCOR_MASK register

This register in AER should be both writeable and should have a default value with a couple of the errors masked including the Uncorrectable Internal Error used by CXL for it's error reporting. Signed-off-by: Jonathan Cameron --- hw/pci/pcie_aer.c | 4 include/hw/pci/pcie_regs.h |

[PULL 07/46] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterFields API

Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221220113436.14299-4-phi...@linaro.org> Reviewed-by: Richard Henderson --- hw/mips/gt64xxx_pci.c | 38 +++--- 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64x

Re: [RFC PATCH v3 20/28] target/arm: Set cortex-a57 as default cpu for KVM-only build

Claudio Fontana writes: > On 1/13/23 15:04, Fabiano Rosas wrote: >> The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the >> cortex-a57 as default cpu for KVM. >> >> Signed-off-by: Fabiano Rosas > > Our recommendation currently for KVM on ARM is to always use CPU="host", as > nam

Re: [PATCH v6 11/13] vfio/migration: Remove VFIO migration protocol v1

On 1/12/23 09:50, Avihai Horon wrote: Now that v2 protocol implementation has been added, remove the deprecated v1 implementation. Signed-off-by: Avihai Horon Reviewed-by: Cédric Le Goater Thanks, C. --- include/hw/vfio/vfio-common.h | 5 - hw/vfio/common.c | 19 +-

[PATCH 5/7] hw/mem/cxl-type3: Add AER extended capability

This enables AER error injection to function as expected. It is intended as a building block in enabling CXL RAS error injection in the following patches. Signed-off-by: Jonathan Cameron --- hw/mem/cxl_type3.c | 13 + 1 file changed, 13 insertions(+) diff --git a/hw/mem/cxl_type3.c

[RFC PATCH v3 05/28] target/arm: Move cpregs code out of cpu.h

Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have a cpregs.h header which is more suitable for this code. Code moved verbatim. Signed-off-by: Fabiano Rosas --- target/arm/cpregs.h | 98 + target/arm/cpu.h| 91 -

[PATCH 8/9] audio: audio state is now mandatory for capture

Both callers of AUD_add_capture will now ensure that the audio state is non-NULL. Signed-off-by: Daniel P. Berrangé --- audio/audio.c | 7 --- 1 file changed, 7 deletions(-) diff --git a/audio/audio.c b/audio/audio.c index 00128c2ad7..64b75cdf94 100644 --- a/audio/audio.c +++ b/audio/audio.

[PULL 40/46] hw/pci-host/bonito: Convert to 3-phase reset

From: Philippe Mathieu-Daudé Convert the TYPE_PCI_BONITO class to use 3-phase reset. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20230105130710.49264-2-phi...@linaro.org> --- hw/pci-host/bonito.c | 9 - 1 file changed, 4 insertions(+), 5 deletions

Re: [PATCH v6 09/13] vfio/migration: Implement VFIO migration protocol v2

On 1/12/23 09:50, Avihai Horon wrote: Implement the basic mandatory part of VFIO migration protocol v2. This includes all functionality that is necessary to support VFIO_MIGRATION_STOP_COPY part of the v2 protocol. The two protocols, v1 and v2, will co-exist and in the following patches v1 proto

[PULL 25/46] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader

Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board.

[PATCH 3/9] audio: remove unused 'name' in QEMUSoundCard struct

Signed-off-by: Daniel P. Berrangé --- audio/audio.c | 2 -- audio/audio.h | 1 - 2 files changed, 3 deletions(-) diff --git a/audio/audio.c b/audio/audio.c index f397072a1f..94a16c2dda 100644 --- a/audio/audio.c +++ b/audio/audio.c @@ -1833,7 +1833,6 @@ void AUD_register_card (const char *name,

Re: [PATCH v6 10/13] vfio/migration: Optimize vfio_save_pending()

On 1/12/23 09:50, Avihai Horon wrote: During pre-copy phase of migration vfio_save_pending() is called repeatedly and queries the VFIO device for its pending data size. As long as pending RAM size is over the threshold, migration can't converge and be completed. Therefore, during this time there

[PATCH 2/9] audio: remove special audio_calloc function

The audio_calloc function does various checks on the size and nmembers parameters to detect various error conditions. There are only 5 callers * alsa_poll_helper: the pollfd count is small and bounded, * audio_pcm_create_voice_pair_: allocating a single fixed size struct * audio_pcm_sw_alloc

[PATCH 0/7] hw/cxl: RAS error emulation and injection

CXL error reporting is complex. This series only covers the protocol related errors reported via PCIE AER - Ira Weiny has posted support for Event log based injection and I will post an update of Poison list injection shortly. My proposal is to upstream this one first, followed by Ira's Event Log s

[PULL 19/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (2/5)

Part 2/5: Convert PCI0 MEM0 BAR setup Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20221211204533.85359-8-phi...@linaro.org> --- hw/mips/malta.c | 35 ++- 1 file changed, 6 insertions(+), 29 deletions(-) diff --git a/hw/mips/

[PATCH 4/9] audio: remove QEMUSoundCard linked list

No code ever iterates over the list Signed-off-by: Daniel P. Berrangé --- audio/audio.c | 5 - audio/audio.h | 1 - audio/audio_int.h | 1 - 3 files changed, 7 deletions(-) diff --git a/audio/audio.c b/audio/audio.c index 94a16c2dda..217095306f 100644 --- a/audio/audio.c +++ b/audio

Re: Qemu interrupt-remap fault support

On Fri, 13 Jan 2023 09:08:38 + David Woodhouse wrote: > I'm looking at interrupt remapping (because I need to hook into the > translation somehow to add PIRQ support for Xen which translates guest > MSIs directly to KVM_IRQ_ROUTING_XEN_EVTCHN). > > Am I right in understanding that it doesn't

Re: [PATCH v14 01/11] s390x/cpu topology: adding s390 specificities to CPU topology

On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote: > S390 adds two new SMP levels, drawers and books to the CPU > topology. > The S390 CPU have specific toplogy features like dedication > and polarity to give to the guest indications on the host > vCPUs scheduling and help the guest take the be

[PATCH 6/7] hw/pci/aer: Make PCIE AER error injection facility available for other emulation to use.

This infrastructure will be reused for CXL RAS error injection in patches that follow. Signed-off-by: Jonathan Cameron --- hw/pci/pci-internal.h | 1 - include/hw/pci/pcie_aer.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci/pci-internal.h b/hw/pci/pci-internal.h

[PATCH 2/7] hw/pci/aer: Add missing routing for AER errors

PCIe r6.0 Figure 6-3 "Pseudo Logic Diagram for Selected Error Message Control and Status Bits" includes a right hand branch under "All PCI Express devices" that allows for messages to be generated or sent onwards without SERR# being set as long as the appropriate per error class bit in the PCIe Dev

Re: [PATCH v6 12/13] vfio: Alphabetize migration section of VFIO trace-events file

On 1/12/23 09:50, Avihai Horon wrote: Sort the migration section of VFIO trace events file alphabetically and move two misplaced traces to common.c section. Signed-off-by: Avihai Horon Reviewed-by: Cédric Le Goater Thanks, C. --- hw/vfio/trace-events | 22 +++--- 1 f

[PULL 12/46] tests/avocado: Add tests booting YAMON ROM on MIPS Malta machines

Add quick tests booting YAMON: $ avocado --show=app,console run -t machine:malta tests/avocado/machine_mips_malta.py (1/2) tests/avocado/machine_mips_malta.py:MaltaMachine.test_mipsel_malta_yamon: console: YAMON ROM Monitor, Revision 02.22. console: Copyright (c) 1999-2007 MIPS Technolo

Re: Qemu interrupt-remap fault support

On Fri, 2023-01-13 at 09:51 -0700, Alex Williamson wrote: > On Fri, 13 Jan 2023 09:08:38 + > David Woodhouse wrote: > > > I'm looking at interrupt remapping (because I need to hook into the > > translation somehow to add PIRQ support for Xen which translates guest > > MSIs directly to KVM_IRQ

Re: [PATCH 0/8] hw/cxl: CXL emulation cleanups and minor fixes for upstream

On Fri, Jan 13, 2023 at 02:45:11PM +, Jonathan Cameron wrote: > On Fri, 13 Jan 2023 14:40:26 + Jonathan Cameron > wrote: > > On Fri, 13 Jan 2023 09:19:59 -0500 Gregory Price > > wrote: > > > On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote: > > > > Just to check, are t

Re: [PATCH v6 13/13] docs/devel: Align VFIO migration docs to v2 protocol

On 1/12/23 09:50, Avihai Horon wrote: Now that VFIO migration protocol v2 has been implemented and v1 protocol has been removed, update the documentation according to v2 protocol. Signed-off-by: Avihai Horon Reviewed-by: Cédric Le Goater Thanks, C. --- docs/devel/vfio-migration.rst

[PATCH 3/7] hw/pci-bridge/cxl_root_port: Wire up AER

We are missing necessary config write handling for AER emulation in the CXL root port. Add it based on pcie_root_port.c Signed-off-by: Jonathan Cameron --- hw/pci-bridge/cxl_root_port.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_

[PATCH v7 2/3] hw/riscv/boot.c: make riscv_load_initrd() static

The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 80 - include/hw/riscv/boot.h | 1

[PULL 02/46] hw/mips/malta: Trace FPGA LEDs/ASCII display updates

The FPGA LEDs/ASCII display is mostly used by the bootloader to show very low-level debug info. QEMU connects its output to a character device backend, which is not very practical to correlate with ASM instruction executed, interrupts or MMIO accesses. Also, the display discard the previous states.

[PULL 39/46] softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818

From: Thomas Huth The 'slew' lost tick policy is only available on systems with a mc146818 RTC. On other systems, "-rtc driftfix=slew" is currently silently ignored. Let's emit at least a warning in this case to make the users aware that there is something wrong in their command line settings. R

Re: completion timeouts with pin-based interrupts in QEMU hw/nvme

On Fri, Jan 13, 2023 at 12:32:29PM +, Peter Maydell wrote: > On Fri, 13 Jan 2023 at 08:55, Klaus Jensen wrote: > > > > +CC qemu pci maintainers > > > > Michael, Marcel, > > > > Do you have any comments on this thread? As you can see one solution is > > to simply deassert prior to asserting, th

[PATCH v7 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs

Hi, In this version I followed Bin Meng's suggestion and reverted patch 1 back from what it was in the v5, acks included, and added a new patch (3) to fix the problem detected with the Xvisor use case. I believe this reflects that there is nothing particularly wrong with what we did in the v5 patc

[PULL 21/46] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (4/5)

Part 4/5: Convert GT64120 ISD base address setup Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20221211204533.85359-10-phi...@linaro.org> --- hw/mips/malta.c | 40 +++- 1 file changed, 7 insertions(+), 33 deletions(-) diff

Re: [RFC] cxl-host: Fix committed check for passthrough decoder

On Fri, Jan 13, 2023 at 09:47:25AM +, Jonathan Cameron wrote: > On Fri, 13 Jan 2023 00:27:55 + > Fan Ni wrote: > > > For passthrough decoder (a decoder hosted by a cxl component with only > > one downstream port), its cache_mem_registers field COMMITTED > > (see spec 2.0 8.2.5.12 - CXL H

[PATCH v7 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()

The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren'

[PULL 45/46] target/mips: Restrict 'qapi-commands-machine.h' to system emulation

Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Extract the QMP functions from cpu.c (which is always compiled) to the new 'sysemu/mips-qmp-cmds.c' unit (which is only comp

[PULL 38/46] hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent

From: Thomas Huth The only reason for this code being target dependent was the IRQ-counting related code in rtc_policy_slew_deliver_irq(). Since these functions have been moved into a new, separate file (kvm_irqcount.c) which is now always compiled and linked if necessary, we can get rid of the #

Re: [PATCH 4/4] tests/tcg/multiarch: add vma-pthread.c

Peter Maydell writes: > On Sat, 24 Dec 2022 at 15:19, Richard Henderson > wrote: >> >> From: Ilya Leoshkevich >> >> Add a test that locklessly changes and exercises page protection bits >> from various threads. This helps catch race conditions in the VMA >> handling. >> >> Signed-off-by: Ilya

[PULL 32/46] hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific

From: Bernhard Beschow pci_map_irq_fn's in general seem to be board-specific, and PIIX4's pci_slot_get_pirq() in particular seems very Malta-specific. So move the latter to malta.c to 1/ keep the board logic in one place and 2/ avoid PIIX4 to make assumptions about its board. Signed-off-by: Bern

[PATCH 0/9] audio: remove deprecated QEMU_AUDIO env support

This removes much of the deprecated audio code, most notably the QEMU_AUDIO env variables. The VNC server will also stop accepting client requests for audio streaming unless an audiodev is set. I tried to make the use of 'audiodev' mandatory for devices but that turned out to not be practical. Our

Re: [Capstone] Feedback request for new architecture updater

Hi! > Do you have any plans to work on Sparc and Mips any time soon? The plan is to update ARM and PPC first, because they seemed to be the most complicated ones. Afterwards other architectures (Mips and Sparc as well). I can't say when exactly ARM will be ready (I hope at latest end of Febru

Re: [PATCH v6 00/33] Consolidate PIIX south bridges

Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" : >Hi Bernhard, > >On 9/1/23 18:23, Bernhard Beschow wrote: >> This series consolidates the implementations of the PIIX3 and PIIX4 south >> bridges and is an extended version of [1]. The motivation is to share as much >> code as p

[PATCH 5/9] audio: remove empty AUD_remove_card method

Since the linked list of QEMUSoundCard structs was removed, AUD_remove_card does nothing useful. Signed-off-by: Daniel P. Berrangé --- audio/audio.c| 4 audio/audio.h| 1 - hw/audio/ac97.c | 1 - hw/audio/adlib.c | 1 - hw/audio/es1370.c| 1 - hw/audio/gus.c

[PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()

Recent hw/risc/boot.c changes caused a regression in an use case with the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' stopped working. The reason seems to be that Xvisor is using 64 bit to encode the 32 bit addresses from the guest, and load_elf_ram_sym() is sign-extending the res

[PATCH 7/9] ui/vnc: don't accept VNC_ENCODING_AUDIO without audiodev

If we have no audio state configured, then we don't want to advertize the VNC_ENCODING_AUDIO feature. If a client attempts to use it despite being disabled, we should also reject it. Signed-off-by: Daniel P. Berrangé --- docs/about/deprecated.rst | 6 -- docs/about/removed-features.rs

Re: [PATCH v6 04/33] hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs()

Am 13. Januar 2023 10:13:29 UTC schrieb "Philippe Mathieu-Daudé" : >On 9/1/23 18:23, Bernhard Beschow wrote: >> pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and >> pci_map_irq_fn to a PCI bus. This coupling gets in the way when the >> pci_map_irq_fn is board-specific while t

Re: [PATCH RESEND v2 0/5] target: Restrict 'qapi-commands-machine.h' to system emulation

On 13/1/23 15:53, Philippe Mathieu-Daudé wrote: On 13/1/23 15:42, Philippe Mathieu-Daudé wrote: On 13/1/23 14:57, Markus Armbruster wrote: Philippe Mathieu-Daudé writes: [resend fixing my last name typography...] All series reviewed, can patches be picked by corresponding maintainers? The

Re: Exposing Mac Host Internal Microphone to Guests

On 30/11/2022 17.15, DUO Labs wrote: Is there any documentation on creating a new microphone/camera that can be exposed to the guest? I'm thinking of writing one to support MacOS hosts, but I don't know where to start. I see that there's something called QOM, but I'm not sure how to use it. T

[PATCH 6/9] docs: split the deprecation warning for soundcards vs VNC

Both soundcards and VNC will require the audiodev= property but lets split the deprecation message since these are distinct functional areas. Signed-off-by: Daniel P. Berrangé --- docs/about/deprecated.rst | 14 +- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/docs/ab

[PATCH v2 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props()

There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board som

Re: [PATCH 1/4] qcow2: Fix theoretical corruption in store_bitmap() error path

On 13/1/23 11:45, Kevin Wolf wrote: Am 13.01.2023 um 08:30 hat Philippe Mathieu-Daudé geschrieben: On 12/1/23 20:14, Kevin Wolf wrote: In order to write the bitmap table to the image file, it is converted to big endian. If the write fails, it is passed to clear_bitmap_table() to free all of the

[PATCH v2 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next

Hi, In this version I fixed the commit message typos pointed by Bin. I've also added some notes about the code repetition the fix is introducing in the cpu_init() functions. The patches are based on riscv-to-apply.next at c1e76da3e668 ("target/riscv/cpu.c: Fix elen check"). Changes from v1: - pa

[PATCH v2 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize()

All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_valida

Re: virtio-iommu issue with VFIO device downstream to a PCIe-to-PCI bridge: VFIO devices are not assigned any iommu group

On Fri, 13 Jan 2023 12:39:18 + Jean-Philippe Brucker wrote: > Hi, > > On Mon, Jan 09, 2023 at 10:11:19PM +0100, Eric Auger wrote: > > > Jean, do you have any idea about how to fix that? Do you think we have a > > > trouble in the acpi/viot setup or virtio-iommu probe sequence. It looks > > >

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Re: [PULL 00/38] target-arm queue

Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git > tags/pull-target-arm-20230113 > > for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31: > > target/arm: allow writes to SCR_EL3.HXEn bit wh

Re: [PULL 00/46] MIPS patches for 2023-01-13

ilable in the Git repository at: > > https://github.com/philmd/qemu.git tags/mips-20230113 > > for you to fetch changes up to 4828656f65324249273ad2f2db80844ba90eeb9b: > > scripts/git.orderfile: Display MAINTA

Re: [PATCH v14 02/11] s390x/cpu topology: add topology entries on CPU hotplug

On Thu, 2023-01-05 at 15:53 +0100, Pierre Morel wrote: > The topology information are attributes of the CPU and are > specified during the CPU device creation. > > On hot plug, we gather the topology information on the core, > creates a list of topology entries, each entry contains a single > core

Re: [PATCH-for-8.0] softmmu: Extract watchpoint API from physmem.c

On 12/9/22 06:12, Philippe Mathieu-Daudé wrote: The watchpoint API is specific to TCG system emulation. Move it to a new compile unit. The inlined stubs are used for user-mode and non-TCG accelerators. Signed-off-by: Philippe Mathieu-Daudé --- MAINTAINERS | 1 + include/hw/core/c

Re: [PATCH 0/7] Trivial: Mark some more files as target-independant

On 1/12/23 05:49, Thomas Huth wrote: Philippe Mathieu-Daudé (4): hw/display: Move omap_lcdc.c out of target-specific source set hw/intc: Move some files out of the target-specific source set hw/tpm: Move tpm_ppi.c out of target-specific source set hw/arm: Move various units to softmmu

Re: [RFC v4 2/3] memory: add depth assert in address_space_to_flatview

Hi, Peter, On 2023/1/12 下午11:13, Peter Xu wrote: We wanted to capture outliers when you apply the follow up patch to vm load procedure. That will make depth>0 for the whole process of vm load during migration, and we wanted to make sure it's safe, hence this patch, right? In my perspective, b

[PATCH 3/4] hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()

Missed during automatic conversion from commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible"). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/or-irq.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/hw/or-irq.h b/include/hw/or-irq.h index f2f0a273

[PATCH 2/4] hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE()

QOM *DECLARE* macros expect a typedef as first argument, not a structure. Replace 'struct IRQState' by 'IRQState' to avoid when modifying the macros: ../hw/core/irq.c:29:1: error: declaration of anonymous struct must be a definition DECLARE_INSTANCE_CHECKER(struct IRQState, IRQ, ^ Use OBJE

[PATCH 0/4] hw: QOM housekeeping around IOTHREAD / IRQ types

- remove unused code - use recent QOM macros - use CamelCase typedef Philippe Mathieu-Daudé (4): iothread: Remove unused IOThreadClass / IOTHREAD_CLASS hw/irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw/or-irq: Declare QOM macros using OBJECT_DECLARE_SIMPLE_TYPE() hw: Replace

[PATCH 4/4] hw: Replace qemu_or_irq typedef by OrIRQState

OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git

[PATCH 1/4] iothread: Remove unused IOThreadClass / IOTHREAD_CLASS

Since commit be8d853766 ("iothread: add I/O thread object") we never used IOThreadClass / IOTHREAD_CLASS() / IOTHREAD_GET_CLASS(), remove these definitions. Signed-off-by: Philippe Mathieu-Daudé --- iothread.c | 4 1 file changed, 4 deletions(-) diff --git a/iothread.c b/iothread.c index 3

Re: [PULL 00/46] MIPS patches for 2023-01-13

) are available in the Git repository at: https://github.com/philmd/qemu.git tags/mips-20230113 for you to fetch changes up to 4828656f65324249273ad2f2db80844ba90eeb9b: scripts/git.orderfile: Display MAINTAINERS changes first (2023-01-13 16:2

[PATCH v2 02/14] block: Convert bdrv_io_plug() to co_wrapper

From: Emanuele Giuseppe Esposito BlockDriver->bdrv_io_plug is categorized as IO callback, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since the callback traverses the block nodes graph, which however is only possible in a coroutine. The only caller of this f

[PATCH v2 07/14] block-backend: use bdrv_getlength instead of blk_getlength

From: Emanuele Giuseppe Esposito The only difference is that blk_ checks if the block is available, but this check is already performed above in blk_check_byte_request(). This is in preparation for the graph rdlock, which will be taken by both the callers of blk_check_byte_request() and blk_getl

[PATCH v2 01/14] block-coroutine-wrapper: support void functions

From: Emanuele Giuseppe Esposito Just omit the various 'return' when the return type is void. Signed-off-by: Emanuele Giuseppe Esposito Signed-off-by: Kevin Wolf --- scripts/block-coroutine-wrapper.py | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/sc

[PATCH v2 00/14] block: Move more functions to coroutines

This series converts some IO_CODE() functions to coroutine_fn because they access the graph and will need to hold the graph lock in the future. IO_CODE() functions can be called from iothreads, so taking the graph lock requires the function to run in coroutine context. Pretty much all of the chang

[PATCH v2 12/14] block: Convert bdrv_lock_medium() to co_wrapper

From: Emanuele Giuseppe Esposito bdrv_lock_medium() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. The only caller of this function is bl

[PATCH v2 06/14] block: Convert bdrv_refresh_total_sectors() to co_wrapper_mixed

From: Emanuele Giuseppe Esposito BlockDriver->bdrv_getlength is categorized as IO callback, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since the callback traverses the block nodes graph, which however is only possible in a coroutine. Therefore turn it into

[PATCH v2 14/14] block: Rename bdrv_load/save_vmstate() to bdrv_co_load/save_vmstate()

From: Emanuele Giuseppe Esposito Since these functions always run in coroutine context, adjust their name to include "_co_", just like all other BlockDriver callbacks. No functional change intended. Signed-off-by: Emanuele Giuseppe Esposito Signed-off-by: Kevin Wolf --- include/block/block_i

[PATCH v2 08/14] block: use bdrv_co_refresh_total_sectors when possible

From: Emanuele Giuseppe Esposito In some places we are sure we are always running in a coroutine, therefore it's useless to call the generated_co_wrapper, instead call directly the _co_ function. Signed-off-by: Emanuele Giuseppe Esposito Signed-off-by: Kevin Wolf --- block/block-backend.c | 6

[PATCH v2 03/14] block: Convert bdrv_io_unplug() to co_wrapper

From: Emanuele Giuseppe Esposito BlockDriver->bdrv_io_unplug is categorized as IO callback, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since the callback traverses the block nodes graph, which however is only possible in a coroutine. The only caller of this

[PATCH v2 09/14] block: Convert bdrv_get_allocated_file_size() to co_wrapper

From: Emanuele Giuseppe Esposito bdrv_get_allocated_file_size() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. Therefore turn it into a c

[PATCH v2 04/14] block: Convert bdrv_is_inserted() to co_wrapper

From: Emanuele Giuseppe Esposito bdrv_is_inserted() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. Therefore turn it into a co_wrapper to

[PATCH v2 05/14] block: Rename refresh_total_sectors to bdrv_refresh_total_sectors

From: Emanuele Giuseppe Esposito The name is not good, not the least because we are going to convert this to a generated co_wrapper, which adds a _co infix after the first part of the name. No functional change intended. Signed-off-by: Emanuele Giuseppe Esposito Signed-off-by: Kevin Wolf ---

[PATCH v2 13/14] block: Convert bdrv_debug_event() to co_wrapper_mixed

From: Emanuele Giuseppe Esposito bdrv_debug_event() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. Therefore turn it into a co_wrapper_mi

[PATCH v2 10/14] block: Convert bdrv_get_info() to co_wrapper_mixed

From: Emanuele Giuseppe Esposito bdrv_get_info() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. Therefore turn it into a co_wrapper to mo

[PATCH v2 11/14] block: Convert bdrv_eject() to co_wrapper

From: Emanuele Giuseppe Esposito bdrv_eject() is categorized as an I/O function, and it currently doesn't run in a coroutine. We should let it take a graph rdlock since it traverses the block nodes graph, which however is only possible in a coroutine. The only caller of this function is blk_ejec

Re: [PATCH v8] xen/pt: reserve PCI slot 2 for Intel igd-passthru

On 1/13/23 4:33 AM, Igor Mammedov wrote: > On Thu, 12 Jan 2023 23:14:26 -0500 > Chuck Zmudzinski wrote: > >> On 1/12/23 6:03 PM, Michael S. Tsirkin wrote: >> > On Thu, Jan 12, 2023 at 10:55:25PM +, Bernhard Beschow wrote: >> >> I think the change Michael suggests is very minimalistic: Move

Re: [PATCH 0/4] Improve the introductory documentation

On 1/13/23 05:39, Alex Bennée wrote: Alex Bennée (4): docs: add hotlinks to about preface text docs: add a new section to outline emulation support semihosting: add semihosting section to the docs docs: add an introduction to the system docs Looks ok. Acked-by: Richard Henderson

RE: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Friday, January 13, 2023 7:39 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; richard.hender...@linaro.org > Subject: [PATCH 1/2] Hexagon (iclass): update J4_hintjumpr slot constraints > > The Hexagon

RE: [PATCH 2/2] Hexagon (decode): look for pkts with multiple insns at the same slot

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Friday, January 13, 2023 7:39 AM > To: qemu-devel@nongnu.org > Cc: Taylor Simpson ; Brian Cain > ; richard.hender...@linaro.org > Subject: [PATCH 2/2] Hexagon (decode): look for pkts with multiple insns at > the same slot >

Re: [RFC PATCH v3 05/28] target/arm: Move cpregs code out of cpu.h

On 1/13/23 06:03, Fabiano Rosas wrote: Since commit cf7c6d1004 ("target/arm: Split out cpregs.h") we now have a cpregs.h header which is more suitable for this code. Code moved verbatim. Signed-off-by: Fabiano Rosas --- target/arm/cpregs.h | 98 +

Re: [RFC PATCH v3 08/28] target/arm: Wrap breakpoint/watchpoint updates with tcg_enabled

On 1/13/23 06:03, Fabiano Rosas wrote: This is in preparation for moving debug_helper.c into a TCG-specific directory. Signed-off-by: Fabiano Rosas --- target/arm/cpu.c | 6 -- target/arm/machine.c | 7 +-- 2 files changed, 9 insertions(+), 4 deletions(-) Reviewed-by: Richard H

Re: [PATCH v10 1/9] mm: Introduce memfd_restricted system call to create restricted user memory

On Fri, Dec 02, 2022, Chao Peng wrote: > The system call is currently wired up for x86 arch. Building on other architectures (except for arm64 for some reason) yields: CALL/.../scripts/checksyscalls.sh :1565:2: warning: #warning syscall memfd_restricted not implemented [-Wcpp] Do we car

Re: [RFC PATCH v3 12/28] target/arm: Wrap arm_rebuild_hflags calls with tcg_enabled

On 1/13/23 06:04, Fabiano Rosas wrote: This is in preparation to moving the hflags code into its own file under the tcg/ directory. Signed-off-by: Fabiano Rosas --- I extracted these into a separate patch so we can discuss. If I move the tcg_enabled check to a header that would add overhead for

Re: [RFC PATCH v3 17/28] target/arm: Move cortex sysregs into cpregs.c

On 1/13/23 06:04, Fabiano Rosas wrote: The file cpu_tcg.c is about to be moved into the tcg/ directory, so move the register definitions into cpregs.c along with all the others. Signed-off-by: Fabiano Rosas --- target/arm/cpregs.c| 59 ++ target/arm

Re: [RFC PATCH v3 18/28] target/arm: Move common cpu code into cpu.c

On 1/13/23 06:04, Fabiano Rosas wrote: The cpu_tcg.c file about to be moved into the tcg directory. Move the code that is needed for cpus that also work with KVM into cpu.c. Signed-off-by: Fabiano Rosas --- target/arm/cpu.c | 76 +++ target/arm/cpu

Re: [PATCH v10 2/9] KVM: Introduce per-page memory attributes

On Fri, Dec 02, 2022, Chao Peng wrote: > diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig > index fbeaa9ddef59..a8e379a3afee 100644 > --- a/arch/x86/kvm/Kconfig > +++ b/arch/x86/kvm/Kconfig > @@ -49,6 +49,7 @@ config KVM > select SRCU > select INTERVAL_TREE > select HAVE_K

Re: [RFC PATCH v3 20/28] target/arm: Set cortex-a57 as default cpu for KVM-only build

On 1/13/23 06:04, Fabiano Rosas wrote: The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the cortex-a57 as default cpu for KVM. Signed-off-by: Fabiano Rosas Ideally there would not be a default at all, requiring the command-line option to be used. Second choice would be "host"

Re: [RFC PATCH v3 20/28] target/arm: Set cortex-a57 as default cpu for KVM-only build

On 1/13/23 08:22, Fabiano Rosas wrote: Claudio Fontana writes: On 1/13/23 15:04, Fabiano Rosas wrote: The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the cortex-a57 as default cpu for KVM. Signed-off-by: Fabiano Rosas Our recommendation currently for KVM on ARM is to alway

Re: [RFC PATCH v3 21/28] tests/qtest: Skip tests that depend on TCG when CONFIG_TCG=n

On 1/13/23 06:04, Fabiano Rosas wrote: @@ -373,6 +387,11 @@ static void sve_tests_sve_off(const void *data) { QTestState *qts; +if (tcg_disabled()) { +g_test_skip("TCG support is disabled in this build"); +return; +} + qts = qtest_init(MACHINE "-cpu max,s

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