Hi,
In this version I followed Bin Meng's suggestion and reverted patch 1
back from what it was in the v5, acks included, and added a new patch
(3) to fix the problem detected with the Xvisor use case. I believe this
reflects that there is nothing particularly wrong with what we
did in the v5 patch and we're going an extra mile to fix what, at first
glance, is a bug somewhere else.
In patch 3 I also followed Phil's idea and used a translate_fn()
callback to do the bit clearing.
Changes from v6:
- patch 1:
- restored to the state it was in v5, acks included
- patch 3 (new):
- clear the higher bits from the result of load_elf_ram_sym() using a
translate_fn() callback for 32 bit CPUs
v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02630.html
Daniel Henrique Barboza (3):
hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
hw/riscv/boot.c: make riscv_load_initrd() static
hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym()
hw/riscv/boot.c | 111 ++++++++++++++++++++++++-------------
hw/riscv/microchip_pfsoc.c | 12 +---
hw/riscv/opentitan.c | 3 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/sifive_u.c | 12 +---
hw/riscv/spike.c | 13 +----
hw/riscv/virt.c | 12 +---
include/hw/riscv/boot.h | 3 +-
8 files changed, 89 insertions(+), 81 deletions(-)
--
2.39.0
