From: Philippe Mathieu-Daudé
This model was merged few days before the QOM cleanup from
commit 8063396bf3 ("Use OBJECT_DECLARE_SIMPLE_TYPE when possible")
was pulled and merged. Manually adapt.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.2316
From: Philippe Mathieu-Daudé
Following docs/devel/style.rst guidelines, rename omap2_gpif_s ->
Omap2GpioState. This also remove a use of 'struct' in the
DECLARE_INSTANCE_CHECKER() macro call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-
January 13, 2023 7:30 AM, "Philippe Mathieu-Daudé" wrote:
> On 13/1/23 12:05, Philippe Mathieu-Daudé wrote:
>
>> On 14/12/22 11:47, Thomas Huth wrote:
>>> On 16/02/2022 16.42, Alexander von Gluck IV wrote:
>>
>> ---
>> tests/vm/haiku.x86_64 | 8
>> 1 file changed, 4 insertions(+), 4 del
From: Philippe Mathieu-Daudé
The total_ram_v1/total_ram_v2 definitions were never used.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-10-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/omap_sx1.c | 2 --
1 file changed, 2 delet
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Add the FLASH_SECTOR_SIZE definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-9-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/mus
Move all the CONFIG_FOO=y from default.mak into "default y if TCG"
statements in Kconfig. That way they won't be selected when
CONFIG_TCG=n.
I'm leaving CONFIG_ARM_VIRT in default.mak because it allows us to
keep the two default.mak files not empty and keep aarch64-default.mak
including arm-defaul
Ah I see, i forgot about that one. Give me a bit and I'll see if it is the
same issue.
On Fri, Jan 13, 2023 at 9:41 AM Jonathan Cameron <
jonathan.came...@huawei.com> wrote:
> On Fri, 13 Jan 2023 09:19:59 -0500
> Gregory Price wrote:
>
> > On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Came
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-8-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/stellaris.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/stellaris
From: Philippe Mathieu-Daudé
Following docs/devel/style.rst guidelines, rename omap_gpif_s ->
Omap1GpioState. This also remove a use of 'struct' in the
DECLARE_INSTANCE_CHECKER() macro call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-5
This function is needed by common code (ptw.c), so move it along with
the other regime_* functions in internal.h. When we enable the build
without TCG, the tlb_helper.c file will not be present.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/internals.h | 21 +++
The cpu_tcg.c file about to be moved into the tcg directory. Move the
code that is needed for cpus that also work with KVM into cpu.c.
Signed-off-by: Fabiano Rosas
---
target/arm/cpu.c | 76 +++
target/arm/cpu_tcg.c | 77 ---
Introduce the target/arm/tcg directory. Its purpose is to hold the TCG
code that is selected by CONFIG_TCG.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
Also moved translate-{m-nocp,
From: Richard Henderson
Don't dereference CPUTLBEntryFull until we verify that
the page is valid. Move the other user-only info field
updates after the valid check to match.
Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1412
Signed-off-by: Richard Henderson
On 13/01/2023 15.04, Fabiano Rosas wrote:
We will soon enable the build without TCG, which does not support many
machines, so only run the bcm2835-dma-test when the corresponding
machine is present.
Signed-off-by: Fabiano Rosas
---
tests/qtest/meson.build | 4 ++--
1 file changed, 2 insertio
If a test was tagged with the "accel" tag and the specified
accelerator it not present in the qemu binary, cancel the test.
We can now write tests without explicit calls to require_accelerator,
just the tag is enough.
Signed-off-by: Fabiano Rosas
---
tests/avocado/avocado_qemu/__init__.py | 4 +
From: Philippe Mathieu-Daudé
This remove a use of 'struct' in the DECLARE_INSTANCE_CHECKER()
macro call, to avoid after a QOM refactor:
hw/timer/xilinx_timer.c:65:1: error: declaration of anonymous struct must be
a definition
DECLARE_INSTANCE_CHECKER(struct timerblock, XILINX_TIMER,
From: Philippe Mathieu-Daudé
Since pxa270_init() must map the device in the system memory,
there is no point in passing get_system_memory() by argument.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-3-phi...@linaro.org
Signed-off-by: Peter
From: Claudio Fontana
move the module containing cpu models definitions
for 32bit TCG-only CPUs to tcg/ and rename it for clarity.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/meson.build| 1 -
target/arm/{cpu_tcg.
From: Philippe Mathieu-Daudé
Add a local 'struct omap_gpif_s *' variable to improve readability.
(This also eases next commit conversion).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.23161-3-phi...@linaro.org
Signed-off-by: Peter Maydell
---
From: Evgeny Iakovlev
ARM trusted firmware, when built with FEAT_HCX support, sets SCR_EL3.HXEn bit
to allow EL2 to modify HCRX_EL2 register without trapping it in EL3. Qemu
uses a valid mask to clear unsupported SCR_EL3 bits when emulating SCR_EL3
write, and that mask doesn't include SCR_EL3.HXE
This struct has no dependencies on TCG code and it is being used in
target/arm/ptw.c to simplify the passing around of page table walk
results. Those routines can be reached by KVM code via the gdbstub
breakpoint code, so take the structure out of CONFIG_TCG to make it
visible when building with --
From: Strahinja Jankovic
During SPL boot several DRAM Controller registers are used. Most
important registers are those related to DRAM initialization and
calibration, where SPL initiates process and waits until certain bit is
set/cleared.
This patch adds these registers, initializes reset value
From: Philippe Mathieu-Daudé
Following docs/devel/style.rst guidelines, rename
omap_intr_handler_s -> OMAPIntcState. This also remove a
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140306.
This is in preparation to moving the hflags code into its own file
under the tcg/ directory.
Signed-off-by: Fabiano Rosas
---
I extracted these into a separate patch so we can discuss. If I move
the tcg_enabled check to a header that would add overhead for all the
calls where we know for sure tha
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-5-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/collie.c | 17 +++--
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/hw/arm/
On 1/13/23 15:04, Fabiano Rosas wrote:
> The cortex-a15 is not present anymore when CONFIG_TCG=n, so use the
> cortex-a57 as default cpu for KVM.
>
> Signed-off-by: Fabiano Rosas
Our recommendation currently for KVM on ARM is to always use CPU="host", as
named cpu models generally don't work (y
ull-target-arm-20230113
for you to fetch changes up to 08899b5c68a55a3780d707e2464073c8f2670d31:
target/arm: allow writes to SCR_EL3.HXEn bit when FEAT_HCX is enabled
(2023-01-13 13:19:36 +)
target-arm queue:
hw/arm/stm32f405:
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
Included {sme,mve}_helper.c and left a couple of files behind that
still have non-tcg code to be removed from them:
helper.c (and op_helper.h as a dep)
vfp_helper.c
Originally
From: Claudio Fontana
make it clearer from the name that this is a tcg-only function.
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
On 13/1/23 14:57, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
[resend fixing my last name typography...]
All series reviewed, can patches be picked by corresponding
maintainers?
The "qapi-commands-machine.h" header is not generated in user-only
emulation. This series removes its
The debug_helper.c file will move into a tcg-specific directory, so
take the cpregs code out of it. That code needs to be present in KVM
builds as well.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
---
target/arm/cpregs.c | 384 ++
target
From: Claudio Fontana
for "all" builds (tcg + kvm), we want to avoid doing
the psci check if tcg is built-in, but not enabled.
Signed-off-by: Claudio Fontana
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deleti
From: Claudio Fontana
Signed-off-by: Claudio Fontana
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Alex Bennée
---
target/arm/meson.build | 1 -
target/arm/tcg/meson.build | 4
target/arm/{ => tcg}/psci.c | 0
3 files changed, 4 insertions(+), 1 deletion
On 13/1/23 15:42, Philippe Mathieu-Daudé wrote:
On 13/1/23 14:57, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
[resend fixing my last name typography...]
All series reviewed, can patches be picked by corresponding
maintainers?
The "qapi-commands-machine.h" header is not generated
On Fri, 13 Jan 2023 14:40:26 +
Jonathan Cameron wrote:
> On Fri, 13 Jan 2023 09:19:59 -0500
> Gregory Price wrote:
>
> > On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote:
> > >
> > > Just to check, are these different from the on stack problem you reported
> > > previousl
On 1/11/23 01:07, Bernhard Beschow
wrote:
Am 9. Januar 2023 19:24:16 UTC schrieb John Snow :
On Tue, Sep 6, 2022 at 10:27 AM Bernhard Beschow wrote:
Am 19. Februar 2022 08:08:17 UTC schrieb Liav Albani :
On 1/13/2023 10:31 AM, Jason Wang wrote:
On Fri, Jan 13, 2023 at 1:27 AM Eugenio Pérez wrote:
Spuriously kick the destination device's queue so it knows in case there
are new descriptors.
RFC: This is somehow a gray area. The guest may have placed descriptors
in a virtqueue but not kicked i
Move this earlier to make the next patch diff cleaner. While here
update the comment slightly to not give the impression that the
misalignment affects only TCG.
Reviewed-by: Richard Henderson
Signed-off-by: Fabiano Rosas
---
target/arm/machine.c | 18 +-
1 file changed, 9 insert
On Sat, 24 Dec 2022 at 15:19, Richard Henderson
wrote:
>
> From: Ilya Leoshkevich
>
> Add a test that locklessly changes and exercises page protection bits
> from various threads. This helps catch race conditions in the VMA
> handling.
>
> Signed-off-by: Ilya Leoshkevich
> Message-Id: <202212231
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Add definitions for RAM / Flash / Flash blocksize.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-7-phi...@linaro.org
Message-Id: <20200223231044.8003
Thomas Huth writes:
> On 13/01/2023 15.04, Fabiano Rosas wrote:
>> Signed-off-by: Fabiano Rosas
>> ---
>> tests/qtest/arm-cpu-features.c | 24
>> 1 file changed, 24 insertions(+)
>>
>> diff --git a/tests/qtest/arm-cpu-features.c b/tests/qtest/arm-cpu-features.c
>> in
From: Strahinja Jankovic
Cubieboard now can boot directly from SD card, without the need to pass
`-kernel` parameter. Update Avocado tests to cover this functionality.
Signed-off-by: Strahinja Jankovic
Reviewed-by: Niek Linnenbank
Tested-by: Niek Linnenbank
Message-id: 20221226220303.14420-8-
On Fri, Jan 13, 2023 at 01:39:23PM +, Alex Bennée wrote:
> Drop the frankly misleading quickstart section for a more rounded
> introduction section. This new section gives an overview of the
> accelerators and high level introduction to some of the key features
> of the emulator. We also expand
From: Felipe Balbi
Olimex makes a series of low-cost STM32 boards. This commit introduces
the minimum setup to support SMT32-H405. See [1] for details
[1] https://www.olimex.com/Products/ARM/ST/STM32-H405/
Signed-off-by: Felipe Balbi
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair F
On Fri, Jan 13, 2023 at 10:20:31AM -0500, Peter Xu wrote:
> On Fri, Jan 13, 2023 at 02:47:24PM +0100, David Hildenbrand wrote:
> > I'd prefer to not go down that path for now. QEMU_VM_SECTION_START without
> > QEMU_VM_SECTION_PART and QEMU_VM_SECTION_END feels pretty incomplete and
> > wrong to me.
From: Strahinja Jankovic
This patch adds minimal support for AXP-209 PMU.
Most important is chip ID since U-Boot SPL expects version 0x1. Besides
the chip ID register, reset values for two more registers used by A10
U-Boot SPL are covered.
Signed-off-by: Strahinja Jankovic
Message-id: 202212262
From: Philippe Mathieu-Daudé
Since pxa255_init() must map the device in the system memory,
there is no point in passing get_system_memory() by argument.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-2-phi...@linaro.org
Signed-off-by: Peter
From: Strahinja Jankovic
This patch implements Allwinner TWI/I2C controller emulation. Only
master-mode functionality is implemented.
The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this is
first part enabling the TWI/I2C bus operation.
Since both Allwinner A10 and H3 use t
The file cpu_tcg.c is about to be moved into the tcg/ directory, so
move the register definitions into cpregs.c along with all the others.
Signed-off-by: Fabiano Rosas
---
target/arm/cpregs.c| 59 ++
target/arm/cpregs.h| 6 +
target/arm/cpu64.
From: Philippe Mathieu-Daudé
Following docs/devel/style.rst guidelines, rename
stellaris_adc_state -> StellarisADCState. This also remove a
use of 'struct' in the DECLARE_INSTANCE_CHECKER() macro call.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109140
On 13.01.23 16:20, Peter Xu wrote:
On Fri, Jan 13, 2023 at 02:47:24PM +0100, David Hildenbrand wrote:
I'd prefer to not go down that path for now. QEMU_VM_SECTION_START without
QEMU_VM_SECTION_PART and QEMU_VM_SECTION_END feels pretty incomplete and
wrong to me.
That's fine.
If we want to d
Am 04.01.2023 um 20:56 hat Stefan Hajnoczi geschrieben:
> scsi_device_purge_requests() is called from I/O code by virtio-scsi TMF
> emulation code. It must not call Global State APIs like blk_drain()
> because that results in an assertion failure.
>
> blk_drain() is a Global State API because it u
From: Strahinja Jankovic
This patch enables copying of SPL from MMC if `-kernel` parameter is not
passed when starting QEMU. SPL is copied to SRAM_A.
The approach is reused from Allwinner H3 implementation.
Tested with Armbian and custom Yocto image.
Signed-off-by: Strahinja Jankovic
Reviewe
On Fri, 13 Jan 2023 09:19:59 -0500
Gregory Price wrote:
> On Fri, Jan 13, 2023 at 09:12:13AM +, Jonathan Cameron wrote:
> >
> > Just to check, are these different from the on stack problem you reported
> > previously? Doesn't look like the fix for that has made it upstream yet.
> >
> > Wha
Currently we only emit trace events for existing PCI functions.
In order to ease debugging PCI enumeration process, also emit
for unexisting functions:
$ qemu-system-foo -trace pci_cfg_\*
...
pci_cfg_read empty 00:0a.4 @0x0 -> 0x
pci_cfg_read empty 00:0a.5 @0x0 -> 0x
pci_
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-11-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/omap_sx1.c | 33 +
From: Thomas Huth
These IRQ counting functions will soon be required in binaries that
do not include the APIC code, too, so let's extract them into a
separate file that can be linked independently of the APIC code.
While we're at it, change the apic_* prefix into kvm_* since the
functions are us
From: Bernhard Beschow
This even spares some casts in hot code paths along the way.
Signed-off-by: Bernhard Beschow
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Mark Cave-Ayland
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20230109172347.1830-10-shen...@gmail.com>
Signed-off-by: Philippe
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-4-phi...@linaro.org>
---
hw/mips/bootloader.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 0035f373
The GT-64120 is a north-bridge, and it is not MIPS specific.
Move it with the other north-bridge devices.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209151533.69516-8-phi...@linaro.org>
Reviewed-by: Richard Henderson
---
MAINTAINERS | 2 +-
hw/mips
On 13/01/2023 15.04, Fabiano Rosas wrote:
The tests under tests/tcg depend on the TCG accelerator. Do not build
them if --disable-tcg was given in the configure line.
Test against CONFIG_TCG='' instead of CONFIG_TCG=y to account for
CONFIG_TCG=m.
sample output:
$ make check-tcg
GIT ui/k
From: Bernhard Beschow
Suggested-by: Mark Cave-Ayland
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Message-Id: <20221204190553.3274-7-shen...@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/i386/pc_piix.c | 3 ++-
hw/i386/pc_q3
From: Bernhard Beschow
Tracking dependencies via Kconfig seems much cleaner.
Note that PIIX4 already depends on ACPI_PIIX4.
Signed-off-by: Bernhard Beschow
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Message-Id: <20230109172347.1830-8-shen...@gmail.com>
Signed-off-by:
The following changes since commit 3db29dcac23da85486704ef9e7a8e7217f7829cd:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2023-01-12 13:51:36 +)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20230113
for yo
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-6-phi...@linaro.org>
---
hw/mips/bootloader.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 9fc926d83f..1dd6
From: Paolo Bonzini
This support was limited to the Malta board, drop it.
I do not have a machine that can run VZ KVM, so I am assuming
that it works for -M malta as well.
Signed-off-by: Paolo Bonzini
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <2022122109
From: Philippe Mathieu-Daudé
This device does not have to be TARGET-dependent.
Add a 'cpu_big_endian' property which sets the byte-swapping
options if required.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221220113436.14299-5-phi...@linaro.org>
Reviewed-by: Richard Henderson
---
hw/m
Declare the TYPE_BONITO_PCI_HOST_BRIDGE QOM type in a
header to be able to access it from board code.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230105130710.49264-8-phi...@linaro.org>
---
MAINTAINERS | 1 +
hw/pci-host/bonito.c
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito* as bonito_pci*.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230105130710.49264-4-phi...@linaro.org>
---
hw/pci-host/bonito.c | 12 ++--
1 fil
On Fri, Jan 13, 2023 at 04:12:06PM +0100, Lukas Wunner wrote:
> On Fri, Jan 13, 2023 at 02:45:11PM +, Jonathan Cameron wrote:
> > On Fri, 13 Jan 2023 14:40:26 + Jonathan Cameron
> > wrote:
> > > On Fri, 13 Jan 2023 09:19:59 -0500 Gregory Price
> > > wrote:
> > > > On Fri, Jan 13, 2023 a
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Message-Id: <20221209151533.69516-2-phi...@linaro.org>
Reviewed-by: Richard Henderson
---
hw/mips/Kconfig | 6 ++
hw/mips/meson.build | 3 ++-
2 files changed, 8 insertions(+), 1 deletion(
Reviewed-by: Richard Henderson
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221211204533.85359-3-phi...@linaro.org>
---
hw/mips/bootloader.c | 24
1 file changed, 20 insertions(+), 4 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index 21f
Similarly to how commit 0c8427baf0 ("hw/mips/malta: Use bootloader
helper to set BAR registers") converted write_bootloader(), convert
the equivalent write_bootloader_nanomips(), allowing us to modify
the bootloader code more easily in the future.
Part 1/5: Convert PCI0 MEM1 BAR setup
Signed-off-
On Fri, Jan 13, 2023 at 02:47:24PM +0100, David Hildenbrand wrote:
> I'd prefer to not go down that path for now. QEMU_VM_SECTION_START without
> QEMU_VM_SECTION_PART and QEMU_VM_SECTION_END feels pretty incomplete and
> wrong to me.
That's fine.
>
> If we want to do that in the future, we shoul
No need to refresh the ASCII bar when a LED is toggled
(and vice versa).
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230104133935.4639-3-phi...@linaro.org>
---
hw/mips/malta.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git
From: Strahinja Jankovic
SPL Boot for Cubieboard expects AXP209 connected to I2C0 bus.
Signed-off-by: Strahinja Jankovic
Reviewed-by: Philippe Mathieu-Daudé
Message-id: 20221226220303.14420-6-strahinja.p.janko...@gmail.com
Signed-off-by: Peter Maydell
---
hw/arm/cubieboard.c | 6 ++
hw/
GT64120's PCI endianness swapping works on little-endian hosts,
but doesn't on big-endian ones. Instead of complicating how
CFGADDR/CFGDATA registers deal with endianness, use the existing
MemoryRegionOps from hw/pci/pci_host.c. Doing so also reduce the
access to internal PCI_HOST_BRIDGE fields.
M
If we get custom to see MAINTAINERS changes first,
we might catch missing MAINTAINERS updates easier.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221216225505.26052-1-phi...@linaro.org>
---
scripts/git.orderfile | 2 ++
1 file changed, 2 insertions(+)
di
Part 3/5: Convert PCI0 I/O BAR setup
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-9-phi...@linaro.org>
---
hw/mips/malta.c | 40
1 file changed, 8 insertions(+), 32 deletions(-)
diff --git a/hw/m
From: Daniel Henrique Barboza
Follow the QEMU convention of naming MachineState pointers as 'ms' by
renaming the instance in create_fdt() where we're calling it 'mc'.
Cc: Paul Burton
Cc: Aleksandar Rikalo
Suggested-by: Philippe Mathieu-Daudé
Signed-off-by: Daniel Henrique Barboza
Reviewed-by
Single registers access in ISD can produce multiple changes
in the address spaces. To reduce computational effort,
accumulate these as a single memory transaction.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230104133935.4639-5-phi...@linaro.org>
---
hw/m
From: Philippe Mathieu-Daudé
IEC binary prefixes ease code review: the unit is explicit.
Add the FLASH_SECTOR_SIZE definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230109115316.2235-8-phi...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/mai
Am 19.12.2022 um 13:26 hat Emanuele Giuseppe Esposito geschrieben:
> Am 16/12/2022 um 17:12 schrieb Vladimir Sementsov-Ogievskiy:
> > On 12/13/22 11:53, Kevin Wolf wrote:
> >> --- a/include/block/block_int-common.h
> >> +++ b/include/block/block_int-common.h
> >> @@ -729,7 +729,7 @@ struct BlockDri
From: Thomas Huth
The 'slew' tick policy is currently enforced to be only available on
x86 via some "#ifdef TARGET_I386" statements in mc146818rtc.c. We
want to get rid of those #ifdefs, so we need a different way of
checking whether the policy is allowed or not. Using the setter
function in hw/c
From: Philippe Mathieu-Daudé
The single machine using this device explicitly sets its
endianness. We don't need to set a default. This allow us
to remove the target specificity from the build system.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209151533.69516-7-phi...@linaro.org>
Re
IRQRC[A:D] registers reset value is 0x80. We were forcing
the MIPS Malta machine routing to be able to boot a Linux
kernel without any bootloader.
We now have these registers initialized in the Malta machine
write_bootloader(), so we can use the correct reset values.
Signed-off-by: Philippe Mathie
Part 5/5: Convert jumping to kernel
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-11-phi...@linaro.org>
---
hw/mips/malta.c | 68 -
1 file changed, 11 insertions(+), 57 deletions(-)
diff --
From: Strahinja Jankovic
During SPL boot several Clock Controller Module (CCM) registers are
read, most important are PLL and Tuning, as well as divisor registers.
This patch adds these registers and initializes reset values from user's
guide.
Signed-off-by: Strahinja Jankovic
Reviewed-by: Ni
From: Bernhard Beschow
pci_bus_irqs() coupled together the assignment of pci_set_irq_fn and
pci_map_irq_fn to a PCI bus. This coupling gets in the way when the
pci_map_irq_fn is board-specific while the pci_set_irq_fn is device-
specific.
For example, both of QEMU's PIIX south bridge models have
The PIIX4 PCI-ISA bridge function is always located at 10:0.
Since we want to re-use its address, add the PIIX4_PCI_DEVFN
definition.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Bernhard Beschow
Reviewed-by: Igor Mammedov
Reviewed-by: Michael S. Tsirkin
Message-Id: <20221027204720.33611
It is irrelevant to the API what the buffers to fill are made of.
In particular, some MIPS ISA have 16-bit wide instructions.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-2-phi...@linaro.org>
---
hw/mips/bootloader.c | 55 +++
From: Philippe Mathieu-Daudé
Per the comment in the Malta board, the [0x.-0x2000.]
range is decoded by the GT64120, so move the "empty_slot" there.
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221209151533.69516-3-phi...@linaro.org>
Reviewed-by: Richard Henderson
---
confi
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
From: Bernhard Beschow
pci_map_irq_fn's in general seem to be board-specific. So move PIIX3's
pci_slot_get_pirq() to board code to not have PIIX3 make assuptions
about its board.
Signed-off-by: Bernhard Beschow
Reviewed-by: Michael S. Tsirkin
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2
On 1/12/23 09:50, Avihai Horon wrote:
vfio_devices_all_running_and_saving() is used to check if migration is
in pre-copy phase. This is done by checking if migration is in setup or
active states and if all VFIO devices are in pre-copy state, i.e.
_SAVING | _RUNNING.
In VFIO migration protocol v2
Hi
On Tue, Jan 10, 2023 at 9:39 PM Alex Bennée wrote:
> We don't need to play timing games to ensure one socat wins over the
> other, just create the fifo they both can use before spawning the
> processes. However in the process we need to disable two tests for
> Windows platforms as we don't ha
Done to avoid fixing ACPI route description of traditional PCI interrupts on q35
and because we should probably move with the times anyway.
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 61 +++
1 file changed, 61 insertions(+)
diff --git a/h
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20221211204533.85359-5-phi...@linaro.org>
---
hw/mips/bootloader.c | 36 ++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader
To make it easier to differentiate between the Host Bridge
object and its PCI function #0, rename bonito_pcihost* as
bonito_host*.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20230105130710.49264-3-phi...@linaro.org>
---
hw/pci-host/bonito.c | 12 ++
This function cannot fail since g_malloc0 aborts on OOM.
Signed-off-by: Daniel P. Berrangé
---
audio/audio.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/audio/audio.c b/audio/audio.c
index d849a94a81..7b4b957945 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -171
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