At present the PLIC config parser can only handle legal config string
like "MS,MS". However if a config string like ",MS,MS,,MS,MS,," is
given the parser won't get the correct configuration.
This commit improves the config parser to make it more robust.
Signed-off-by: Bin Meng
---
hw/intc/sifi
Richard Henderson writes:
> The only thing that still touches PageDesc in translate-all.c
> are some locking routines related to tb-maint.c which have not
> yet been moved. Do so now.
>
> Move some code up in tb-maint.c as well, to untangle the maze
> of ifdefs, and allow a sensible final orde
This is a follow-up on older attempts to make a second UART
available for the arm-virt machine in normal world. The use case
is, that this give a simple I/O channel in addition to stdout, as this
simplifies various test scenarios. Especially for non-Linux operating
systems (e.g. seL4) where arm-vir
From: Axel Heider
The first UART always always exists. If the security extensions are
enabled, the second UART also always exists. Otherwise, it only exists
if a backend is configured explicitly via '-serial ', where
'null' creates a dummy backend. This allows enabling the second UART
explicitly
On Thu, Dec 01, 2022 at 01:39:13PM +0100, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
> >> HMP "info spice" has a bit of code to show channel type
> >> SPICE_CHANNEL_WEBDAV as "webdav", disabled since commit 7c6044
On Thu, Dec 01, 2022 at 10:36:23AM +0100, Alexandre Ghiti wrote:
> RISC-V specifies multiple sizes for addressable memory and Linux probes for
> the machine's support at startup via the satp CSR register (done in
> csr.c:validate_vm).
>
> As per the specification, sv64 must support sv57, which in
On Thu, Dec 01, 2022 at 04:35:48PM +0800, Jason Wang wrote:
> On Wed, Nov 30, 2022 at 11:17 PM Peter Xu wrote:
> >
> > On Wed, Nov 30, 2022 at 02:33:51PM +0800, Jason Wang wrote:
> > > On Tue, Nov 29, 2022 at 11:57 PM Peter Xu wrote:
> > > >
> > > > On Tue, Nov 29, 2022 at 04:10:37PM +0800, Jason
luzhipeng writes:
> From: zhipeng Lu
>
> The drive interface supports media=cdrom so that the usb cdrom
> can be emulated as cdrom in qemu, but libvirt deprived the drive
> interface, so media=cdrom is added to the blockdev interface to
> support usb cdrom emulated as cdrom
>
> Signed-off-by: zh
On 1/12/22 13:36, Ilya Leoshkevich wrote:
On Wed, 2022-11-30 at 17:34 +0100, Philippe Mathieu-Daudé wrote:
Although TCGv is defined as TCGv_i64 on s390x,
make it clear tcg_temp_new_i64() returns a TCGv_i64.
Signed-off-by: Philippe Mathieu-Daudé
---
target/s390x/tcg/translate.c | 2 +-
1 fil
From: Axel Heider
The interrupt state can change due to:
- reset clears both SR.OCIF and CR.OCIE
- write to CR.EN or CR.OCIE
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/i
From: Axel Heider
- fix #1263 for CR writes
- rework compare time handling
- The compare timer has to run even if CR.OCIEN is not set,
as SR.OCIF must be updated.
- The compare timer fires exactly once when the
compare value is less than the current value, but the
reload values is
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 20 ++--
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 7af3a8b10e..39f47222d0 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit.c
@@ -99
From: Axel Heider
---
hw/timer/imx_epit.c | 12 ++--
include/hw/timer/imx_epit.h | 2 ++
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 661e9158e3..f148868b8c 100644
--- a/hw/timer/imx_epit.c
+++ b/hw/timer/imx_epit
From: Axel Heider
remove unused defines, add needed defines
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 4 ++--
include/hw/timer/imx_epit.h | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 2841fbaa1c..661e
From: Axel Heider
The CNT register is a read-only register. There is no need to
store it's value, it can be calculated on demand.
The calculated frequency is needed temporarily only.
Note that this is a migration compatibility break for all boards
types that use the EPIT peripheral.
Signed-off-
From: Axel Heider
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 207
1 file changed, 113 insertions(+), 94 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index 39f47222d0..e04427542f 100644
--- a/hw/timer/imx_epit.c
+++ b
From: Axel Heider
Fix typos, add background information
Signed-off-by: Axel Heider
---
hw/timer/imx_epit.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c
index ec0fa440d7..2841fbaa1c 100644
--- a/hw/timer/imx_
Daniel P. Berrangé writes:
> On Thu, Dec 01, 2022 at 01:39:13PM +0100, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
>> >> HMP "info spice" has a bit of code to show channel type
>> >> SPICE_CHANNEL_WEBDAV as "w
On Tue, Nov 29, 2022 at 04:10:36PM +0800, Jason Wang wrote:
> Without dt mode, device IOTLB notifier won't work since guest won't
> send device IOTLB invalidation descriptor in this case. Let's fail
> early instead of misbehaving silently.
>
> Signed-off-by: Jason Wang
> ---
> hw/i386/intel_iomm
On 12/1/22 05:37, Thomas Huth wrote:
Many users forget to remove the suggestions from the bug template
when creating a new issue. So when searching for strings like "s390x"
or "Windows", you get a lot of unrelated issues in the results.
Thus let's move the suggestions into HTML comments - so they
It seems not super clear on when iova_tree is used, and why. Add a rich
comment above iova_tree to track why we needed the iova_tree, and when we
need it.
Suggested-by: Jason Wang
Signed-off-by: Peter Xu
---
include/hw/i386/intel_iommu.h | 30 +-
1 file changed, 29
On Tue, 22 Nov 2022 at 23:25, Zhuojia Shen wrote:
>
> In CPUID registers exposed to userspace, some registers were missing
> and some fields were not exposed. This patch aligns exposed ID
> registers and their fields with what the upstream kernel currently
> exposes.
Thanks; I've applied this to
From: Klaus Jensen
There are several bugs in the async cancel code for the Format command.
Firstly, cancelling a format operation neglects to set iocb->ret as well
as clearing the iocb->aiocb after cancelling the underlying aiocb which
causes the aio callback to ignore the cancellation. Trivial
From: Klaus Jensen
Make sure that iocb->aiocb is NULL'ed when cancelling.
Fix a potential use-after-free by removing the bottom half and enqueuing
the completion directly.
Fixes: 38f4ac65ac88 ("hw/nvme: reimplement flush to allow cancellation")
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jen
From: Klaus Jensen
If the zone reset operation is cancelled but the block unmap operation
completes normally, the callback will continue resetting the next zone
since it neglects to check iocb->ret which will have been set to
-ECANCELED. Make sure that this is checked and bail out if an error is
From: Klaus Jensen
Fix a potential use-after-free by removing the bottom half and enqueuing
the completion directly.
Fixes: 796d20681d9b ("hw/nvme: reimplement the copy command to allow aio
cancellation")
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 63 ++
From: Klaus Jensen
Hi,
The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
Update VERSION for v7.2.0-rc3 (2022-11-29 18:15:26 -0500)
are available in the Git repository at:
git://git.infradead.org/qemu-nvme.git tags/nvme-next-pull-request
for you to fetch changes
From: Klaus Jensen
When the DSM operation is cancelled asynchronously, we set iocb->ret to
-ECANCELED. However, the callback function only checks the return value
of the completed aio, which may have completed succesfully prior to the
cancellation and thus the callback ends up continuing the dsm
Stefan Hajnoczi writes:
> [[PGP Signed Part:Undecided]]
> On Wed, Nov 30, 2022 at 11:24:38AM +, Alex Bennée wrote:
>> ..and use for both virtio-user-blk and virtio-user-gpio. This avoids
>> the circular close by deferring shutdown due to disconnection until a
>> later point.
>
> I thought r
Hi Peter
On 12/1/22 17:25, Peter Xu wrote:
> It seems not super clear on when iova_tree is used, and why. Add a rich
> comment above iova_tree to track why we needed the iova_tree, and when we
> need it.
>
> Suggested-by: Jason Wang
> Signed-off-by: Peter Xu
> ---
> include/hw/i386/intel_iommu
The SET ADDRESS SPACE CONTROL FAST code has a couple of issues:
1) The instruction is not privileged, it can be used from problem space,
too. Just the switching to the home address space is privileged and
should still generate a privilege exception. This bug is e.g. causing
programs like Java that
On 01/12/2022 19.27, Thomas Huth wrote:
The SET ADDRESS SPACE CONTROL FAST code has a couple of issues:
1) The instruction is not privileged, it can be used from problem space,
too. Just the switching to the home address space is privileged and
should still generate a privilege exception. This b
On Thu, Dec 01, 2022 at 04:49:25PM +0100, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Thu, Dec 01, 2022 at 01:39:13PM +0100, Markus Armbruster wrote:
> >> Daniel P. Berrangé writes:
> >>
> >> > On Thu, Dec 01, 2022 at 07:13:05AM +0100, Markus Armbruster wrote:
> >> >> HMP "in
The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be
used from problem space, too. Just the switching to the home address space
is privileged and should still generate a privilege exception. This bug is
e.g. causing programs like Java that use the "getcpu" vdso kernel functio
Richard Henderson writes:
> On 11/30/22 10:07, Ilya Leoshkevich wrote:
>> Reviewed-by: Ilya Leoshkevich
>> While not directly related to this patch, it would be good to update
>> tcg/README with all the new kinds of temporaries. E.g. the EBB ones are
>> not mentioned there:
>> TCG instruc
Thomas Huth writes:
> Many users forget to remove the suggestions from the bug template
> when creating a new issue. So when searching for strings like "s390x"
> or "Windows", you get a lot of unrelated issues in the results.
> Thus let's move the suggestions into HTML comments - so they will
>
On Thu, Dec 01, 2022 at 07:17:41PM +0100, Eric Auger wrote:
> Hi Peter
Hi, Eric,
>
> On 12/1/22 17:25, Peter Xu wrote:
> > It seems not super clear on when iova_tree is used, and why. Add a rich
> > comment above iova_tree to track why we needed the iova_tree, and when we
> > need it.
> >
> > S
Aaron Lindsay writes:
> On Nov 22 10:57, Aaron Lindsay wrote:
>> On Nov 21 18:22, Richard Henderson wrote:
>> > On 11/21/22 13:51, Alex Bennée wrote:
>> > >
>> > > Aaron Lindsay writes:
>> > >
>> > > > On Nov 15 22:36, Alex Bennée wrote:
>> > > > > Aaron Lindsay writes:
>> > > > > > I belie
On Thu, Dec 01, 2022 at 02:22:27PM -0500, Peter Xu wrote:
> On Thu, Dec 01, 2022 at 07:17:41PM +0100, Eric Auger wrote:
> > Hi Peter
>
> Hi, Eric,
>
> >
> > On 12/1/22 17:25, Peter Xu wrote:
> > > It seems not super clear on when iova_tree is used, and why. Add a rich
> > > comment above iova_t
Hi Paul,
From: Paul Durrant
Date: Wednesday, October 19, 2022 at 7:54 AM
To: Garhwal, Vikram , qemu-devel@nongnu.org
Cc: Stabellini, Stefano , Michael S. Tsirkin
, Marcel Apfelbaum , Paolo Bonzini
, Richard Henderson ,
Eduardo Habkost , Stefano Stabellini
, Anthony Perard , open
list:X86 X
On 12/1/22 11:13, Alex Bennée wrote:
I'm not sure I want to take this anymore. It's confusing to use. I
really think what I should do instead is improve the TCG register
allocator.
Whats the ultimate aim for the rewrite? Hold values in target registers
over the extended block? What about avoi
On 12/1/22 10:44, Thomas Huth wrote:
The SET ADDRESS SPACE CONTROL FAST instruction is not privileged, it can be
used from problem space, too. Just the switching to the home address space
is privileged and should still generate a privilege exception. This bug is
e.g. causing programs like Java th
On Thu, Dec 01, 2022 at 12:21:21PM +, Alex Bennée wrote:
>
> "Michael S. Tsirkin" writes:
>
> > On Thu, Dec 01, 2022 at 10:14:39AM +, Alex Bennée wrote:
> >> Do you think rust-vmm's vhost crates have enough of the state
> >> management to manage vhost and vhost-user backends? Maybe it wo
On Thu, 2022-12-01 at 22:07 +0800, Bin Meng wrote:
> Since commit ef6310064820 ("hw/riscv: opentitan: Update to the latest
> build")
> the IBEX PLIC model was replaced with the SiFive PLIC model in the
> 'opentitan' machine but we forgot the add the dependency there.
>
> Signed-off-by: Bin Meng
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> PLIC is not included in the 'spike' machine.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/spike.c | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index 1e1d752c00.
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> H-mode has been removed since priv spec 1.10. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> include/hw/intc/sifive_plic.h | 1 -
> hw/intc/sifive_plic.c | 1 -
> 2 files changed, 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> Per chapter 6.5.2 in [1], the number of interupt sources including
> interrupt source 0 should be 187.
>
> [1] PolarFire SoC MSS TRM:
> https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_S
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> Per chapter 10 in Freedom E310 manuals [1][2][3], E310 G002 and G003
> supports 52 interrupt sources while G000 supports 51 interrupt
> sources.
>
> We use the value of G002 and G003, so it is 53 (including source 0).
>
> [1] G000 manual:
> htt
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> At present magic number is used to create "riscv,ndev" property
> in the dtb. Let's use the macro SIFIVE_U_PLIC_NUM_SOURCES that
> is used to instantiate the PLIC model instead.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/sifive_u.c | 3 ++
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/opentitan.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
>
The "perf stat" at the VM side still works even we set "-cpu host,-pmu" in
the QEMU command line. That is, neither "-cpu host,-pmu" nor "-cpu EPYC"
could disable the pmu virtualization in an AMD environment.
We still see below at VM kernel side ...
[0.510611] Performance Events: Fam17h+ core
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> The pending register upper limit is currently set to
> plic->num_sources >> 3, which is wrong, e.g.: considering
> plic->num_sources is 7, the upper limit becomes 0 which fails
> the range check if reading the pending register at pending_base.
>
This patchset is to fix two svm pmu virtualization bugs, x86 only.
version 1:
https://lore.kernel.org/all/20221119122901.2469-1-dongli.zh...@oracle.com/
1. The 1st bug is that "-cpu,-pmu" cannot disable svm pmu virtualization.
To use "-cpu EPYC" or "-cpu host,-pmu" cannot disable the pmu
virtual
The QEMU side calls kvm_get_msrs() to save the pmu registers from the KVM
side to QEMU, and calls kvm_put_msrs() to store the pmu registers back to
the KVM side.
However, only the Intel gp/fixed/global pmu registers are involved. There
is not any implementation for AMD pmu registers. The
'has_arch
On Tue, Oct 25, 2022 at 8:18 AM Chao Peng wrote:
>
> From: "Kirill A. Shutemov"
>
> Introduce 'memfd_restricted' system call with the ability to create
> memory areas that are restricted from userspace access through ordinary
> MMU operations (e.g. read/write/mmap). The memory content is expected
libvirt issue： https://gitlab.com/libvirt/libvirt/-/issues/261
1、start vm with usb cdrom
2、 get qemu cmdline
qemu ... -blockdev
{"driver":"file","filename":"/tmp/cdrom","node-name":"libvirt-1-storage","auto-read-only":true,"discard":"unmap"}
-blockdev
{"node-name":"libv
Hi Ard,
在 2022/12/1 19:07, Ard Biesheuvel 写道:
On Thu, 1 Dec 2022 at 09:07, Ard Biesheuvel wrote:
On Thu, 1 Dec 2022 at 08:15, chenxiang (M) wrote:
Hi Ard,
在 2022/11/30 16:18, Ard Biesheuvel 写道:
On Wed, 30 Nov 2022 at 08:53, Marc Zyngier wrote:
On Wed, 30 Nov 2022 02:52:35 +,
"chenx
From: Stefano Stabellini
This is done to prepare for enabling xenpv support for ARM architecture.
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails,
continue to the PV backends initialization.
Signed-off-by
Add CONFIG_XEN for aarch64 device to support build for ARM targets.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 81d36420f0..a4965251a
xenstore_record_dm_state() will also be used in aarch64 xenpv machine.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
accel/xen/xen-all.c | 2 +-
include/hw/xen/xen.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/xen/xen-all.c b/accel/xen/xen-
From: Stefano Stabellini
This patch does following:
1. creates arch_handle_ioreq() and arch_xen_set_memory(). This is done in
preparation for moving most of xen-hvm code to an arch-neutral location,
move the x86-specific portion of xen_set_memory to arch_xen_set_memory.
Also, move han
From: Stefano Stabellini
have_xen_pci_passthrough is only used for Xen x86 VMs.
Signed-off-by: Stefano Stabellini
Reviewed-by: Alex Bennée
---
meson.build | 2 ++
1 file changed, 2 insertions(+)
diff --git a/meson.build b/meson.build
index 5c6b5a1c75..81d36420f0 100644
--- a/meson.build
+++
Add a new machine xenpv which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and support TPM functionalities for a guest dom
From: Stefano Stabellini
On ARM it is possible to have a functioning xenpv machine with only the
PV backends and no IOREQ server. If the IOREQ server creation fails continue
to the PV backends initialization.
Also, moved the IOREQ registration and mapping subroutine to new function
xen_do_ioreq_
In preparation to moving most of xen-hvm code to an arch-neutral location,
move non IOREQ references to:
- xen_get_vmport_regs_pfn
- xen_suspend_notifier
- xen_wakeup_notifier
- xen_ram_init
towards the end of the xen_hvm_init_pc() function.
This is done to keep the common ioreq functions in one
xen-mapcache.c contains common functions which can be used for enabling Xen on
aarch64 with IOREQ handling. Moving it out from hw/i386/xen to hw/xen to make it
accessible for both aarch64 and x86.
Signed-off-by: Vikram Garhwal
Signed-off-by: Stefano Stabellini
---
hw/i386/meson.build
Replace g_malloc with g_new and perror with error_setg_errno.
Signed-off-by: Vikram Garhwal
---
hw/xen/xen-hvm-common.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/hw/xen/xen-hvm-common.c b/hw/xen/xen-hvm-common.c
index 03128e575b..4ba5141fa2 100644
--- a/
From: Stefano Stabellini
In preparation to moving most of xen-hvm code to an arch-neutral location, move:
- shared_vmport_page
- log_for_dirtybit
- dirty_bitmap
- suspend
- wakeup
out of XenIOState struct as these are only used on x86, especially the ones
related to dirty logging.
Updated XenIOS
Hi Julien,
From: Julien Grall
Date: Sunday, October 16, 2022 at 10:48 AM
To: Garhwal, Vikram , qemu-devel@nongnu.org
Cc: Stabellini, Stefano , Peter Maydell
, Stefano Stabellini ,
Anthony Perard , Paul Durrant , open
list:ARM TCG CPUs , open list:X86 Xen CPUs
Subject: Re: [PATCH v1 10/12]
Add a helper function for computing the size of a type.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 16
tcg/tcg.c | 27 ---
2 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/include/
Create two new functions, set_temp_val_{reg,nonreg}.
Assert that the reg_to_temp mapping is correct before
any changes are made.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 159 +-
1 file changed, 85 insertions(+), 74 deletions(-)
diff --
Allocate the first of a pair at the lower address, and the
second of a pair at the higher address. This will make it
easier to find the beginning of the larger memory block.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg-internal.h | 4 ++--
tcg/tcg.c
Remove whitespace at end of line, plus one place this also
highlights some missing braces.
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 33 +
tcg/ppc/tcg-target.c.inc | 2 +-
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/tcg/
We now check the consistency of reg_to_temp[] with each update,
so the utility of checking consistency at the end of each
opcode is minimal. In addition, the form of this check is
quite expensive, consuming 10% of a checking-enabled build.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 76 ---
Change 32-bit tci TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EVEN, to
force 32-bit values to be aligned to 64-bit. With a small reorg
to the argument processing loop, this neatly replaces an ifdef for
CONFIG_TCG_INTERPRETER.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
From: Philippe Mathieu-Daudé
In the unlikely case of invalid typecode mask, the function
will abort instead of returning a NULL pointer.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe M
Like CONFIG_TCG, the enabled method of execution is a host property
not a guest property. This exposes the define to compile-once files.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/m
From: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221122180804.938-3-phi...@linaro.org>
---
tcg/tcg.c | 83 ++
From: Philippe Mathieu-Daudé
We are going to modify this code, so fix its style first to avoid:
ERROR: spaces required around that '*' (ctx:VxV)
#281: FILE: tcg/s390x/tcg-target.c.inc:1224:
+uintptr_t mask = ~(0xull << i*16);
^
Revie
Unused since commit 7b7d8b2d9a ("tcg/tci: Use ffi for calls").
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tci.c| 1 -
tcg/tci/tcg-target.c.inc | 4
2 files changed, 5 deletions(-)
diff --git a/tcg/tci.c b/tcg/tci.c
index bdfac83492..05a241
Record the location of a TCGTemp within a larger object.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
tcg/tcg.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index d207bc47be..afa18986b1
We have been allocating a worst case number of arguments
to support calls. Instead, allow the size to vary.
By default leave space for 4 args, to maximize reuse,
but allow calls to increase the number of args to 32.
Signed-off-by: Richard Henderson
---
include/exec/helper-head.h | 2 --
includ
From: Mark Cave-Ayland
Convert tcg/README to rst and move it to docs/devel as a new "TCG Intermediate
Representation" page. There are a few minor changes to improve the aesthetic
of the final output which are as follows:
- Rename the title from "Tiny Code Generator - Fabrice Bellard" to "TCG
This eliminates an ifdef for TCI, and will be required for
expanding the call for TCGv_i128.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c| 12 ++--
tcg/aarch64/tcg-target.c.inc | 12 +---
tcg/arm/tcg-target.c.inc
The hppa host code has been removed since 2013; this
should have been deleted at the same time.
Fixes: 802b5081233a ("tcg-hppa: Remove tcg backend")
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 -
tcg/arm/tcg-target.h | 1 -
tcg/tcg
This contains a few bits that I've queued for 8.0, as well
as the first half of the TCGv_i128 patch set (just prior to
the introduction of TCG_TYPE_I128).
Included are the paired register patches, which have seen
changes since v2, and a bit more testing on s390x host
(which uses register pairs for
The function pointer is immediately after the output and input
operands; no need to search.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 29 +++--
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-ge
We copied all of the arguments in copy_op_nocheck.
We only need to replace the one argument that we change.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plu
The count is not itself an enumerator. Move it outside to
prevent the compiler from considering it with -Wswitch-enum.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/tcg/tc
For 64-bit hosts that had TCG_TARGET_EXTEND_ARGS, set
TCG_TARGET_CALL_ARG_I32 to TCG_CALL_ARG_EXTEND.
Otherwise, use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 1 +
tcg/arm/tcg-target.h | 1 +
tcg/i386/t
Move the error-generating fallback from tcg-op.c, and
replace "_link_error" with modern QEMU_ERROR markup.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-op.h | 33 +
include/tcg/tcg.h| 12
tcg/tcg-intern
There are several instances where we need to be able to
allocate a pair of registers to related inputs/outputs.
Add 'p' and 'm' register constraints for this, in order to
be able to allocate the even/odd register first or second.
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 2 +
tc
We will shortly have the possibility of more that two outputs,
though only for calls (for which preferences are moot). Avoid
direct references to op->output_pref[] when possible.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 5 +
tcg/tcg.c
Replace goto allocate_in_reg with a boolean.
Remove o_preferred_regs which isn't used, except to copy.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 45 +
1 file changed, 21 insertions(+), 24 deletions(-)
diff -
The assignment to mem_coherent should be done with any
modification, not simply with a newly allocated register.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index db64799e03..d1e91b8acc 100644
--- a/
Instead of requiring a separate hash table lookup,
put a pointer to the CIF into TCGHelperInfo.
Signed-off-by: Richard Henderson
Message-Id: <2022074101.2069454-27-richard.hender...@linaro.org>
[PMD: Split from bigger patch]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20221122180804.9
The first thing that temp_sync does is check mem_coherent,
so there's no need for the caller to do so.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 0f58013a5a..36a33a122c 100644
--- a/tcg/tc
On 02.12.22 04:00, Vikram Garhwal wrote:
Add a new machine xenpv which creates a IOREQ server to register/connect with
Xen Hypervisor.
Optional: When CONFIG_TPM is enabled, it also creates a tpm-tis-device, adds a
TPM emulator and connects to swtpm running on host machine via chardev socket
and
Better to re-use the existing function for copying ops.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index 77e6
For 32-bit hosts when TCG_TARGET_CALL_ALIGN_ARGS was set, use
TCG_CALL_ARG_EVEN. For 64-bit hosts, TCG_TARGET_CALL_ALIGN_ARGS
was silently ignored, so always use TCG_CALL_ARG_NORMAL.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.h | 2 +-
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