On 10/10/2022 18.09, Cornelia Huck wrote:
I haven't really been working on s390x for some time now, and in
practice, I don't have time for it, either. So let's remove myself
from this entry.
Signed-off-by: Cornelia Huck
---
MAINTAINERS | 2 --
1 file changed, 2 deletions(-)
Cornelia, thank
在 2022/10/10 22:43, Peter Maydell 写道:
On Mon, 10 Oct 2022 at 15:20, Richard Henderson
wrote:
On 9/17/22 00:43, Song Gao wrote:
We can use alternate stack, so that we can use sp register as intput/ouput
register.
I had tested aarch64/LoongArch architecture.
Signed-off-by: Song Gao
---
ri
On 10/11/22 10:20 AM, Daniil Tatianin wrote:
Ping :)
Oops, didn't see the pull request. Disregard this.
On 9/6/22 10:31 AM, Daniil Tatianin wrote:
This patch set attempts to align vhost-user-blk with virtio-blk in
terms of backward compatibility and flexibility. It also improves
the virtio
Ping :)
On 9/6/22 10:31 AM, Daniil Tatianin wrote:
This patch set attempts to align vhost-user-blk with virtio-blk in
terms of backward compatibility and flexibility. It also improves
the virtio core by introducing new common code that can be used by
a virtio device to calculate its config space
On 9/28/22 18:28, Cédric Le Goater wrote:
On 9/28/22 18:16, Pierre Morel wrote:
More thinking about this I will drop this patch for backward
compatibility and in topology masks treat CPUs as being cores*threads
yes. You never know, people might have set threads=2 in their
domain file (like
On 10/11/22 09:21, Pierre Morel wrote:
On 9/28/22 18:28, Cédric Le Goater wrote:
On 9/28/22 18:16, Pierre Morel wrote:
More thinking about this I will drop this patch for backward compatibility and
in topology masks treat CPUs as being cores*threads
yes. You never know, people might have s
On 11.10.22 08:03, Markus Armbruster wrote:
David Hildenbrand writes:
Let's make it easier to pin threads created via a ThreadContext to
all CPUs currently belonging to a given set of NUMA nodes -- which is the
common case.
"node-affinity" is simply a shortcut for setting "cpu-affinity" manua
But note that due to dynamic library loading this example will not work
before we actually make use of thread_context_create_thread() in QEMU
code, because the type will otherwise not get registered.
What do you mean exactly by "not work"? It's not "CLI option or HMP
command fails":
For me,
Le 03/10/2022 à 13:02, Jason A. Donenfeld a écrit :
Rather than poking directly into RAM, add the bootinfo block as a proper
ROM, so that it's restored when rebooting the system. This way, if the
guest corrupts any of the bootinfo items, but then tries to reboot,
it'll still be restored back to n
On Mon, 10 Oct 2022 15:29:39 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Gcc requires constant versions of cpu_to_le* calls.
>
> Add a 64 bit version.
>
> Signed-off-by: Ira Weiny
Seems reasonable to me but I'm not an expert in this stuff.
FWIW
Reviewed-by: Jonathan Cameron
The
* David Hildenbrand (da...@redhat.com) wrote:
> On 10.10.22 12:40, Dr. David Alan Gilbert wrote:
> > * David Hildenbrand (da...@redhat.com) wrote:
> > > This is a follow-up on "util: NUMA aware memory preallocation" [1] by
> > > Michal.
> > >
> > > Setting the CPU affinity of threads from inside Q
On Mon, 10 Oct 2022 15:29:40 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> UUID's are defined as network byte order fields. No static initializer
> was available for UUID's in their standard big endian format.
>
> Define a big endian initializer for UUIDs.
>
> Signed-off-by: Ira Wein
From: Marc-André Lureau
As described in:
https://learn.microsoft.com/en-us/visualstudio/debugger/how-to-set-a-thread-name-in-native-code?view=vs-2022
SetThreadDescription() is available since Windows 10, version 1607 and
in some versions only by "Run Time Dynamic Linking". Its declaration is
not
On Tue, 11 Oct 2022 at 07:57, gaosong wrote:
>
>
> 在 2022/10/10 22:43, Peter Maydell 写道:
> > On Mon, 10 Oct 2022 at 15:20, Richard Henderson
> > wrote:
> >> On 9/17/22 00:43, Song Gao wrote:
> >>> We can use alternate stack, so that we can use sp register as
> >>> intput/ouput register.
> >>> I
On Tue, 11 Oct 2022 at 09:41, Laurent Vivier wrote:
>
> Le 03/10/2022 à 13:02, Jason A. Donenfeld a écrit :
> > Rather than poking directly into RAM, add the bootinfo block as a proper
> > ROM, so that it's restored when rebooting the system. This way, if the
> > guest corrupts any of the bootinfo
On Sat, Oct 08, 2022 at 04:50:29PM +0800, Lei He wrote:
> crypto: support export RSA private keys with PKCS#8 standard.
> So that users can upload this private key to linux kernel.
>
> Signed-off-by: lei he
> ---
> crypto/akcipher.c | 18 ++
> crypto/rsakey.c |
On Mon, 10 Oct 2022 15:29:38 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> CXL Event records inform the OS of various CXL device events. Thus far CXL
> memory devices are emulated and therefore don't naturally have events which
> will occur.
>
> Add mock events and a HMP trigger mecha
On Sat, Oct 08, 2022 at 04:50:28PM +0800, Lei He wrote:
> Add encoding interfaces for DER encoding:
> 1. support decoding of 'bit string', 'octet string', 'object id'
> and 'context specific tag' for DER encoder.
> 2. implemented a simple DER encoder.
> 3. add more testsuits for DER encoder.
>
> S
On Mon, 10 Oct 2022 at 23:48, wrote:
>
> From: Ira Weiny
>
> Gcc requires constant versions of cpu_to_le* calls.
>
> Add a 64 bit version.
>
> Signed-off-by: Ira Weiny
> ---
> include/qemu/bswap.h | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/include/qemu/bswap.h b/includ
Hi Jonathan,
We've reviewed the patches related to DOE and everything looks good. And we
are glad to maintain the code as the maintainers.
Thanks for applying the changes.
Best Regards,
Huai-Cheng Kuo
On Mon, Oct 10, 2022 at 6:30 PM Jonathan Cameron <
jonathan.came...@huawei.com> wrote:
> On F
Hi,
On Thu, Sep 15, 2022 at 3:38 PM Chao Peng wrote:
>
> If CONFIG_HAVE_KVM_PRIVATE_MEM=y, userspace can register/unregister the
> guest private memory regions through KVM_MEMORY_ENCRYPT_{UN,}REG_REGION
> ioctls. The patch reuses existing SEV ioctl number but differs that the
> address in the reg
On Mon, 10 Oct 2022 15:29:41 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> To facilitate testing of guest software add mock events and code to
> support iterating through the event logs.
>
> Signed-off-by: Ira Weiny
Various comments inline, but biggest one is I'd like to see
a much m
The element size is encoded in the M3 field, not in the M4
field. Let's also add a TCG test that shows the failing
behavior without this fix.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1248
Signed-off-by: Thomas Huth
---
tests/tcg/s390x/vf.c| 50 +
I would like to ping a patch
https://patchew.org/QEMU/20220929223547.1429580-1-michael.lab...@virtuozzo.com/
On 9/30/22 01:35, Michael Labiuk via wrote:
Add pci bridge setting to run hotplug tests on q35 machine type.
Hotplug tests was bounded to 'pc' machine type by commit 7b172333f1b
v5
On Mon, 3 Oct 2022, BALATON Zoltan wrote:
This series includes some clean ups to mac_newworld and mac_oldworld
to make them a bit simpler and more readable, It also removes the
shared mac.h file that turns out was more of a random collection of
unrelated things. Getting rid of this mac.h improves
On Mon, 10 Oct 2022 15:29:42 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Replace the stubbed out CXL Get/Clear Event mailbox commands with
> commands which return the mock event information.
>
> Signed-off-by: Ira Weiny
> ---
> hw/cxl/cxl-device-utils.c | 1 +
> hw/cxl/cxl-mailb
The following changes since commit f1d33f55c47dfdaf8daacd618588ad3ae4c452d1:
Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of
https://github.com/stsquad/qemu into staging (2022-10-06 07:11:56 -0400)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/f
Several hypervisor capabilities in KVM are target-specific. When exposed
to QEMU users as accelerator properties (i.e. -accel kvm,prop=value), they
should not be available for all targets.
Add a hook for targets to add their own properties to -accel kvm, for
now no such property is defined.
Sign
From: John Millikin
SunOS expects CD-ROM devices to have a block size of 512, and will
fail to mount or install using QEMU's default block size of 2048.
When initializing the SCSI device, allow the `physical_block_size'
block device option to override the default block size.
Signed-off-by: John
From: Richard Henderson
All callers pass s->base.pc_next and s->pc, which we can just as
well compute within the function. Adjust to use tcg_constant_i32
while we're at it.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <2022100114
From: Chenyi Qiang
Expose struct KVMState out of kvm-all.c so that the field of struct
KVMState can be accessed when defining target-specific accelerator
properties.
Signed-off-by: Chenyi Qiang
Message-Id: <20220929072014.20705-4-chenyi.qi...@intel.com>
Signed-off-by: Paolo Bonzini
---
accel/
From: Chenyi Qiang
There are cases that malicious virtual machine can cause CPU stuck (due
to event windows don't open up), e.g., infinite loop in microcode when
nested #AC (CVE-2015-5307). No event window means no event (NMI, SMI and
IRQ) can be delivered. It leads the CPU to be unavailable to h
From: Chenyi Qiang
For the direct triple faults, i.e. hardware detected and KVM morphed
to VM-Exit, KVM will never lose them. But for triple faults sythesized
by KVM, e.g. the RSM path, if KVM exits to userspace before the request
is serviced, userspace could migrate the VM and lose the triple fa
From: Richard Henderson
Instead of returning the new pc, which is present in
DisasContext, return true if an insn was translated.
This is false when we detect a page crossing and must
undo the insn under translation.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Reviewed
From: Richard Henderson
Replace sequences of gen_update_cc_op, gen_update_eip_next,
and gen_eob with the new is_jmp enumerator.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-10-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
tar
From: Richard Henderson
Like gen_update_cc_op, sync EIP before doing something
that could raise an exception. Replace all gen_jmp_im
that use s->base.pc_next.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-6-richard.hender...@linaro.org>
Signed-
From: Richard Henderson
The DisasContext member and the disas_insn local variable of
the same name are identical to DisasContextBase.pc_next.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-2-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonz
From: Richard Henderson
Create common routines for computing the length of the insn.
Use tcg_constant_i32 in the new function, while we're at it.
Reviewed-by: Paolo Bonzini
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-12-richard.hende
From: Richard Henderson
All callers pass s->base.pc_next - s->cs_base, which we can just
as well compute within the function. Note the special case of
EXCP_VSYSCALL in which s->cs_base wasn't subtracted, but cs_base
is always zero in 64-bit mode, when vsyscall is used.
Reviewed-by: Paolo Bonzin
From: Richard Henderson
Drop the unused dest argument to gen_jr().
Remove most of the calls to gen_jr, and use DISAS_JUMP.
Remove some unused loads of eip for lcall and ljmp.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-14-richard.hender...@lin
From: Richard Henderson
All callers pass s->base.pc_next and s->pc, which we can just
as well compute within the functions. Pull out common helpers
and reduce the amount of code under macros.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-13-ric
From: Richard Henderson
Replace lone calls to gen_eob() with the new enumerator.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-11-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 12 ++--
1 f
From: Richard Henderson
Create helpers for loading the address of the next insn.
Use tcg_constant_* in adjacent code where convenient.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-16-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
-
From: Richard Henderson
Add a few DISAS_TARGET_* aliases to reduce the number of
calls to gen_eob() and gen_eob_inhibit_irq(). So far,
only update i386_tr_translate_insn for exiting the block
because of single-step or previous inhibit irq.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Hend
From: Richard Henderson
Sync EIP before exiting a translation block.
Replace all gen_jmp_im that use s->pc.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-7-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translat
From: Richard Henderson
We can set is_jmp early, using only one if, and let that
be overwritten by gen_rep*'s calls to gen_jmp_tb.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-17-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
From: Richard Henderson
Set is_jmp properly in gen_movl_seg_T0, so that the callers
need to nothing special.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-9-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/transla
From: Richard Henderson
These functions are always passed aflag, so we might as well
read it from DisasContext directly. While we're at it, use
a common subroutine for these two functions.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-22-richar
From: Richard Henderson
Create a common helper for pc-relative branches. The jmp jb insn
was missing a mask for CODE32. In all cases the CODE64 check was
incorrectly placed, allowing PREFIX_DATA to truncate %rip to 16 bits.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-27-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu-param.h | 4 ++
target/i386/tcg/tcg-cpu.c | 8 ++-
target/i386/tcg/translate.c | 1
From: Alexander Graf
Intel CPUs starting with Haswell-E implement a new MSR called
MSR_CORE_THREAD_COUNT which exposes the number of threads and cores
inside of a package.
This MSR is used by XNU to populate internal data structures and not
implementing it prevents virtual machines with more tha
From: Richard Henderson
With gen_jmp_rel, we may chain to the next tb instead of merely
writing to eip and exiting. For repz, subtract cur_insn_len to
restart the current insn.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-19-richard.hender...@
From: Richard Henderson
Use i32 not int or tl for eip and cs arguments.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-15-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 +-
target/i386/tcg/seg_he
Linux can use FXSAVE to save/restore XMM registers even on 32-bit
systems. This requires some care in order to keep the FXSAVE area
aligned to 16 bytes; for this reason, get_sigframe is changed to
pass the offset into the FXSAVE area rather than the full frame
size.
Reviewed-by: Richard Henderson
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-20-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 57 -
1 file changed, 18 insertions(+), 39
From: Alexander Graf
The MSR_CORE_THREAD_COUNT MSR describes CPU package topology, such as number
of threads and cores for a given package. This is information that QEMU has
readily available and can provide through the new user space MSR deflection
interface.
This patch propagates the existing
From: Richard Henderson
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-24-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target
On Mon, 10 Oct 2022 15:29:43 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> To facilitate testing of event interrupt support add a QMP HMP command
> to reset the event logs and issue interrupts when the guest has enabled
> those interrupts.
Two things in here, so probably wants breaking
From: Richard Henderson
With gen_jmp_rel, we may chain between two translation blocks
which may only be separated because of TB size limits.
Reviewed-by: Paolo Bonzini
Signed-off-by: Richard Henderson
Message-Id: <20221001140935.465607-21-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonz
Recent versions of Linux moved the 32-bit fpstate towards the end of the
frame, so that the variable-sized xsave data does not overwrite the
(ABI-defined) extramask[] field. Follow suit in QEMU.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
linux-user/i386/signal.c | 11 +
Alyssa Ross writes:
> Alyssa Ross writes:
>
>> Linus Heckemann writes:
>>
>>> While it's unclear to me what git send-email actually does with the
>>> -v2 parameter (it is not documented, but also not rejected), it does
>>> not add a v2 tag to the email's subject, which is what led to the
>>> mi
Control VQ is the way net devices use to send changes to the device state, like
the number of active queues or its mac address.
QEMU needs to intercept this queue so it can track these changes and is able to
migrate the device. It can do it from 1576dbb5bbc4 ("vdpa: Add x-svq to
NetdevVhostVDPAOpt
The memory listener that thells the device how to convert GPA to qemu's
va is registered against CVQ vhost_vdpa. This series try to map the
memory listener translations to ASID 0, while it maps the CVQ ones to
ASID 1.
Let's tell the listener if it needs to register them on iova tree or
not.
Signe
From: Richard Henderson
These functions have only one caller, and the logic is more
obvious this way.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-23-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c |
From: Alexander Graf
KVM has grown support to deflect arbitrary MSRs to user space since
Linux 5.10. For now we don't expect to make a lot of use of this
feature, so let's expose it the easiest way possible: With up to 16
individually maskable MSRs.
This patch adds a kvm_filter_msr() function th
SVQ may run or not in a device depending on runtime conditions (for
example, if the device can move CVQ to its own group or not).
Allocate the resources unconditionally, and decide later if to use them
or not.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 33 +++-
Add support for saving/restoring extended save states when signals
are delivered. This allows using AVX, MPX or PKRU registers in
signal handlers.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
linux-user/i386/signal.c | 119 +--
target/i386
The stack used to visit the graph is implemented as a fixed-size array,
and the array is sized according to the maximum anticipated length of
a path on the graph. However, the worst case for a depth-first search
is to push all nodes on the graph, and in fact stack overflows have
been observed in t
From: Richard Henderson
Create a tcg global temp for this, and use it instead of explicit stores.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-25-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 13
CVQ can be shadowed two ways:
- Device has x-svq=on parameter (current way)
- The device can isolate CVQ in its own vq group
QEMU needs to check for the second condition dynamically, because CVQ
index is not known at initialization time. Since this is dynamic, the
CVQ isolation could vary with dif
On Tue, Oct 11, 2022 at 5:29 PM wrote:
>
> From: Marc-André Lureau
>
> As described in:
> https://learn.microsoft.com/en-us/visualstudio/debugger/how-to-set-a-thread-name-in-native-code?view=vs-2022
>
> SetThreadDescription() is available since Windows 10, version 1607 and
> in some versions only
From: Richard Henderson
Expand this function at each of its callers.
Signed-off-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Message-Id: <20221001140935.465607-26-richard.hender...@linaro.org>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 15 +--
1 file chang
On 30/09/2022 00.35, Michael Labiuk via wrote:
Move sending 'device_del' command to separate function.
Function can be used in case of addition action is needed to start
actual removing device after sending command.
Signed-off-by: Michael Labiuk
---
tests/qtest/device-plug-test.c | 15 ++-
Queued, thanks.
Paolo
* Zhenzhong Duan (zhenzhong.d...@intel.com) wrote:
Hi,
> Imagine a rare case, after a dirty page is sent to compression threads's
> ring, dirty bitmap sync trigger right away and mark the same page dirty
> again and sent. Then the new page may be overwriten by stale page in
> compression threads'
> On 11 Oct 2022, at 05:02, Ani Sinha wrote:
>
> On Mon, Oct 10, 2022 at 6:53 PM Miguel Luis wrote:
>>
>> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
>> specification adding the field "Hypervisor Vendor Identity" that was missing.
>>
>> This field's description
So the caller can choose which ASID is destined.
No need to update the batch functions as they will always be called from
memory listener updates at the moment. Memory listener updates will
always update ASID 0, as it's the passthrough ASID.
All vhost devices's ASID are 0 at this moment.
Signed-
On 30/09/2022 00.35, Michael Labiuk via wrote:
Configure pci bridge setting to plug pci device and unplug.
Signed-off-by: Michael Labiuk
---
tests/qtest/device-plug-test.c | 41 ++
1 file changed, 41 insertions(+)
Reviewed-by: Thomas Huth
In order to use the increased number of cpus, we need to bring smbios
tables in line with the SMBIOS 3.0 specification. This allows us to
introduce core_count2 which acts as a duplicate of core_count if we have
fewer cores than 256, and contains the actual core number per socket if
we have more.
c
On Mon, 10 Oct 2022 15:29:44 -0700
ira.we...@intel.com wrote:
> From: Ira Weiny
>
> Replace the stubbed out CXL Get/Set Event interrupt policy mailbox
> commands. Enable those commands to control interrupts for each of the
> event log types.
>
> Signed-off-by: Ira Weiny
A few trivial comments
Hi Paolo,
On Thu, Oct 6, 2022 at 11:03 AM Bin Meng wrote:
>
> Hi Paolo,
>
> On Wed, Sep 28, 2022 at 2:10 PM Bin Meng wrote:
> >
> > Hi Paolo,
> >
> > On Wed, Sep 21, 2022 at 9:02 AM Bin Meng wrote:
> > >
> > > On Wed, Sep 14, 2022 at 4:08 PM Bin Meng wrote:
> > > >
> > > > On Wed, Sep 7, 2022
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-4-jus...@redhat.com>
---
tests/data/acpi/q35/APIC.core-count2| 0
tests/data/acpi/q35/DSDT.core-count2| 0
tests/data/acpi/q35/FACP.core-count2| 0
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
4 files
Changes in the tables (for 275 cores):
FACP:
+ Use APIC Cluster Model (V4) : 1
APIC:
+[02Ch 0044 1]Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1]
Isolate control virtqueue in its own group, allowing to intercept control
commands but letting dataplane run totally passthrough to the guest.
Signed-off-by: Eugenio Pérez
---
v5:
* Fixing the not adding cvq buffers when x-svq=on is specified.
* Move vring state in vhost_vdpa_get_vring_group inst
This function used to trust in v->shadow_vqs != NULL to know if it must
start svq or not.
This is not going to be valid anymore, as qemu is going to allocate svq
unconditionally (but it will only start them conditionally).
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 4 ++--
1 file
Introduce the 64-bit entry point. Since we no longer have a total
number of structures, stop checking for the new ones at the EOF
structure (type 127).
Signed-off-by: Julia Suvorova
Reviewed-by: Igor Mammedov
Message-Id: <20220731162141.178443-3-jus...@redhat.com>
---
tests/qtest/bios-tables-te
While the test-build test happily run for mingw the test-mingw case
runs more of the packaging inline with what our CI does. It however
fails if we don't find both compilers and expects to be run on a
docker image with both.
Remove that distinction and make it work more like the other build
test s
Hi,
Consider this a hotfix testing/next series. I hadn't noticed the
update to build the BIOS's would trigger a lot of downloading for a
normal build. I've reverted one patch which stops that from happening
and we can revisit enabling this is a more sustainable way later.
Also we have updates for
The new test is run with a large number of cpus and checks if the
core_count field in smbios_cpu_test (structure type 4) is correct.
Choose q35 as it allows to run with -smp > 255.
Signed-off-by: Julia Suvorova
Message-Id: <20220731162141.178443-5-jus...@redhat.com>
---
tests/qtest/bios-tables-
On 30/09/2022 00.35, Michael Labiuk via wrote:
Signed-off-by: Michael Labiuk
---
tests/qtest/hd-geo-test.c | 97 +++
1 file changed, 97 insertions(+)
diff --git a/tests/qtest/hd-geo-test.c b/tests/qtest/hd-geo-test.c
index 61f4c24b81..278464c379 100644
---
On 2022-10-11 12:34:56 +0200, Paolo Bonzini wrote:
> Queued, thanks.
Thank you!
Venu
>
> Paolo
>
On 30/09/2022 00.35, Michael Labiuk via wrote:
Using g_autofree char* and g_strdup_printf(...) instead of ugly
snprintf on stack array.
Signed-off-by: Michael Labiuk
---
tests/qtest/drive_del-test.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/d
On 30/09/2022 00.35, Michael Labiuk via wrote:
Add pci bridge setting to test hotplug.
Duplicate tests for plugging scsi and virtio devices for q35 machine type.
Signed-off-by: Michael Labiuk
---
tests/qtest/hd-geo-test.c | 76 ++-
1 file changed, 75 inser
Convert another two dockerfiles to lcitool and update. I renamed the
helper because it is not Debian specific. We need an updated lcitool
for this to deal with the weirdness of a 32bit nsis tool for both 32
and 64 bit builds. As a result there are some minor whitespace and
re-order changes in a bun
The SMBIOS 3.0 specification provides the ability to reflect over
255 cores. The 64-bit entry point has been used for a while, but
structure type 4 has not been updated before, so the dmidecode output
looked like this (-smp 280):
Handle 0x0400, DMI type 4, 42 bytes
Processor Information
On 30/09/2022 00.35, Michael Labiuk via wrote:
Signed-off-by: Michael Labiuk
---
tests/qtest/drive_del-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/qtest/drive_del-test.c b/tests/qtest/drive_del-test.c
index 467e752b0d..44b9578801 100644
--- a/tests/qtest/d
On 11/10/2022 12.18, Michael Labiuk wrote:
I would like to ping a patch
Sorry, it took me a little bit longer to get back to this...
Anyway, patches look fine, and I've queued them now (with the typo fixed in
the first patch) to my testing-next branch:
https://gitlab.com/thuth/qemu/-/commi
On 30/09/2022 00.35, Michael Labiuk via wrote:
Configure pci bridge setting to test ivshmem on 'q35'.
Signed-off-by: Michael Labiuk
---
tests/qtest/ivshmem-test.c | 18 ++
1 file changed, 18 insertions(+)
Reviewed-by: Thomas Huth
On 30/09/2022 00.35, Michael Labiuk via wrote:
Moving common code to function.
Signed-off-by: Michael Labiuk
---
tests/qtest/hd-geo-test.c | 144 +++---
1 file changed, 57 insertions(+), 87 deletions(-)
Nice refactoring, nice diffstat!
Reviewed-by: Thomas H
On Tue, Oct 11, 2022 at 4:33 PM Miguel Luis wrote:
>
>
> > On 11 Oct 2022, at 05:02, Ani Sinha wrote:
> >
> > On Mon, Oct 10, 2022 at 6:53 PM Miguel Luis wrote:
> >>
> >> Update the Fixed ACPI Description Table (FADT) to revision 6.0 of the ACPI
> >> specification adding the field "Hypervisor Ve
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