Re: [PATCH] docs/devel: remove incorrect claim about git send-email

Linus Heckemann writes: > While it's unclear to me what git send-email actually does with the > -v2 parameter (it is not documented, but also not rejected), it does > not add a v2 tag to the email's subject, which is what led to the > mishap in [1]. > > [1]: https://lists.nongnu.org/archive/html/

Re: [PATCH] docs/devel: remove incorrect claim about git send-email

Alyssa Ross writes: > Linus Heckemann writes: > >> While it's unclear to me what git send-email actually does with the >> -v2 parameter (it is not documented, but also not rejected), it does >> not add a v2 tag to the email's subject, which is what led to the >> mishap in [1]. >> >> [1]: https:/

[RISU PATCH 3/5] loongarch: Implement risugen module

Signed-off-by: Song Gao --- risugen_loongarch64.pm | 502 + 1 file changed, 502 insertions(+) create mode 100644 risugen_loongarch64.pm diff --git a/risugen_loongarch64.pm b/risugen_loongarch64.pm new file mode 100644 index 000..693fb71 --- /dev/null

[RISU PATCH 2/5] loongarch: Add LoongArch basic test support

This patch adds LoongArch server, client support, and basic test file. Signed-off-by: Song Gao --- risu_loongarch64.c | 50 ++ risu_reginfo_loongarch64.c | 183 + risu_reginfo_loongarch64.h | 25 + test_loongarch64.s | 92 +++

[RISU PATCH 0/5] Add LoongArch architectures support

hi, This series adds LoongArch architectures support, we had tested two mode: 1. LoongArch host server + LoongArch host client; 2. LoongArch host server + qemu client. You can find all LoongArch instructions at [1]. This series not contains all LoongArch instructions, such as pcadd, syscalls,

[RISU PATCH 5/5] loongarch: Add block 'safefloat' and nanbox_s()

Some LoongArch instructions don't care the high 32bit, so use nanbox_s() set the high 32bit 0x. Signed-off-by: Song Gao --- loongarch64.risu | 119 +++-- risugen| 2 +- risugen_loongarch64.pm | 30 +++ 3 files changed,

[RISU PATCH 4/5] loongarch: Add risufile with loongarch instructions

Signed-off-by: Song Gao --- loongarch64.risu | 573 +++ 1 file changed, 573 insertions(+) create mode 100644 loongarch64.risu diff --git a/loongarch64.risu b/loongarch64.risu new file mode 100644 index 000..d059811 --- /dev/null +++ b/loongarch64.

[RISU PATCH 1/5] risu: Use alternate stack

We can use alternate stack, so that we can use sp register as intput/ouput register. I had tested aarch64/LoongArch architecture. Signed-off-by: Song Gao --- risu.c | 16 +++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/risu.c b/risu.c index 1c096a8..714074e 100644

[PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_bit.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc index 9337714ec4..33e94878fd 100644 --- a/target/loongarch/ins

[PATCH 4/5] target/loongarch: flogb_{s/d} add set float_flag_divbyzero

if fj ==0 or fj == INT32_MIN/INT64_MIN, LoongArch host set fcsr cause exception FP_DIV0, So we need set exception flags float_flagdivbyzero if fj ==0. Signed-off-by: Song Gao --- target/loongarch/fpu_helper.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/target/loongarch/f

[PATCH 1/5] target/loongarch: ftint_xxx insns set the result high 32bit 0xffffffff

we just set high 32bit 0x as the other float instructions do. Signed-off-by: Song Gao --- target/loongarch/fpu_helper.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c index 4b9637210a..1

Re: [PATCH] RISC-V: Add support for Ztso

On 9/16/22 14:52, Palmer Dabbelt wrote: Though, honestly, I've had patches to add the required barriers sitting around for the last few releases, to better support things like x86 on aarch64.  I should just finish that up. I can just do that for the RISC-V TSO support?  Like the cover letter

[PATCH 0/5] Fix some bugs

hi, This series fix some bugs find from RISU test. Thanks. Song Gao Song Gao (5): target/loongarch: ftint_xxx insns set the result high 32bit 0x target/loongarch: bstrins.w need set dest register EXT_SIGN target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags target/loongarch:

[PATCH 3/5] target/loongarch: Fix fnm{sub/add}_{s/d} set wrong flags

Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_farith.c.inc | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc index 65ad2ffab8..7bb3f41aee 100644 --- a/ta

[PATCH v2] RISC-V: Add support for Ztso

The Ztso extension was recently frozen, this adds it as a CPU property and adds various fences throughout the port in order to allow TSO targets to function on weaker hosts. We need no fences for AMOs as they're already SC, the placess we need barriers are described. Signed-off-by: Palmer Dabbelt

[PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

div.d, div.du, div,w, div.wu, the LoongArch host if x/0 the result is 0. So we set the divisor to 1 and the dividend to 0. Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_arith.c.inc | 34 +++ 1 file changed, 27 insertions(+), 7 deletions(-) diff --git a/target/lo

Re: [PATCH] RISC-V: Add support for Ztso

On Sat, 17 Sep 2022 01:02:46 PDT (-0700), Richard Henderson wrote: On 9/16/22 14:52, Palmer Dabbelt wrote: Though, honestly, I've had patches to add the required barriers sitting around for the last few releases, to better support things like x86 on aarch64.  I should just finish that up. I

Re: [RFC PATCH 3/4] hw/intc/gic: use MxTxAttrs to divine accessing CPU

On 9/16/22 17:28, Alex Bennée wrote: I pondered boolean but wasn't sure if that would blow up the size of MemTxAttrs so went for the bitfield. You can use bool with a bitfield. Though Phil's suggestion of .requestor_type has merit. That depends on what comes of Peter's hw modeling suggestion

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

On 2022/9/17 15:59, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/insn_trans/trans_bit.c.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc index 9337714ec4..33

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

On 2022/9/17 15:59, Song Gao wrote: div.d, div.du, div,w, div.wu, the LoongArch host if x/0 the result is 0. The message has a typo: "div,w" => "div.w" Also I don't know why we need to do this, since the manual say: "When the divisor is 0, the result can be any value". So we set the div

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

在 2022/9/17 下午4:59, Qi Hu 写道: On 2022/9/17 15:59, Song Gao wrote: div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result is 0. The message has a typo: "div,w" => "div.w" Also I don't know why we need to do this, since the manual say: "When the divisor is 0, the result can be

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

在 2022/9/17 下午4:41, Qi Hu 写道: On 2022/9/17 15:59, Song Gao wrote: Signed-off-by: Song Gao ---   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--   1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/tran

Re: [PATCH 5/5] target/loongarch: div if x/0 set dividend to 0

On 9/17/22 11:12, gaosong wrote: 在 2022/9/17 下午4:59, Qi Hu 写道: On 2022/9/17 15:59, Song Gao wrote: div.d, div.du, div,w, div.wu, the LoongArch host if x/0  the result is 0. The message has a typo: "div,w" => "div.w" Also I don't know why we need to do this, since the manual say: "When the

Re: [PATCH 2/5] target/loongarch: bstrins.w need set dest register EXT_SIGN

On 2022/9/17 17:16, gaosong wrote: 在 2022/9/17 下午4:41, Qi Hu 写道: On 2022/9/17 15:59, Song Gao wrote: Signed-off-by: Song Gao ---   target/loongarch/insn_trans/trans_bit.c.inc | 4 ++--   1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/loongarch/insn_trans/trans_bit.c.in

[PATCH 0/4] target/m68k: MacOS supervisor/user mode switch fixes

This series fixes a couple of bugs that were discovered when trying to boot MacOS on my github q800 branch with virtual memory enabled. Patch 1 renames M68K_FEATURE_M68000 to M68K_FEATURE_M68K in order to clarify that this feature indicates any Motorola 68K CPU rather than the 68000 specifically [

[PATCH 1/4] target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K

The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constants which define the features available for s

[PATCH 3/4] target/m68k: use M68K_FEATURE_MOVEFROMSR_PRIV feature for move_from_sr privilege check

Now that M68K_FEATURE_M68000 has been renamed to M68K_FEATURE_M68K it is easier to see that the privilege exception check is wrong: it is currently only generated for ColdFire CPUs when in fact it should also be generated for Motorola CPUs from the 68010 onwards. Introduce a new M68K_FEATURE_MOV

[PATCH 2/4] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t

There are already 32 feature bits in use, so change the size of the m68k CPU features to uint64_t (allong with the associated m68k_feature() functions) to allow up to 64 feature bits to be used. Signed-off-by: Mark Cave-Ayland --- target/m68k/cpu.c | 4 ++-- target/m68k/cpu.h | 6 +++--- 2 files

[PATCH 4/4] target/m68k: always call gen_exit_tb() after writes to SR

Any write to SR can change the security state so always call gen_exit_tb() when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Signed-off-by: Mark Cave-Ayland --- target/m68k/translate.c | 4 1 file changed, 4

[PATCH] Remove unused MAX_IDE_BUS define

Several machines have an unused MAX_IDE_BUS define. Remove it from these machines that don't need it. Signed-off-by: BALATON Zoltan --- hw/alpha/dp264.c| 2 -- hw/hppa/machine.c | 2 -- hw/mips/fuloong2e.c | 1 - hw/mips/malta.c | 2 -- hw/ppc/prep.c | 2 -- hw/sparc64/sun4u.c

Re: [PATCH 2/4] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t

On Sat, 17 Sep 2022, Mark Cave-Ayland wrote: There are already 32 feature bits in use, so change the size of the m68k CPU features to uint64_t (allong with the associated m68k_feature() functions) to allow up to 64 feature bits to be used. Signed-off-by: Mark Cave-Ayland --- target/m68k/cpu.c |

[PATCH 0/2] audio: prevent a class of guest-triggered aborts

The issues with guest-triggered aborts started with commit ab32b78cd1 "audio: Simplify audio_bug() removing old code" which introduced an abort() in function audio_bug(). The abort() was there before, but it was only compiled in for debugging purposes. After this commit issue https://bugs.laun

[PATCH 1/2] Revert "audio: Log context for audio bug"

This reverts commit 8e30d39bade3010387177ca23dbc2244352ed4a3. Revert commit 8e30d39bad "audio: Log context for audio bug" to make error propagation work again. Signed-off-by: Volker Rümelin --- audio/audio.c | 25 + audio/audio_template.h | 27 +++---

[PATCH 2/2] audio: remove abort() in audio_bug()

Commit ab32b78cd1 "audio: Simplify audio_bug() removing old code" introduced abort() in audio_bug() for regular builds. audio_bug() was never meant to abort QEMU for the following reasons. - There's code in audio_bug() that expects audio_bug() gets called more than once with error condition

[PATCH] hw/display: load the correct ROM file for isa-vga device

Apparently we didn't load the correct ROM file when using the isa-vga device, which resulted in a display waiting to be initialized by a guest OS kernel. With this fix, SeaBIOS is able to print vital data to a text mode console during boot, which is useful in case of failing to continue booting. S

Re: [PATCH] hw/display: load the correct ROM file for isa-vga device

On 9/17/22 17:06, Liav Albani wrote: Apparently we didn't load the correct ROM file when using the isa-vga device, which resulted in a display waiting to be initialized by a guest OS kernel. With this fix, SeaBIOS is able to print vital data to a text mode console during boot, which is useful i

Re: [PULL 00/12] linux-user patches

The close_range(2) man page says: close_range() first appeared in Linux 5.9. Library support was added in glibc in version 2.34. The qemu-user GitLab CI jobs are failing. For example, see https://gitlab.com/qemu-project/qemu/-/jobs/3043629417: ../linux-user/syscall.c:8734:26: error: implicit dec

[PATCH v2] hw/display: load the correct ROM file for isa-vga device

Apparently QEMU didn't load the correct ROM file when using the isa-vga device on my development machine, which resulted in a display waiting to be initialized by a guest OS kernel. With this fix, SeaBIOS is able to print vital data to a text mode console during boot, which is useful in case of fai

Re: [PATCH v2] hw/display: load the correct ROM file for isa-vga device

On 9/17/22 17:32, Liav Albani wrote: diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 388e0db6e4..6af94a4a0a 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -29,7 +29,7 @@ blobs = [ 'bios-microvm.bin', 'qboot.rom', 'sgabios.bin', - 'vgabios.bin', + 'vgabio

Re: [PATCH v2] hw/display: load the correct ROM file for isa-vga device

On 9/17/22 17:40, Liav Albani wrote: On 9/17/22 17:32, Liav Albani wrote: diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 388e0db6e4..6af94a4a0a 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -29,7 +29,7 @@ blobs = [     'bios-microvm.bin',     'qboot.rom',     'sg

Re: [PATCH v2] hw/display: load the correct ROM file for isa-vga device

+David On 17/9/22 17:06, Liav Albani wrote: On 9/17/22 17:40, Liav Albani wrote: On 9/17/22 17:32, Liav Albani wrote: diff --git a/pc-bios/meson.build b/pc-bios/meson.build index 388e0db6e4..6af94a4a0a 100644 --- a/pc-bios/meson.build +++ b/pc-bios/meson.build @@ -29,7 +29,7 @@ blobs = [    

Re: [PULL 00/12] linux-user patches

On 17/9/22 16:26, Stefan Hajnoczi wrote: The close_range(2) man page says: close_range() first appeared in Linux 5.9. Library support was added in glibc in version 2.34. The qemu-user GitLab CI jobs are failing. For example, see https://gitlab.com/qemu-project/qemu/-/jobs/3043629417: ../linux-

Re: [PULL 00/12] linux-user patches

On Sat, 17 Sept 2022 at 15:31, Philippe Mathieu-Daudé wrote: > > On 17/9/22 16:26, Stefan Hajnoczi wrote: > > The close_range(2) man page says: > > close_range() first appeared in Linux 5.9. Library support was added > > in glibc in version 2.34. > > > > The qemu-user GitLab CI jobs are failing.

Re: [PULL 00/11] semihosting patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v9 1/7] include: add zoned device structs

On Thu, Sep 15, 2022 at 06:06:38PM +0800, Sam Li wrote: > Eric Blake 于2022年9月15日周四 16:05写道： > > > > On Sat, Sep 10, 2022 at 01:27:53PM +0800, Sam Li wrote: > > > Signed-off-by: Sam Li > > > Reviewed-by: Stefan Hajnoczi > > > Reviewed-by: Damien Le Moal > > > --- > > > include/block/block-commo

Re: [PATCH v9 5/7] config: add check to block layer

On Sat, Sep 10, 2022 at 01:27:57PM +0800, Sam Li wrote: > diff --git a/block/file-posix.c b/block/file-posix.c > index 4edfa25d04..354de22860 100644 > --- a/block/file-posix.c > +++ b/block/file-posix.c > @@ -779,6 +779,20 @@ static int raw_open_common(BlockDriverState *bs, QDict > *options, >

Re: [PULL 00/20] target-arm.next patch queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v9 3/7] block: add block layer APIs resembling Linux ZonedBlockDevice ioctls

On Sat, Sep 10, 2022 at 01:27:55PM +0800, Sam Li wrote: > Add a new zoned_host_device BlockDriver. The zoned_host_device option > accepts only zoned host block devices. By adding zone management > operations in this new BlockDriver, users can use the new block > layer APIs including Report Zone and

Re: [PULL 0/3] hmp queue

Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/7.2 for any user-visible changes. signature.asc Description: PGP signature

Re: [PATCH v2 07/11] acpi/tests/bits: add python test that exercizes QEMU bios tables using biosbits

On Fri, Sep 16, 2022 at 09:30:42PM +0530, Ani Sinha wrote: > On Thu, Jul 28, 2022 at 12:08 AM Ani Sinha wrote: > > > > > > > > On Mon, 25 Jul 2022, Ani Sinha wrote: > > > > > > > > > > > On Sat, 16 Jul 2022, Michael S. Tsirkin wrote: > > > > > > > On Sat, Jul 16, 2022 at 12:06:00PM +0530, Ani Sinh

Re: [PATCH] Remove unused MAX_IDE_BUS define

On 9/17/22 13:51, BALATON Zoltan wrote: Several machines have an unused MAX_IDE_BUS define. Remove it from these machines that don't need it. Signed-off-by: BALATON Zoltan --- hw/alpha/dp264.c| 2 -- hw/hppa/machine.c | 2 -- hw/mips/fuloong2e.c | 1 - hw/mips/malta.c | 2 -- hw/

Re: [PATCH] Remove unused MAX_IDE_BUS define

On 17/9/22 13:51, BALATON Zoltan wrote: Several machines have an unused MAX_IDE_BUS define. Remove it from these machines that don't need it. Signed-off-by: BALATON Zoltan --- hw/alpha/dp264.c| 2 -- hw/hppa/machine.c | 2 -- hw/mips/fuloong2e.c | 1 - hw/mips/malta.c | 2 -- hw

Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly

On 14/9/22 12:11, Alistair Francis via wrote: Instead of using our properties to set a config value which then might be used to set the resetvec (depending on your timing), let's instead just set the resetvec directly in the env struct. This allows us to set the reset vec from the command line w

Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property

On 14/9/22 12:11, Alistair Francis via wrote: On the OpenTitan hardware the resetvec is fixed at the start of ROM. In QEMU we don't run the ROM code and instead just jump to the next stage. This means we need to be a little more flexible about what the resetvec is. This patch allows us to set th

Re: [PATCH 01/10] mac_newworld: Drop some variables

On 17/9/22 01:07, BALATON Zoltan wrote: Values not used frequently enough may not worth putting in a local variable, especially with names almost as long as the original value because that does not improve readability, to the contrary it makes it harder to see what value is used. Drop a few such

Re: [PATCH 02/10] mac_oldworld: Drop some more variables

On 17/9/22 01:07, BALATON Zoltan wrote: Drop some more local variables additionally to commit b8df32555ce5 to match clean ups done to mac_newwold in previous patch. Signed-off-by: BALATON Zoltan --- hw/ppc/mac_oldworld.c | 43 +-- 1 file changed, 21 in

Re: [PATCH 05/10] mac_{old|new}world: Reduce number of QOM casts

On 17/9/22 01:07, BALATON Zoltan wrote: By storing the device pointers in a variable with the right type the number of QOM casts can be reduced which also makes the code more readable. Signed-off-by: BALATON Zoltan --- hw/ppc/mac_newworld.c | 60 --- h

Re: [PATCH 09/10] hw/ppc/mac.h: Move PROM and KERNEL defines to board code

On 17/9/22 01:07, BALATON Zoltan wrote: The PROM_FILENAME and KERNEL_* defines are used by mac_oldworld and mac_newworld but they don't have to be identical so these could be moved to the individual boards. The NVRAM_SIZE define is not used so it can be dropped. This further reduces the mac.h hea

Re: [PATCH 07/10] hw/ppc/mac.h: Move macio specific atuff out from shared header

On 17/9/22 01:07, BALATON Zoltan wrote: Move the parts specific to and only used by macio out from the shared mac.h into macio.c where they better belong. Signed-off-by: BALATON Zoltan --- hw/misc/macio/macio.c | 26 -- hw/ppc/mac.h | 23 -

Re: [PATCH 07/10] hw/ppc/mac.h: Move macio specific atuff out from shared header

On 17/9/22 01:07, BALATON Zoltan wrote: Move the parts specific to and only used by macio out from the shared mac.h into macio.c where they better belong. Signed-off-by: BALATON Zoltan --- hw/misc/macio/macio.c | 26 -- hw/ppc/mac.h | 23 -

Re: [PATCH 1/7] scripts/nsis.py: Drop the unnecessary path separator

On 8/9/22 15:28, Bin Meng wrote: From: Bin Meng There is no need to append a path separator to the destination directory that is passed to "make install". Signed-off-by: Bin Meng --- scripts/nsis.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Philippe Mathieu-Daud

Re: [PATCH 2/7] scripts/nsis.py: Fix destination directory name when invoked on Windows

On 8/9/22 15:28, Bin Meng wrote: From: Bin Meng "make installer" on Windows fails with the following message: Traceback (most recent call last): File "G:\msys64\home\foo\git\qemu\scripts\nsis.py", line 89, in main() File "G:\msys64\home\foo\git\qemu\scripts\nsis.py", line

Re: [PATCH 4/7] .gitlab-ci.d/windows.yml: Drop the sed processing in the 64-bit build

On 8/9/22 15:28, Bin Meng wrote: From: Bin Meng The sed processing of build/config-host.mak seems to be no longer needed, and there is no such in the 32-bit build too. Drop it. Signed-off-by: Bin Meng --- .gitlab-ci.d/windows.yml | 1 - 1 file changed, 1 deletion(-) Reviewed-by: Philipp

Re: [PATCH 7/7] .gitlab-ci.d/windows.yml: Test 'make installer' in the CI

On 8/9/22 15:28, Bin Meng wrote: From: Bin Meng Now that we have supported packaging DLLs automatically, let's add the 'make installer' in the CI and publish the generated installer file as an artifact. Increase the job timeout to 90 minutes to accommodate to it. Signed-off-by: Bin Meng ---

Re: [PATCH 5/7] block/nfs: Fix 32-bit Windows build

On 8/9/22 15:28, Bin Meng wrote: From: Bin Meng libnfs.h declares nfs_fstat() as the following for win32: int nfs_fstat(struct nfs_context *nfs, struct nfsfh *nfsfh, struct __stat64 *st); The 'st' parameter should be of type 'struct __stat64'. The codes happen to build suc

Re: [PATCH] vfio/common: Fix vfio_iommu_type1_info use after free

On 15/9/22 19:18, Alex Williamson wrote: On error, vfio_get_iommu_info() frees and clears *info, but vfio_connect_container() continues to use the pointer regardless of the return value. Restructure the code such that a failure of this function triggers an error and clean up the remainder of the

Re: [PATCH v2 2/4] scripts/ci/setup: Fix libxen requirements

On 14/9/22 14:41, Lucas Mateus Castro(alqotel) wrote: From: "Lucas Mateus Castro (alqotel)" XEN hypervisor is only available in ARM and x86, but the yaml only checked if the architecture is different from s390x, changed it to a more accurate test. Tested this change on a Ubuntu 20.04 ppc64le.

Re: [PATCH v2 3/4] scripts/ci/setup: spice-server only on x86 aarch64

On 14/9/22 14:41, Lucas Mateus Castro(alqotel) wrote: From: "Lucas Mateus Castro (alqotel)" Changed build-environment.yml to only install spice-server on x86_64 and aarch64 as this package is only available on those architectures. Signed-off-by: Lucas Mateus Castro (alqotel) --- scripts/ci/

Re: [PATCH v3 1/1] monitor/hmp: print trace as option in help for log command

Hi Markus, On 2/9/22 14:24, Markus Armbruster wrote: Dongli Zhang writes: The below is printed when printing help information in qemu-system-x86_64 command line, and when CONFIG_TRACE_LOG is enabled: $ qemu-system-x86_64 -d help ... ... trace:PATTERN enable tra

Re: [PATCH v4 06/21] ppc4xx_sdram: Move size check to ppc4xx_sdram_init()

On 14/9/22 13:34, BALATON Zoltan wrote: Instead of checking if memory size is valid in board code move this check to ppc4xx_sdram_init() as this is a restriction imposed by the SDRAM controller. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc405.h | 2 -- hw/ppc/ppc405_boards.c | 10 -

Re: [PATCH v4 08/21] ppc4xx_sdram: Drop extra zeros for readability

On 14/9/22 13:34, BALATON Zoltan wrote: Constants that are written zero padded for no good reason are hard to read, it's easier to see what is meant if it's just 0 or 1 instead. It would be nice to be able to use the single quote separator for integer literals, but they are only part of C++14,

Re: [PATCH v4 09/21] ppc440_sdram: Split off map/unmap of sdram banks for later reuse

On 14/9/22 13:34, BALATON Zoltan wrote: Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 5db59d1190..01184e717b 100644 --- a/hw/ppc/ppc440_uc

Re: [PATCH v4 13/21] ppc4xx_sdram: Rename functions to prevent name clashes

On 14/9/22 13:34, BALATON Zoltan wrote: Rename functions to avoid name clashes when moving the DDR2 controller model currently called ppc440_sdram to ppc4xx_devs. This also more clearly shows which function belongs to which model. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440_uc.c | 69 ++

Re: [PATCH v4 21/21] ppc4xx_sdram: Add errp parameter to ppc4xx_sdram_banks()

On 14/9/22 13:34, BALATON Zoltan wrote: Do not exit from ppc4xx_sdram_banks() but report error via an errp parameter instead. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc4xx_sdram.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) Reviewed-by: Philippe Ma

Re: [PATCH v4 14/21] ppc440_sdram: Move RAM size check to ppc440_sdram_init

On 14/9/22 13:34, BALATON Zoltan wrote: Move the check for valid memory sizes from board to sdram controller init. Board now only checks for additional restrictions imposed by firmware then sdram init checks for valid sizes for SoC. Signed-off-by: BALATON Zoltan --- hw/ppc/ppc440.h| 4 ++

Re: [PATCH 1/4] target/m68k: rename M68K_FEATURE_M68000 to M68K_FEATURE_M68K

On 17/9/22 13:25, Mark Cave-Ayland wrote: The M68K_FEATURE_M68000 feature is misleading in that its name suggests the feature is defined just for Motorola 68000 CPUs, whilst in fact it is defined for all Motorola 680X0 CPUs. In order to avoid confusion with the other M68K_FEATURE_M680X0 constan

Re: [PATCH 2/4] target/m68k: increase size of m68k CPU features from uint32_t to uint64_t

On 17/9/22 14:09, BALATON Zoltan wrote: On Sat, 17 Sep 2022, Mark Cave-Ayland wrote: There are already 32 feature bits in use, so change the size of the m68k CPU features to uint64_t (allong with the associated m68k_feature() functions) to allow up to 64 feature bits to be used. Signed-off-by:

Re: [PATCH 4/4] target/m68k: always call gen_exit_tb() after writes to SR

On 17/9/22 13:25, Mark Cave-Ayland wrote: Any write to SR can change the security state so always call gen_exit_tb() when this occurs. In particular MacOS makes use of andiw/oriw in a few places to handle the switch between user and supervisor mode. Shouldn't be safer to add the gen_exit_tb() c