On Sat, 17 Sep 2022 01:02:46 PDT (-0700), Richard Henderson wrote:
On 9/16/22 14:52, Palmer Dabbelt wrote:
Though, honestly, I've had patches to add the required barriers sitting around
for the
last few releases, to better support things like x86 on aarch64. I should just
finish
that up.
I can just do that for the RISC-V TSO support? Like the cover letter says that
was my
first thought, it's only when I found the comment saying not to do it that I
went this way.
My patches inject the barriers automatically by the tcg optimizer, rather than
by hand,
which is what the comment was trying to discourage. Last version was
https://lore.kernel.org/qemu-devel/20210316220735.2048137-1-richard.hender...@linaro.org/
Thanks, I get it now.
