Le 12/08/2022 à 06:16, Thomas Huth a écrit :
On 11/08/2022 23.38, Pierre Muller wrote:
I am using qemu to check code generated by Free Pascal compiler
for various CPUs.
Recently, this allowed me to find out that Free Pascal was generating
wrong instructions, leading to SIGBUS errors
On Fri, Aug 12, 2022 at 10:54 AM Wilfred Mallawa
wrote:
>
> From: Wilfred Mallawa
>
> The following patch updates opentitan to match the new configuration,
> as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
>
> Note: with this patch we now skip the usage of the opentitan
> `boot
Am 12.08.22 um 01:34 schrieb Philippe Mathieu-Daudé:
Cc'ing qemu-windows@ team
On 10/8/22 23:42, Peter Butler wrote:
In x64 win10 I today I d/l QEMU into new directory. Then navigated to
that dir and…
qemu-system-aarch64 -boot d -cdrom
f:\Downloads\debian-11.4.0-arm64-netinst.iso -m 2048
This is the v7 of this series which tries to implement the
fd-based KVM
guest private memory. The patches are based on latest kvm/queue
branch
commit:
b9b71f43683a (kvm/queue) KVM: x86/mmu: Buffer nested MMU
split_desc_cache only by default capacity
Introduction
In general
On Thu, 11 Aug 2022 23:05:52 -0300
Murilo Opsfelder Araújo wrote:
> On 8/11/22 11:02, Daniel P. Berrangé wrote:
> [...]
> >>> Hmm, I was hoping you could just use SIGKILL to guarantee that this
> >>> gets killed off. Is SIGKILL delivered too soon to allow for the
> >>> main QEMU process to have
Signed-off-by: Stefan Weil
---
docs/about/deprecated.rst | 2 +-
docs/specs/acpi_erst.rst| 4 ++--
docs/system/devices/canokey.rst | 8
docs/system/devices/cxl.rst | 12 ++--
4 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/docs/about/deprecat
On Thu, 11 Aug 2022 at 22:26, Pierre Muller wrote:
>But as I use machines on which I am not admin,
> I needed to compile capstone locally, install it inside my home dir,
> and export PKG_CONFIG_PATH to allow the meson configuration
> to correctly detect this local installation...
Yes, like al
Hi list,
When I did some tests in my virtual domain with live-attached virtio deivces, I
got a coredump file of Qemu.
The error print from qemu is "kvm_mem_ioeventfd_add: error adding ioeventfd:
File exists (17)".
And the call trace in the coredump file displays as below:
#0 0x89acecc8
On Fri, Aug 12, 2022 at 09:56:42AM +0200, Stefan Weil wrote:
> diff --git a/docs/system/devices/canokey.rst b/docs/system/devices/canokey.rst
> index c2c58ae3e7..cfa6186e48 100644
> --- a/docs/system/devices/canokey.rst
> +++ b/docs/system/devices/canokey.rst
> @@ -28,9 +28,9 @@ With the same softw
On 12/08/22 12:48, Gupta, Pankaj wrote:
>
>>
>> However, fallocate() preallocates full guest memory before starting the
>> guest.
>> With this behaviour guest memory is *not* demand pinned. Is there a way
>> to
>> prevent fallocate() from reserving full guest memory?
>
1. Add some information about how to boot the LoongArch virt
machine by uefi bios and linux kernel and how to access the
source code or binary file.
2. Move the explanation of LoongArch system emulation in the
target/loongarch/README to docs/system/loongarch/loongson3.rst
Signed-off-by: Xiaojuan
On Fri, Aug 12, 2022 at 02:21:40AM +, Wilfred Mallawa wrote:
> On Thu, 2022-08-11 at 16:23 +0200, Andrew Jones wrote:
> > On Thu, Aug 11, 2022 at 09:02:00AM +1000, Wilfred Mallawa wrote:
> > > From: Wilfred Mallawa
> > >
> > > This patch addresses the coverity issues specified in [1],
> > > a
I've added some more relevant mailing lists to the cc.
On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > I noticed that we starting to get many errors like this:
> >
> > qemu-system-aarch64: Failed to retrieve host CPU fe
On 2022/8/12 下午5:19, Xiaojuan Yang wrote:
1. Add some information about how to boot the LoongArch virt
machine by uefi bios and linux kernel and how to access the
source code or binary file.
2. Move the explanation of LoongArch system emulation in the
target/loongarch/README to docs/system/loon
However, fallocate() preallocates full guest memory before starting the guest.
With this behaviour guest memory is *not* demand pinned. Is there a way to
prevent fallocate() from reserving full guest memory?
Isn't the pinning being handled by the corresponding host memory backend with mmu >
On Sun, Jul 31, 2022 at 06:21:36PM +0200, Julia Suvorova wrote:
> The SMBIOS 3.0 specification provides the ability to reflect over
> 255 cores. The 64-bit entry point has been used for a while, but
> structure type 4 has not been updated before, so the dmidecode output
> looked like this (-smp 280
On Fri, 12 Aug 2022 at 08:59, Stefan Weil via wrote:
>
> Signed-off-by: Stefan Weil
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, 12 Aug 2022 at 08:59, Stefan Weil via wrote:
>
> Signed-off-by: Stefan Weil
> ---
> docs/about/deprecated.rst | 2 +-
> docs/specs/acpi_erst.rst| 4 ++--
> docs/system/devices/canokey.rst | 8
> docs/system/devices/cxl.rst | 12 ++--
> 4 files change
On Wed, 10 Aug 2022 at 13:20, wrote:
>
> From: Marc-André Lureau
>
> ../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
> ../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output
> may be truncated writing between 1 and 10 bytes into a region of size 6
On Fri, 12 Aug 2022 at 03:20, Zenghui Yu wrote:
>
> With the introduction of the new TCG GICv4, build_madt() is badly broken
> as we do not present any GIC Redistributor structure in MADT for GICv4
> guests, so that they have no idea about where the Redistributor
> register frames are. This fixes
On Tue, 9 Aug 2022 at 19:57, Ben Dooks wrote:
>
> Add a helper for qemu_fdt_setprop_strings() to take a set of strings
> to put into a device-tree, which removes several open-coded methods
> such as setting an char arr[] = {..} or setting char val[] = "str\0str2";
>
> This is for hw/arm, hw/mips a
From: Vitaly Buka
aarch64 stores MTE tags in target_date, and they should be reset by
MADV_DONTNEED.
Signed-off-by: Vitaly Buka
Reviewed-by: Richard Henderson
Message-Id: <20220711220028.2467290-1-vitalyb...@google.com>
[lv: fix code style issues]
Signed-off-by: Laurent Vivier
---
accel/tcg/
On Tue, 9 Aug 2022 at 23:22, Philippe Mathieu-Daudé via
wrote:
>
> Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot
> to move the macOS dyld(3) include, resulting in the following
> error (when building with Homebrew GCC on macOS Monterey 12.4):
>
> [313/1197] Compiling C object li
r/qemu.git
tags/linux-user-for-7.1-pull-request
for you to fetch changes up to dbbf89751b14aa5d281bad3af273e9ffaae82262:
linux-user/aarch64: Reset target data on MADV_DONTNEED (2022-08-11 11:34:17
+0200)
Pull request linux-use
socket_get_fd() have much the same codes as monitor_fd_param(),
so qemu_get_fd() is introduced to implement the common logic.
now socket_get_fd() and monitor_fd_param() directly call this
function.
Signed-off-by: Guoyi Tu
---
include/qemu/osdep.h | 1 +
monitor/misc.c | 21 +-
The intention of the Zoned Namespace Command Set Specification was
never to make an automatic zone transition optional.
Excerpt from the nvmexpress.org zns mailing list:
"""
A question came up internally on the differences between ZNS and ZAC/ZBC
that asked about when a controller should transitio
On Thu, Aug 11, 2022 at 01:41:04PM -0700, Furquan Shaikh wrote:
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels -
On Thu, 11 Aug 2022 at 21:47, Furquan Shaikh wrote:
>
> Unlike ARM, RISC-V does not define a separate breakpoint type for
> semihosting. Instead, it is entirely ABI. Thus, we need an option
> to allow users to configure what the ebreak behavior should be for
> different privilege levels - M, S, U,
On 8/12/22 04:26, Claudio Imbrenda wrote:
On Thu, 11 Aug 2022 23:05:52 -0300
Murilo Opsfelder Araújo wrote:
On 8/11/22 11:02, Daniel P. Berrangé wrote:
[...]
Hmm, I was hoping you could just use SIGKILL to guarantee that this
gets killed off. Is SIGKILL delivered too soon to allow for the
ma
From: Guoyi Tu
qemu_socketpair() will create a pair of connected sockets
with FD_CLOEXEC set
Signed-off-by: Guoyi Tu
---
include/qemu/sockets.h | 3 +++
util/osdep.c | 24
2 files changed, 27 insertions(+)
diff --git a/include/qemu/sockets.h b/include/qemu/
From: Zenghui Yu
With the introduction of the new TCG GICv4, build_madt() is badly broken
as we do not present any GIC Redistributor structure in MADT for GICv4
guests, so that they have no idea about where the Redistributor
register frames are. This fixes a Linux guest crash at boot time with
AC
From: Guoyi Tu
introduce qemu_socketpair() to create socket pair fd, and
set the close-on-exec flag at default as with the other type
of socket does.
besides, the live update feature is developing, so it's necessary
to do that.
Guoyi Tu (2):
osdeps: Introduce qemu_socketpair()
vhost-user:
From: Guoyi Tu
set close-on-exec flag on the new opened file descriptors at default
Signed-off-by: Guoyi Tu
---
hw/display/vhost-user-gpu.c | 3 ++-
hw/virtio/vhost-user.c | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/display/vhost-user-gpu.c b/hw/display/vhost
From: Stefan Weil
Signed-off-by: Stefan Weil
Reviewed-by: Hongren (Zenithal) Zheng
Message-id: 20220812075642.1200578-1...@weilnetz.de
Reviewed-by: Peter Maydell
Signed-off-by: Peter Maydell
---
docs/about/deprecated.rst | 2 +-
docs/specs/acpi_erst.rst| 4 ++--
docs/system/d
The newly added neoverse-n1 CPU has ID register values which indicate
the presence of the Statistical Profiling Extension, because the real
hardware has this feature. QEMU's TCG emulation does not yet
implement SPE, though (not even as a minimal stub implementation), so
guests will crash if they t
From: Philippe Mathieu-Daudé
Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot
to move the macOS dyld(3) include, resulting in the following
error (when building with Homebrew GCC on macOS Monterey 12.4):
[313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o
FAILED: libq
es since commit a6b1c53e79d08a99a28cc3e67a3e1a7c34102d6b:
Merge tag 'linux-user-for-7.1-pull-request' of
https://gitlab.com/laurent_vivier/qemu into staging (2022-08-10 10:26:57 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20220812
for y
On Fri, 12 Aug 2022 at 12:44, wrote:
>
> From: Guoyi Tu
>
> set close-on-exec flag on the new opened file descriptors at default
What goes wrong if we don't do this? The commit message
is a good place to explain what bug the commit is fixing,
and its consequences.
thanks
-- PMM
From: Marc-André Lureau
../tests/test-qobject-input-visitor.c: In function ‘test_visitor_in_list’:
../tests/test-qobject-input-visitor.c:454:49: warning: ‘%d’ directive output
may be truncated writing between 1 and 10 bytes into a region of size 6
[-Wformat-truncation=]
454 | snprintf
On Fri, 12 Aug 2022 08:38:59 -0300
Murilo Opsfelder Araújo wrote:
> On 8/12/22 04:26, Claudio Imbrenda wrote:
> > On Thu, 11 Aug 2022 23:05:52 -0300
> > Murilo Opsfelder Araújo wrote:
> >
> >> On 8/11/22 11:02, Daniel P. Berrangé wrote:
> >> [...]
> > Hmm, I was hoping you could just use
On Fri, 12 Aug 2022 at 12:44, wrote:
>
> From: Guoyi Tu
>
> qemu_socketpair() will create a pair of connected sockets
> with FD_CLOEXEC set
>
> Signed-off-by: Guoyi Tu
> ---
> include/qemu/sockets.h | 3 +++
> util/osdep.c | 24
> 2 files changed, 27 insertio
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Cortex-R52 has the MPUIR register which has the same encoding
> has the MIDR alias with opc2=4. So we only add that alias
> when we are not realizing a Cortex-R.
>
> Signed-off-by: Tobias Röhmel
> ---
> target/arm/h
(I've added your rwth-aachen.de address because the quicinc
one seems to be bouncing :-( )
On Mon, 18 Jul 2022 at 12:54, Tobias Roehmel wrote:
>
> From: Tobias Röhmel
>
> Signed-off-by: Tobias Röhmel
Having looked a bit more carefully at the architecture
manual, I think this is not complete. I
Our decoding of fence-instructions is problematic in respect to the
RISC-V ISA specification:
- rs and rd are ignored, but need to be 0
- fm is ignored
This change adjusts the decode pattern to enfore rs and rd being 0,
and validates the fm-field (together with pred/succ for FENCE.TSO) to
determin
The RISC-V specification specifies imm12, rs1 and rd to be all-zeros,
so we can't ignore these bits when decoding into fence.i.
Update the decode pattern to reflect the specification.
Signed-off-by: Philipp Tomsich
---
target/riscv/insn32.decode | 2 +-
1 file changed, 1 insertion(+), 1 deleti
On Fri, 12 Aug 2022 at 14:17, Philipp Tomsich wrote:
>
> Our decoding of fence-instructions is problematic in respect to the
> RISC-V ISA specification:
> - rs and rd are ignored, but need to be 0
> - fm is ignored
>
> This change adjusts the decode pattern to enfore rs and rd being 0,
> and valid
This patch adds support for asynchronously tearing down a VM on Linux.
When qemu terminates, either naturally or because of a fatal signal,
the VM is torn down. If the VM is huge, it can take a considerable
amount of time for it to be cleaned up. In case of a protected VM, it
might take even longe
PATCH v1: add support for SMBIOS type 8 to qemu
PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
internal_reference: internal reference designator
external_reference: external reference designator
connector_type: hex value for port connector type (see SMBIOS 7.9.2)
por
Please use a cover-letter for multi-patch patch series.
On Fri, Aug 12, 2022 at 03:13:03PM +0200, Philipp Tomsich wrote:
> The RISC-V specification specifies imm12, rs1 and rd to be all-zeros,
> so we can't ignore these bits when decoding into fence.i.
>
> Update the decode pattern to reflect t
On Fri, Aug 12, 2022 at 03:13:04PM +0200, Philipp Tomsich wrote:
> Our decoding of fence-instructions is problematic in respect to the
> RISC-V ISA specification:
> - rs and rd are ignored, but need to be 0
> - fm is ignored
>
> This change adjusts the decode pattern to enfore rs and rd being 0,
>
On Fri, 12 Aug 2022 at 16:01, Andrew Jones wrote:
>
> > Update the decode pattern to reflect the specification.
>
> I got hung-up on this for a bit since there isn't any "must-be-0" fields,
Please refer to '“Zifencei” Instruction-Fetch Fence, Version 2.0' in
the specification.
The encoding diagra
On 11.08.2022 17:00, Alexander Ivanov wrote:
When an image is opened, data_end field in BDRVParallelsState
is setted as the biggest offset in the BAT plus cluster size.
If there is a corrupted offset pointing outside the image,
the image size increase accordingly. It potentially leads
to attempts
Happy to lower it back into the decode file.
However, I initially pulled it up into the trans-function to more
closely match the ISA specification: there is only one FENCE
instruction with 3 arguments (FM, PRED, and SUCC).
One might argue that the decode table for "RV32I Base Instruction Set"
in th
On Fri, 12 Aug 2022 at 15:11, Philipp Tomsich wrote:
>
> On Fri, 12 Aug 2022 at 16:01, Andrew Jones wrote:
> >
> > > Update the decode pattern to reflect the specification.
> >
> > I got hung-up on this for a bit since there isn't any "must-be-0" fields,
>
> Please refer to '“Zifencei” Instructio
On 11.08.2022 17:00, Alexander Ivanov wrote:
Will need to set BAT entry in multiple places.
Move the code of settings entries and marking relevant blocks dirty
to a separate helper parallels_set_bat_entry.
The comment and the patch text is ambiguous.
You say that we need to set BAT in multiple p
Use generic infrastructure for BAT writing in parallels_co_check()
On 11.08.2022 17:00, Alexander Ivanov wrote:
It's too costly to write all the BAT to the disk. Let the flush function
write only dirty blocks.
Use parallels_set_bat_entry for setting a BAT entry and marking a relevant
block as di
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The same rationale provided in the PHB3 bus case applies here.
Note: we could have merged both buses in a single object, like we did
with the root ports, and spare some boilerplate. The reason we opted to
preserve both buses objects is twofo
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
For default root ports we have a way of accessing chassis and slot,
before root_port_realize(), via pnv_phb_attach_root_port(). For the
future user created root ports this won't be the case: we can't use
this helper because we don't have acce
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Revert the condition with s->header_unclean.
same comment about change log as previously
And commit message misses motivation part, why we are
doing this rework. What is the goal of this change?
The code part is clean.
Signed-off-by: Alexander
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
We rely on the phb-id and chip-id, which are PHB properties, to assign
chassis and slot to the root port. For default devices this is no big
deal: the root port is being created under pnv_phb_realize() and the
values are being passed on via t
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Move unrelated helper parallels_set_bat_entry creation to
a separate patch.
same notes as for previous patch
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 48 ++-
1 file changed, 35
On Fri, 10 Jun 2022 at 17:07, Peter Maydell wrote:
>
> From: Richard Henderson
>
> With ARMv8, this field is always RES0.
> With ARMv7, targeting EL2 and TA=0, it is always 0xA.
I was just looking at this change again because we still
have the loose end of syn_simd_access_trap() not being used,
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: No changes.
same notes about motivation, changelog as before
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 85 +--
1 file changed, 52 insertions(+), 33 deletions(-)
diff --git a/block/pa
On 11.08.2022 17:00, Alexander Ivanov wrote:
v2: Move fragmentation counting code to this function too.
same note here about ChnageLog and motivation
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 54 +++
1 file changed, 31 insertions(+
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
pnv_parent_qom_fixup() and pnv_parent_bus_fixup() are versions of the
helpers that were reverted by commit 9c10d86fee "ppc/pnv: Remove
user-created PHB{3,4,5} devices". They are needed to amend the QOM and
bus hierarchies of user created pnv-
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
When enabling user created PHBs (a change reverted by commit 9c10d86fee)
we were handling PHBs created by default versus by the user in different
manners. The only difference between these PHBs is that one will have a
valid phb3->chip that is
Hi Peter,
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get ma
On 11.08.2022 17:00, Alexander Ivanov wrote:
Replace the way we use mutex in parallels_co_check() for more clean code.
I think that "cleaness" is the same, but new code would be just shorter ;)
or less error prone.
v2: Fix an incorrect usage of WITH_QEMU_LOCK_GUARD.
Signed-off-by: Alexander I
On Fri, Aug 12, 2022 at 03:51:53PM +0200, Hal Martin wrote:
> PATCH v1: add support for SMBIOS type 8 to qemu
> PATCH v2: incorporate patch v1 feedback and add smbios type=8 to qemu-options
history after --- pls
> internal_reference: internal reference designator
> external_reference: external re
On Thu, 2022-08-11 at 08:42 -0700, Richard Henderson wrote:
> On 8/11/22 02:28, Ilya Leoshkevich wrote:
> > How is qemu-user's get_page_addr_code() involved here?
> >
> > I tried to experiment with it, and while I agree that it looks
> > buggy,
> > it's called only from translation code paths. If
On 11.08.2022 17:00, Alexander Ivanov wrote:
Fix image inflation when offset in BAT is out of image.
Replace whole BAT syncing by flushing only dirty blocks.
Move all the checks outside the main check function in
separate functions
Use WITH_QEMU_LOCK_GUARD for more clean code.
Alexander Ivano
On Fri, 12 Aug 2022 10:25:55 +0100,
Peter Maydell wrote:
>
> I've added some more relevant mailing lists to the cc.
>
> On Fri, 12 Aug 2022 at 09:45, Vitaly Chikunov wrote:
> > On Fri, Aug 12, 2022 at 05:14:27AM +0300, Vitaly Chikunov wrote:
> > > I noticed that we starting to get many errors l
In more recent Raspbian OS Linux kernels, the fb driver gives up
immediately if RPI_FIRMWARE_FRAMEBUFFER_GET_NUM_DISPLAYS fails or no
displays are reported.
This change simply always reports one display. It makes bcm2835_fb work
again with these more recent kernels.
Signed-off-by: Enrik Berkhan
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The PHB4 backend relies on a link with the corresponding PEC element.
This is trivial to do during machine_init() time for default devices,
but not so much for user created ones.
pnv_phb4_get_pec() is a small variation of the function that w
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The function assumes that we're always dealing with a PNV9_CHIP()
object. This is not the case when the pnv-phb device belongs to a
powernv10 machine.
Change pnv_phb4_get_pec() to be able to work with PNV10_CHIP() if
necessary.
Signed-off-b
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
Given that powernv9 and powernv10 uses the same pnv-phb backend, the
logic to allow user created pnv-phbs for powernv10 is already in place.
Let's flip the switch.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
On Thu, 11 Aug 2022 18:08:57 +0100
Jonathan Cameron via wrote:
> On Tue, 9 Aug 2022 17:08:25 +0100
> Jonathan Cameron wrote:
>
> > On Tue, 9 Aug 2022 21:07:06 +0800
> > Bobo WL wrote:
> >
> > > Hi Jonathan
> > >
> > > Thanks for your reply!
> > >
> > > On Mon, Aug 8, 2022 at 8:37 PM Jonat
On Thu, Aug 4, 2022 at 12:44 PM Marc-André Lureau
wrote:
> Hi
>
> Great work so far! This seems easier to hack than my attempt to use
> clang-tidy to write some qemu checks
> (https://github.com/elmarco/clang-tools-extra)
>
> The code seems quite generic, I wonder if such a tool in python wasn't
>
On Wed, Aug 3, 2022 at 1:30 PM Peter Maydell wrote:
> The problem with a patch like this is that it rolls up into a
> single patch changes to the API of many functions in multiple
> subsystems across the whole codebase. Some of those changes
> might be right; some might be wrong. No single person
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
User creatable root ports are being parented by the 'peripheral' or the
'peripheral-anon' container. This happens because this is the regular
QOM schema for sysbus devices that are added via the command line.
Let's make this QOM hierarchy si
Jonathan Cameron wrote:
> On Thu, 11 Aug 2022 18:08:57 +0100
> Jonathan Cameron via wrote:
>
> > On Tue, 9 Aug 2022 17:08:25 +0100
> > Jonathan Cameron wrote:
> >
> > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > Bobo WL wrote:
> > >
> > > > Hi Jonathan
> > > >
> > > > Thanks for your reply!
>
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
Enable pnv-phb user created devices for powernv9 now that we have
everything in place.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
Same comment as in patch 6 regarding the QOM relationship of the
user-creat
On Fri, 12 Aug 2022 09:03:02 -0700
Dan Williams wrote:
> Jonathan Cameron wrote:
> > On Thu, 11 Aug 2022 18:08:57 +0100
> > Jonathan Cameron via wrote:
> >
> > > On Tue, 9 Aug 2022 17:08:25 +0100
> > > Jonathan Cameron wrote:
> > >
> > > > On Tue, 9 Aug 2022 21:07:06 +0800
> > > > Bobo WL
On 11/08/2022 18:39, Daniel Henrique Barboza wrote:
The bulk of the work was already done by previous patches.
Use defaults_enabled() to determine whether we need to create the
default devices or not.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
---
The QOM relat
On Wed, Aug 3, 2022 at 12:15 PM Richard W.M. Jones wrote:
> If it helps to think about this, Coverity checks for consistency.
> Across the whole code base, is the return value of a function used or
> ignored consistently. You will see Coverity errors like:
>
> Error: CHECKED_RETURN (CWE-252
On Sun, 3 Jul 2022 at 09:25, Richard Henderson
wrote:
>
> This is a major reorg to arm page table walking. While the result
> here is "merely" Hardware-assited Access Flag and Dirty Bit Setting
> (HAFDBS), the ultimate goal is the Realm Management Extension (RME).
> RME "recommends" that HAFDBS b
cpu64.c has ended up in a slightly odd order -- it starts with the
initfns for most of the models-real-hardware CPUs; after that comes a
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
come the initfns for the 'host' and 'max' CPU types, and then after
that one more models-real
:17
+0200)
Pull request linux-user 20220812
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as
appropriate.
r~
Vitaly Buka (1):
linux-user/aarch64: Reset target data on MADV_DONTNEED
accel/tcg
On 8/12/22 09:31, Peter Maydell wrote:
Is it possible to rearrange this patchset so the easy
refactoring patches that do "use a struct to return
values from get_phys_addr and friends" are at the front
(ie before the stuff that touches core code) ?
That way they're easy to take into the tree early
On 8/12/22 08:02, Ilya Leoshkevich wrote:
tb_lookup() skips get_page_addr_code() if tb is found in tb_jmp_cache.
I assume it's a bug?
Yes, I think so. I've rearranged that for other reasons, and so may have inadvertently
fix this. I'll post the in-progress work in a moment.
r~
This is part of a larger body of work, but in the process of
reorganizing I was reminded that PROT_EXEC wasn't being enforced
properly for user-only. As this has come up in the context of
some of Ilya's patches, I thought I'd go ahead and post this part.
r~
Ilya Leoshkevich (1):
accel/tcg: I
We're about to start validating PAGE_EXEC, which means
that we've got to put this code into a section that is
both writable and executable.
Note that this test did not run on hardware beforehand either.
Signed-off-by: Richard Henderson
---
tests/tcg/i386/test-i386.c | 2 +-
1 file changed, 1 in
We're about to start validating PAGE_EXEC, which means
that we've got to mark the commpage executable. We had
been placing the commpage outside of reserved_va, which
was incorrect and lead to an abort.
Signed-off-by: Richard Henderson
---
linux-user/arm/target_cpu.h | 4 ++--
linux-user/elfload
The only user can easily use translator_lduw and
adjust the type to signed during the return.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 1 -
target/i386/tcg/translate.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/exec/translator.h b/incl
Map the stack executable if required by default or on demand.
Signed-off-by: Richard Henderson
---
include/elf.h| 1 +
linux-user/qemu.h| 1 +
linux-user/elfload.c | 19 ++-
3 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
We're about to start validating PAGE_EXEC, which means that we've
got to mark page zero executable. We had been special casing this
entirely within translate.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 34 +++---
1 file changed, 31 insertions(+), 3 d
We're about to start validating PAGE_EXEC, which means that we've
got to the vsyscall page executable. We had been special casing
this entirely within translate.
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/
This function is used only once, so merge it into
its only caller, tb_lookup. This requires moving
the support routine, tb_lookup_cmp, and its private
data structure, tb_desc, up in the file.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 3 -
accel/tcg/cpu-exec.c| 134 +++
Bool is more appropriate type for the alloc parameter.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index cf99b2b876..65a23f47d6 100644
--- a
This bitmap is created and discarded immediately.
We gain nothing by its existence.
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 78 ++-
1 file changed, 4 insertions(+), 74 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/tr
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