On Fri, 12 Aug 2022 at 16:01, Andrew Jones <ajo...@ventanamicro.com> wrote: > > > Update the decode pattern to reflect the specification. > > I got hung-up on this for a bit since there isn't any "must-be-0" fields,
Please refer to '“Zifencei” Instruction-Fetch Fence, Version 2.0' in the specification. The encoding diagram clearly states 0 for imm[11:0], 0 for rs1 and 0 for rd. However, there is an explanatory paragraph below (unfortunately, it is not clear whether this is normative or informative): > The unused fields in the FENCE.I instruction, imm[11:0], rs1, and rd, are > reserved for finer-grain fences in future extensions. For forward > compatibility, base implementations shall ignore these fields, and standard > software shall zero these fields. Strictly speaking, this patch may be too restrictive (it violates the "for forward-compatibility" part — which I consider informative only, though). Thanks, Philipp.
