Re: [PATCH] linux-user: Fix pipe() vs. pipe2() usage for ALPHA, MIPS, SH4 and SPARC

On Sun, 17 Jul 2022 at 17:10, Helge Deller wrote: > > In 2010, the commit b41a66edd0c added a thrird parameter "is_pipe2" to the typo in commit hash (lost the first letter). Should be fb41a66edd0c7bd6 ("alpha-linux-user: Fix pipe return mechanism." I think ? > internal do_pipe() function, but mi

Re: [PATCH v8 05/11] i386/pc: factor out cxl range end to helper

On Fri, 15 Jul 2022 18:16:22 +0100 Joao Martins wrote: > Move calculation of CXL memory region end to separate helper. > > This is in preparation to a future change that removes CXL range > dependency on the CXL memory region, with the goal of allowing > pc_pci_hole64_start() to be called before

Re: [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end()

On Fri, 15 Jul 2022 18:16:24 +0100 Joao Martins wrote: > Remove pc_get_cxl_range_end() dependency on the CXL memory region, > and replace with one that does not require the CXL host_mr to determine > the start of CXL start. > > This in preparation to allow pc_pci_hole64_start() to be called earl

Re: [PATCH v8 08/11] i386/pc: factor out device_memory base/size to helper

On Fri, 15 Jul 2022 18:16:25 +0100 Joao Martins wrote: > Move obtaining hole64_start from device_memory memory region base/size > into an helper alongside correspondent getters in pc_memory_init() when > the hotplug range is unitialized. While doing that remove the memory > region based logic fro

[PATCH V3 1/6] target/riscv: Add check for supported privilege mode combinations

There are 3 suggested privilege mode combinations listed in section 1.2 of the riscv-privileged spec(draft-20220717): 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 6 ++ 1 fil

[PATCH V3 4/6] target/riscv: Add check for csrs existed with U extension

Add umode/umode32 predicate for mcounteren, menvcfg/menvcfgh Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/csr.c | 24 +--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/targe

[PATCH V3 0/6] Improve the U/S/H extension related check

This patchset tries to improve the U/S/H related check: * add check for the supported privilege modes conbinations: only supporting M, S mode is not a suggested combination * add check for "H extension depends on I extension" * add check for "H extension implicitly requires S mode" * add check for

[PATCH V3 3/6] target/riscv: Fix checkpatch warning may triggered in csr_ops table

Fix the lines with over 80 characters Fix the lines which are obviously misalgined with other lines in the same group Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/csr.c | 441 ---

[PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check

Just add 1 to the effective privledge level when in HS mode, then reuse the check of 'effective_priv < csr_priv' in riscv_csrrw_check to replace the privilege level related check in hmode. Then, hmode will only check whether H extension is supported. When accessing Hypervior CSRs: 1) If accessi

[PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32

Add check for the implicit dependence between H and S Csrs only existed in RV32 will not trigger virtual instruction fault when not in RV32 based on section 8.6.1 of riscv-privileged spec (draft-20220717) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Andrew Jones --- targ

[PATCH V3 2/6] target/riscv: H extension depends on I extension

Add check for "H depends on an I base integer ISA with 32 x registers" which is stated at the beginning of chapter 8 of the riscv-privileged spec(draft-20220717) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones --- target/riscv/cpu.

Re: [PATCH] x86: cpu: Error out if memory exceeds addressable range

On 7/18/2022 6:12 PM, Igor Mammedov wrote: > On Mon, 18 Jul 2022 13:47:34 +0530 > Nikunj A Dadhania wrote: > >> Currently it is possible to start a guest with memory that is beyond >> the addressable range of CPU and QEMU does not even warn about it. >> The default phys_bits is 40 and can addr

Re: [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA

On Fri, 15 Jul 2022 18:16:26 +0100 Joao Martins wrote: > Calculate max *used* GPA against the CPU maximum possible address > and error out if the former surprasses the latter. This ensures > max used GPA is reacheable by configured phys-bits. Default phys-bits > on Qemu is TCG_PHYS_ADDR_BITS (40)

Re: [PATCH 1/1] block: add missed block_acct_setup with new block device init procedure

On 11.07.2022 13:07, Denis V. Lunev wrote: Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from the first glance, but it has changed things a lot. 'libvirt' uses it to detect that it should follow new initialization way and this changes things considerably. With this procedure

Re: [PATCH v7 12/13] multifd: Zero pages transmission

* Juan Quintela (quint...@redhat.com) wrote: > This implements the zero page dection and handling. > > Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert > > --- > > Add comment for offset (dave) > Use local variables for offset/block to have shorter lines > --- > migration/mu

Re: [PATCH v8 10/11] i386/pc: relocate 4g start to 1T where applicable

On Fri, 15 Jul 2022 18:16:27 +0100 Joao Martins wrote: > It is assumed that the whole GPA space is available to be DMA > addressable, within a given address space limit, except for a > tiny region before the 4G. Since Linux v5.4, VFIO validates > whether the selected GPA is indeed valid i.e. not

[RFC PATCH v2] tests/9p: introduce declarative function calls

There are currently 4 different functions for sending a 9p 'Twalk' request. They are all doing the same thing, just in a slightly different way and with slightly different function arguments. Merge those 4 functions into a single function by using a struct for function call arguments and use desig

[PATCH 0/5] NIC vhost-vdpa state restore via Shadow CVQ

CVQ of net vhost-vdpa devices can be intercepted since the work of [1]. The virtio-net device model is updated. The migration was blocked because although the state can be megrated between VMM it was not possible to restore on the destination NIC. This series add support for SVQ to inject external

[PATCH 4/5] vdpa: Add virtio-net mac address via CVQ at start

This is needed so the destination vdpa device see the same state a the guest set in the source. Signed-off-by: Eugenio Pérez --- include/net/vhost-vdpa.h | 1 + hw/net/vhost_net.c | 8 ++ net/vhost-vdpa.c | 59 ++-- 3 files changed, 66 inse

[PATCH 3/5] vdpa: Make vhost_vdpa_net_cvq_map_elem accept any out sg

So its generic enough to accept any out sg buffer and we can inject NIC state messages. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 29 +++-- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index fa00928854..533b

Re: [PATCH 1/4] Modifying ‘migrate’ qmp command to add multi-FD socket on particular source and destination pair

On 18/07/22 2:05 pm, Markus Armbruster wrote: Het Gala writes: i) Modified the format of the qemu monitor command : 'migrate' by adding a list, each element in the list consists of multi-FD connection parameters: source and destination uris and of the number of multi-fd channels betw

[PATCH 1/5] vhost: stop transfer elem ownership in vhost_handle_guest_kick

It was easier to allow vhost_svq_add to handle the memory. Now that we will move SVQDesc to an opaque context, it's better to handle it in the caller. Signed-off-by: Eugenio Pérez --- hw/virtio/vhost-shadow-virtqueue.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git

[PATCH 2/5] vdpa: Extract vhost_vdpa_net_cvq_add from vhost_vdpa_net_handle_ctrl_avail

So we can reuse to inject state messages. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 71 ++-- 1 file changed, 44 insertions(+), 27 deletions(-) diff --git a/net/vhost-vdpa.c b/net/vhost-vdpa.c index 986e6414b4..fa00928854 100644 --- a/net/vho

Re: [PATCH v7 13/13] migration: Use multifd before we check for the zero page

* Juan Quintela (quint...@redhat.com) wrote: > So we use multifd to transmit zero pages. > > Signed-off-by: Juan Quintela Reviewed-by: Dr. David Alan Gilbert > > --- > > - Check zero_page property before using new code (Dave) > --- > migration/ram.c | 33 - >

Re: [PATCH v7 07/14] KVM: Use gfn instead of hva for mmu_notifier_retry

On Fri, Jul 15, 2022 at 01:36:15PM +0200, Gupta, Pankaj wrote: > > Currently in mmu_notifier validate path, hva range is recorded and then > > checked in the mmu_notifier_retry_hva() from page fault path. However > > for the to be introduced private memory, a page fault may not have a hva > > As t

[PATCH 5/5] vdpa: Delete CVQ migration blocker

We can restore the device state in the destination via CVQ now. Remove the migration blocker. Signed-off-by: Eugenio Pérez --- include/hw/virtio/vhost-vdpa.h | 1 - hw/virtio/vhost-vdpa.c | 11 --- net/vhost-vdpa.c | 2 -- 3 files changed, 14 deletions(-) diff --

Re: [PATCH] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug()

On Mon, 18 Jul 2022 15:12:03 +0800 Robert Hoo wrote: [...] > BTW, during the unit test, I met some bios-table test error, > https://gitlab.com/qemu-project/qemu/-/issues/1098, perhaps related to > your patches in June. > https://patchwork.kernel.org/project/qemu-devel/cover/20220608135340.3304695

Re: [PATCH] hw/virtio/virtio-iommu: Enforce power-of-two notify for both MAP and UNMAP

Hi Tina, On Fri, Jul 15, 2022 at 12:09:23AM +, Zhang, Tina wrote: > > +static void virtio_iommu_notify_map_unmap(IOMMUMemoryRegion *mr, > > + IOMMUTLBEvent *event, > > + hwaddr virt_start, hwaddr > > +virt_end) {

Re: [PATCH] x86: cpu: Error out if memory exceeds addressable range

On 7/18/22 14:10, Nikunj A. Dadhania wrote: > On 7/18/2022 6:12 PM, Igor Mammedov wrote: >> On Mon, 18 Jul 2022 13:47:34 +0530 >> Nikunj A Dadhania wrote: >> >>> Currently it is possible to start a guest with memory that is beyond >>> the addressable range of CPU and QEMU does not even warn about

Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32

Same other $SUBJECT and comment suggestions as the previous patches. On Tue, Jul 12, 2022 at 02:32:35PM +0800, Weiwei Li wrote: > - add check for the implicit dependence between H and S > - Csrs only existed in RV32 will not trigger virtual instruction fault > when not in RV32 I think I found t

[PATCH 13/16] virtio: introduce queue_enable in virtio

Introduce the interface queue_enable() in VirtioDeviceClass and the fucntion virtio_queue_enable() in virtio, it can be called when VIRTIO_PCI_COMMON_Q_ENABLE is written. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo --- hw/virtio/virtio-pci.c | 1 + hw/virtio/virtio.c | 9

Re: [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table

On Tue, Jul 12, 2022 at 02:32:33PM +0800, Weiwei Li wrote: > - fix the lines with over 80 characters > - fix the lines which is obviously misalgined with other lines s/is/are/ > in same the group Same comments as other patches about '-' vs. sentences. Also, please capitalize 'fix' in $SUBJECT.

Re: [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension

On Tue, Jul 12, 2022 at 02:32:34PM +0800, Weiwei Li wrote: > - add umode/umode32 predicate for mcounteren,menvcfg/menvcfgh Same commit message and $SUBJECT comments as the other patches. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang > Reviewed-by: Alistair Francis > --- > targe

[PATCH 00/16] Support VIRTIO_F_RING_RESET for virtio-net and vhost-user in virtio pci

The virtio queue reset function has already been defined in the virtio spec 1.2. The relevant virtio spec information is here: https://github.com/oasis-tcs/virtio-spec/issues/124 https://github.com/oasis-tcs/virtio-spec/issues/139 This patch set is to support this function in QEMU. It con

[PATCH 01/16] virtio-pci: virtio_pci_common_cfg add queue_notify_data

From: Xuan Zhuo Add queue_notify_data in struct virtio_pci_common_cfg, which comes from here https://github.com/oasis-tcs/virtio-spec/issues/89 Since I want to add queue_reset after queue_notify_data, I submitted this patch first. Signed-off-by: Xuan Zhuo --- include/standard-headers/linux/vi

[PATCH 07/16] virtio-net: support queue reset

From: Xuan Zhuo virtio-net implements queue reset. Queued packets in the corresponding queue pair are flushed or purged. Queue reset is currently only implemented for non-vhosts. Signed-off-by: Xuan Zhuo --- hw/net/virtio-net.c | 15 +++ 1 file changed, 15 insertions(+) diff --gi

Re: [PATCH v2 2/6] target/riscv: H extension depends on I extension

On Tue, Jul 12, 2022 at 02:32:32PM +0800, Weiwei Li wrote: > - add check for "H depends on an I base integer ISA with 32 x registers" Please use a normal sentence without '-'. It'd be nice to write the doc/version/section of the spec that inspires this check in the commit message. > > Signed-off

[PATCH 03/16] virtio: pci: virtio_pci_common_cfg add queue_reset

From: Xuan Zhuo Add queue_reset in virtio_pci_common_cfg. Signed-off-by: Xuan Zhuo --- include/standard-headers/linux/virtio_pci.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/standard-headers/linux/virtio_pci.h b/include/standard-headers/linux/virtio_pci.h index 598ebe9825..

[PATCH 06/16] virtio-pci: support queue reset

From: Xuan Zhuo PCI devices support vq reset. Based on this function, the driver can adjust the size of the ring, and quickly recycle the buffer in the ring. Signed-off-by: Xuan Zhuo --- hw/virtio/virtio-pci.c | 16 include/hw/virtio/virtio-pci.h | 1 + 2 files chang

[PATCH 05/16] virtio: introduce virtio_queue_reset()

From: Xuan Zhuo Introduce a new interface function virtio_queue_reset() to implement reset for vq. Add a new callback to VirtioDeviceClass for queue reset operation for each child device. Signed-off-by: Xuan Zhuo --- hw/virtio/virtio.c | 11 +++ include/hw/virtio/virtio.h | 2

Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa

On 7/18/2022 2:54 PM, Igor Mammedov wrote: On Mon, 11 Jul 2022 11:44:29 +0100 Hesham Almatary wrote: From: Brice Goglin The "Memory Proximity Domain Attributes" structure of the ACPI HMAT has a "Processor Proximity Domain Valid" flag that is currently always set because Qemu -numa requires

[PATCH 08/16] vhost: add op to enable or disable a single vring

The interface to set enable status for a single vring is lacked in VhostOps, since the vhost_set_vring_enable_op will manipulate all virtqueues in a device. Resetting a single vq will rely on this interface. It requires a reply to indicate that the reset operation is finished, so the parameter, wa

[PATCH 10/16] vhost: extract the logic of unmapping the vrings and desc

Introduce vhost_virtqueue_unmap() to ummap the vrings and desc of a virtqueue. The function will be used later. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo --- hw/virtio/vhost.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/hw/virtio/vhost.c b

[PATCH 11/16] vhost: introduce restart and release for vhost_dev's vqs

Introduce vhost_dev_virtqueue_restart(), which can restart the virtqueue when the vhost has already started running. Meanwhile, vhost_dev_virtqueue_release(), which can ummap the vrings and the desc of a specific vq of a device. Combining the two functions, we can reset a virtqueue with a started

[PULL 01/15] hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high

In the M-profile Arm ARM, rule R_CVJS defines when an interrupt should be set to the Pending state: A) when the input line is high and the interrupt is not Active B) when the input line transitions from low to high and the interrupt is Active (Note that the first of these is an ongoing condit

[PATCH 04/16] virtio: introduce __virtio_queue_reset()

From: Xuan Zhuo Separate the logic of vq reset. This logic will be called directly later. Signed-off-by: Xuan Zhuo --- hw/virtio/virtio.c | 37 + 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 5d

Re: [PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check

Hi Weiwei, We still need the s/resue/reuse/ typo fix in $SUBJECT. (That's maybe something that could be fixed up while applying?) Thanks, drew On Mon, Jul 18, 2022 at 09:09:55PM +0800, Weiwei Li wrote: > Just add 1 to the effective privledge level when in HS mode, then reuse > the check of 'e

[PATCH 12/16] vhost-net: introduce restart and stop for vhost_net's vqs

Introduce vhost_virtqueue_restart(), which can restart the virtqueue when the vhost net started running before. Introduce vhost_virtqueue_stop(), which can disable the vq and unmap vrings and the desc of the vq. When disabling the vq, the function is blocked and waits for a reply. Combining the t

[PATCH 16/16] vhost-net: vq reset feature bit support

Add support for negotation of vq reset feature bit. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo --- hw/net/vhost_net.c | 1 + hw/net/virtio-net.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/net/vhost_net.c b/hw/net/vhost_net.c index 4f5f034c11..de910f6466 1

[PATCH 15/16] virtio-net: support queue_reset for vhost-user

Support queue reset in vhost-user scenario. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo --- hw/net/virtio-net.c | 4 1 file changed, 4 insertions(+) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 2c26e2ef73..0747ffe71c 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/vir

Re: [PATCH] x86: cpu: Error out if memory exceeds addressable range

On 7/18/2022 7:15 PM, Joao Martins wrote: > On 7/18/22 14:10, Nikunj A. Dadhania wrote: >> On 7/18/2022 6:12 PM, Igor Mammedov wrote: >>> On Mon, 18 Jul 2022 13:47:34 +0530 >>> Nikunj A Dadhania wrote: >>> Currently it is possible to start a guest with memory that is beyond the addres

[PULL 02/15] target/arm: Fill in VL for tbflags when SME enabled and SVE disabled

From: Richard Henderson When PSTATE.SM, VL = SVL even if SVE is disabled. This is visible in kselftest ssve-test. Reported-by: Mark Brown Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-2-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell

[PATCH 02/16] virtio: add VIRTIO_F_RING_RESET

From: Xuan Zhuo Added VIRTIO_F_RING_RESET, it came from here https://github.com/oasis-tcs/virtio-spec/issues/124 This feature indicates that the driver can reset a queue individually. Signed-off-by: Xuan Zhuo --- include/standard-headers/linux/virtio_config.h | 5 + 1 file changed, 5 inse

Re: [PATCH v4] Align Raspberry Pi DMA interrupts with Linux DTS

On Sat, 16 Jul 2022 at 12:34, Andrey Makarov wrote: > > There is nothing in the specs on DMA engine interrupt lines: it should have > been in the "BCM2835 ARM Peripherals" datasheet but the appropriate > "ARM peripherals interrupt table" (p.113) is nearly empty. > > All Raspberry Pi models 1-3 (ba

[PULL 05/15] target/arm: Define and use new regime_tcr_value() function

The regime_tcr() function returns a pointer to a struct TCR corresponding to the TCR controlling a translation regime. The struct TCR has the raw value of the register, plus two fields mask and base_mask which are used as a small optimization in the case of 32-bit short-descriptor lookups. Almost

Re: [PATCH v8 06/11] i386/pc: factor out cxl range start to helper

On 7/18/22 13:52, Igor Mammedov wrote: > On Fri, 15 Jul 2022 18:16:23 +0100 > Joao Martins wrote: > >> Factor out the calculation of the base address of the memory region. >> It will be used later on for the cxl range end counterpart calculation >> and as well in pc_memory_init() CXL memory regio

[PATCH 09/16] vhost-user: enable/disable a single vring

Implement the vhost_set_single_vring_enable, which is to enable or disable a single vring. The parameter wait_for_reply is added to help for some cases such as vq reset. Meanwhile, vhost_user_set_vring_enable() is refactored. Signed-off-by: Kangjie Xu Signed-off-by: Xuan Zhuo --- hw/virtio/vh

Re: [PATCH 5/8] tests: Add HMAT AArch64/virt empty table files

On Mon, 11 Jul 2022 11:44:33 +0100 Hesham Almatary wrote: > Signed-off-by: Hesham Almatary > --- > tests/data/acpi/virt/DSDT.acpihmatvirt | 0 > tests/data/acpi/virt/FACP.acpihmatvirt | 0 > tests/data/acpi/virt/HMAT.acpihmatvirt | 0 > tests/data/acpi/virt/SRAT.acpihmatvirt

Re: [PATCH 1/8] hmat acpi: Don't require initiator value in -numa

On Mon, 11 Jul 2022 11:44:29 +0100 Hesham Almatary wrote: > From: Brice Goglin > > The "Memory Proximity Domain Attributes" structure of the ACPI HMAT > has a "Processor Proximity Domain Valid" flag that is currently > always set because Qemu -numa requires an initiator=X value > when hmat=on.

[PATCH 14/16] virtio-net: support queue_enable for vhost-user

Support queue enable in vhost-user scenario. It will be called when a vq reset operation is performed and the vq will be restared. It should be noted that we can restart the vq when the vhost has already started. When launching a new vhost-user device, the vhost is not started and all vqs are not

Re: [PATCH 6/8] hw/arm/virt: Enable HMAT on arm virt machine

On Mon, 11 Jul 2022 11:44:34 +0100 Hesham Almatary wrote: > From: Xiang Chen > > Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"), > HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine. > > Signed-off-by: Xiang Chen Reviewed-by: Igor Mamme

Re: [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA

On Mon, 18 Jul 2022 15:16:22 +0200 Igor Mammedov wrote: > On Fri, 15 Jul 2022 18:16:26 +0100 > Joao Martins wrote: > > > Calculate max *used* GPA against the CPU maximum possible address > > and error out if the former surprasses the latter. This ensures > > max used GPA is reacheable by config

[PULL 00/15] target-arm queue

in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220718 for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7: Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:2

Re: [PATCH v8 07/11] i386/pc: handle unitialized mr in pc_get_cxl_range_end()

On 7/18/22 13:58, Igor Mammedov wrote: > On Fri, 15 Jul 2022 18:16:24 +0100 > Joao Martins wrote: > >> Remove pc_get_cxl_range_end() dependency on the CXL memory region, >> and replace with one that does not require the CXL host_mr to determine >> the start of CXL start. >> >> This in preparation

[PULL 03/15] target/arm: Fix aarch64_sve_change_el for SME

From: Richard Henderson We were only checking for SVE disabled and not taking into account PSTATE.SM to check SME disabled, which resulted in vectors being incorrectly truncated. Signed-off-by: Richard Henderson Message-id: 20220713045848.217364-3-richard.hender...@linaro.org Reviewed-by: Peter

[PULL 04/15] linux-user/aarch64: Do not clear PROT_MTE on mprotect

From: Richard Henderson The documentation for PROT_MTE says that it cannot be cleared by mprotect. Further, the implementation of the VM_ARCH_CLEAR bit, contains PROT_BTI confiming that bit should be cleared. Introduce PAGE_TARGET_STICKY to allow target/arch/cpu.h to control which bits may be r

Re: [PATCH v8 08/11] i386/pc: factor out device_memory base/size to helper

On 7/18/22 14:03, Igor Mammedov wrote: > On Fri, 15 Jul 2022 18:16:25 +0100 > Joao Martins wrote: > >> Move obtaining hole64_start from device_memory memory region base/size >> into an helper alongside correspondent getters in pc_memory_init() when >> the hotplug range is unitialized. While do

[PULL 09/15] target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t

Change the representation of the VSTCR_EL2 and VTCR_EL2 registers in the CPU state struct from struct TCR to uint64_t. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-6-peter.mayd...@linaro.org --- target/arm/cpu.h | 4 ++-- target/arm/inter

[PULL 08/15] target/arm: Fix big-endian host handling of VTCR

We have a bug in our handling of accesses to the AArch32 VTCR register on big-endian hosts: we were not adjusting the part of the uint64_t field within TCR that the generated code would access. That can be done with offsetoflow32(), by using an ARM_CP_STATE_BOTH cpreg struct, or by defining a full

[PULL 10/15] target/arm: Store TCR_EL* registers as uint64_t

Change the representation of the TCR_EL* registers in the CPU state struct from struct TCR to uint64_t. This allows us to drop the custom vmsa_ttbcr_raw_write() function, moving the "enforce RES0" checks to their more usual location in the writefn vmsa_ttbcr_write(). We also don't need the resetf

[PULL 11/15] target/arm: Honour VTCR_EL2 bits in Secure EL2

In regime_tcr() we return the appropriate TCR register for the translation regime. For Secure EL2, we return the VSTCR_EL2 value, but in this translation regime some fields that control behaviour are in VTCR_EL2. When this code was originally written (as the comment notes), QEMU didn't care about

[PATCH 2/2] scripts/coverity-scan/COMPONENTS.md: Update slirp component info

Update the regex for the slirp component now that it lives solely inside /slirp/, and note that it should be ignored in Coverity analysis (because it's a separate upstream project now, and they run Coverity on it themselves). Signed-off-by: Peter Maydell --- scripts/coverity-scan/COMPONENTS.md |

[PULL 07/15] target/arm: Fold regime_tcr() and regime_tcr_value() together

The only caller of regime_tcr() is now regime_tcr_value(); fold the two together, and use the shorter and more natural 'regime_tcr' name for the new function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220714132303.1287193-4-peter.mayd...@linaro.org --- target/arm

[PULL 12/15] hw/adc: Fix CONV bit in NPCM7XX ADC CON register

From: Hao Wu The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch fixes that in the module, and also lower the IRQ when the guest is done handling an interrupt event from the ADC module. Signed-off-by: Hao Wu Reviewed-by: Patrick Venture Reviewed-by: Peter Maydell Message-id:

[PULL 06/15] target/arm: Calculate mask/base_mask in get_level1_table_address()

In get_level1_table_address(), instead of using precalculated values of mask and base_mask from the TCR struct, calculate them directly (in the same way we currently do in vmsa_ttbcr_raw_write() to populate the TCR struct fields). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Messa

[PULL 14/15] target/arm: Don't set syndrome ISS for loads and stores with writeback

The architecture requires that for faults on loads and stores which do writeback, the syndrome information does not have the ISS instruction syndrome information (i.e. ISV is 0). We got this wrong for the load and store instructions covered by disas_ldst_reg_imm9(). Calculate iss_valid correctly s

Re: [RFC PATCH v2] tests/9p: introduce declarative function calls

On Montag, 18. Juli 2022 15:10:55 CEST Christian Schoenebeck wrote: > There are currently 4 different functions for sending a 9p 'Twalk' > request. They are all doing the same thing, just in a slightly different > way and with slightly different function arguments. > > Merge those 4 functions into

[PULL 13/15] hw/adc: Make adci[*] R/W in NPCM7XX ADC

From: Hao Wu Our sensor test requires both reading and writing from a sensor's QOM property. So we need to make the input of ADC module R/W instead of write only for that to work. Signed-off-by: Hao Wu Reviewed-by: Titus Rwantare Reviewed-by: Peter Maydell Message-id: 20220714182836.89602-5-w

[PULL 15/15] Align Raspberry Pi DMA interrupts with Linux DTS

From: Andrey Makarov There is nothing in the specs on DMA engine interrupt lines: it should have been in the "BCM2835 ARM Peripherals" datasheet but the appropriate "ARM peripherals interrupt table" (p.113) is nearly empty. All Raspberry Pi models 1-3 (based on bcm2835) have Linux device tree (a

Re: [PATCH 1/4] Modifying ‘migrate’ qmp command to add multi-FD socket on particular source and destination pair

Het Gala writes: > On 18/07/22 2:05 pm, Markus Armbruster wrote: >> Het Gala writes: >> >>> i) Modified the format of the qemu monitor command : 'migrate' by adding a >>> list, >>> each element in the list consists of multi-FD connection parameters: >>> source >>> and destination uris

Re: [PATCH 3/8] tests: acpi: q35: add test for hmat nodes without initiators

On Mon, 11 Jul 2022 11:44:31 +0100 Hesham Almatary wrote: > From: Brice Goglin > > expected HMAT: > > [000h 4]Signature : "HMAT"[Heterogeneous > Memory Attributes Table] > [004h 0004 4] Table Length : 0120 > [008h 0008 1]

Re: [PATCH 4/8] tests: acpi: q35: update expected blobs *.hmat-noinitiators

On Mon, 11 Jul 2022 11:44:32 +0100 Hesham Almatary wrote: > From: Brice Goglin > [...] > Signed-off-by: Brice Goglin > --- > tests/data/acpi/q35/APIC.acpihmat-noinitiator | Bin 0 -> 144 bytes [...] > tests/data/acpi/q35/FACP.acpihmat-noinitiator | Bin 0 -> 244 bytes drop these 2 tables, the

[PATCH 0/2] coverity COMPONENTS.md: Update for loongarch, slirp

This patchseries updates the Coverity Scan component regexs to add a new component for the new loongarch architecture, and to tweak the slirp component and mark it as "ignore when doing scans" (since it's now a separate upstream project). Unfortunately there's no automated way to upload new compon

Re: [PATCH 7/8] tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators

On Mon, 11 Jul 2022 11:44:35 +0100 Hesham Almatary wrote: > This patch imitates the "tests: acpi: q35: add test for hmat nodes > without initiators" commit to test numa nodes with different HMAT > attributes, but on AArch64/virt. > > Tested with: > qemu-system-aarch64 -accel tcg \ > -machine vi

[PATCH 1/2] scripts/coverity-scan/COMPONENTS.md: Add loongarch component

Add the component regex for the new loongarch target. Signed-off-by: Peter Maydell --- scripts/coverity-scan/COMPONENTS.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/scripts/coverity-scan/COMPONENTS.md b/scripts/coverity-scan/COMPONENTS.md index de2eb962416..a61d011d9a4 100644 --- a

Re: [PATCH v8 09/11] i386/pc: bounds check phys-bits against max used GPA

On 7/18/22 14:56, Igor Mammedov wrote: > On Mon, 18 Jul 2022 15:16:22 +0200 > Igor Mammedov wrote: > >> On Fri, 15 Jul 2022 18:16:26 +0100 >> Joao Martins wrote: >> >>> Calculate max *used* GPA against the CPU maximum possible address >>> and error out if the former surprasses the latter. Thi

[PATCH v2] hw/virtio/virtio-iommu: Enforce power-of-two notify for both MAP and UNMAP

Currently we only enforce power-of-two mappings (required by the QEMU notifier) for UNMAP requests. A MAP request not aligned on a power-of-two may be successfully handled by VFIO, and then the corresponding UNMAP notify will fail because it will attempt to split that mapping. Ensure MAP and UNMAP

Re: [PATCH] linux-user: Fix pipe() vs. pipe2() usage for ALPHA, MIPS, SH4 and SPARC

On 7/18/22 14:51, Peter Maydell wrote: > On Sun, 17 Jul 2022 at 17:10, Helge Deller wrote: >> >> In 2010, the commit b41a66edd0c added a thrird parameter "is_pipe2" to the > > typo in commit hash (lost the first letter). Should be > fb41a66edd0c7bd6 ("alpha-linux-user: Fix pipe return mechanism."

Re: [PATCH] linux-user: Fix pipe() vs. pipe2() usage for ALPHA, MIPS, SH4 and SPARC

On Mon, 18 Jul 2022 at 15:21, Helge Deller wrote: > On 7/18/22 14:51, Peter Maydell wrote: > > Why do we need to do this? > > Yep, we don't *need* to... > > > If the flags argument is 0, > > then pipe2() is the same as pipe(), so we can safely > > emulate it with the host pipe() call. It is, or at

Re: [PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check

在 2022/7/18 下午9:47, Andrew Jones 写道: Hi Weiwei, We still need the s/resue/reuse/ typo fix in $SUBJECT. (That's maybe something that could be fixed up while applying?) Thanks, drew Thanks a lot. Sorry for not finding this typo. I'll fix it in next version. Regards, Weiwei Li On Mon, Ju

Re: [RFC PATCH 8/8] block: remove all unused ->can_set_aio_ctx and ->set_aio_ctx callbacks

Am 18/07/2022 um 10:45 schrieb Emanuele Giuseppe Esposito: > > > Am 15/07/2022 um 16:34 schrieb Hanna Reitz: >> On 12.07.22 23:19, Emanuele Giuseppe Esposito wrote: >>> Together with all _can_set_ and _set_ APIs, as they are not needed >>> anymore. >>> >>> Signed-off-by: Emanuele Giuseppe Espo

Re: [PATCH v2 07/11] vfio/migration: Implement VFIO migration protocol v2

On Mon, May 30, 2022 at 08:07:35PM +0300, Avihai Horon wrote: > +/* Returns 1 if end-of-stream is reached, 0 if more data and -1 if error */ > +static int vfio_save_block(QEMUFile *f, VFIOMigration *migration) > +{ > +ssize_t data_size; > + > +data_size = read(migration->data_fd, migration

Re: [PATCH 1/4] Modifying ‘migrate’ qmp command to add multi-FD socket on particular source and destination pair

On 18/07/22 8:03 pm, Markus Armbruster wrote: Het Gala writes: On 18/07/22 2:05 pm, Markus Armbruster wrote: Het Gala writes: i) Modified the format of the qemu monitor command : 'migrate' by adding a list, each element in the list consists of multi-FD connection parameters: source

Re: [PATCH v7 07/14] KVM: Use gfn instead of hva for mmu_notifier_retry

On Mon, Jul 18, 2022, Chao Peng wrote: > On Fri, Jul 15, 2022 at 01:36:15PM +0200, Gupta, Pankaj wrote: > > > Currently in mmu_notifier validate path, hva range is recorded and then > > > checked in the mmu_notifier_retry_hva() from page fault path. However > > > for the to be introduced private me

Re: [PULL 0/1] MAINTAINERS: Add myself as Guest Agent co-maintainer

On Mon, 18 Jul 2022 at 10:28, Konstantin Kostiuk wrote: > > > The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9: > > Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme > into staging (2022-07-15 15:38:13 +0100) > > are available in the Git reposito

Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support

On Fri, 2022-07-08 at 07:44 +0800, Weiwei Li wrote: > 在 2022/7/8 上午12:53, Mayuresh Chitale 写道: > > On Sat, 2022-07-02 at 18:19 +0800, angell1518 wrote: > > > At 2022-06-04 00:04:22, "Mayuresh Chitale" < > > > mchit...@ventanamicro.com > > > > wrote: > > > > Smstateen extension specifies a mechanism

Re: [PATCH] linux-user: Fix pipe() vs. pipe2() usage for ALPHA, MIPS, SH4 and SPARC

On 7/18/22 16:33, Peter Maydell wrote: > On Mon, 18 Jul 2022 at 15:21, Helge Deller wrote: >> On 7/18/22 14:51, Peter Maydell wrote: >>> Why do we need to do this? >> >> Yep, we don't *need* to... >> >>> If the flags argument is 0, >>> then pipe2() is the same as pipe(), so we can safely >>> emula

Re: [PATCH 0/2] coverity COMPONENTS.md: Update for loongarch, slirp

On 7/18/22 16:23, Peter Maydell wrote: This patchseries updates the Coverity Scan component regexs to add a new component for the new loongarch architecture, and to tweak the slirp component and mark it as "ignore when doing scans" (since it's now a separate upstream project). Unfortunately ther

Re: [PATCH] i386: Disable BTS and PEBS

On 7/18/22 05:22, Zhenzhong Duan wrote: Since below KVM commit, KVM hided BTS as it's not supported yet. b9181c8ef356 ("KVM: x86/pmu: Avoid exposing Intel BTS feature") After below KVM commit, it gave control of MSR_IA32_MISC_ENABLES to userspace. 9fc222967a39 ("KVM: x86: Give host userspace ful

Re: [PATCH v4 0/3] ui/cocoa: Run qemu_init in the main thread

On 7/17/22 09:33, Akihiko Odaki wrote: This work is based on: https://patchew.org/QEMU/20220317125534.38706-1-philippe.mathieu.da...@gmail.com/ Simplify the initialization dance by running qemu_init() in the main thread before the Cocoa event loop starts. The secondary thread only runs only qemu

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