On 04/06/2022 05.27, Richard Henderson wrote:
GCC11 from crossbuild-essential-armhf from ubuntu 22.04 errors:
cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU
Signed-off-by: Richard Henderson
---
tests/tcg/arm/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+),
On Fri, Jun 3, 2022 at 9:38 PM Ani Sinha wrote:
>
> On an additional note, my changes are not backward compatible with
> older compiler. The build will break when built with a centos 7
> docker/vm/host:
>
> /home/anisinha/workspace/bits/build/grub/grub-core/contrib-deps/python/Modules/_ctypes/_cty
Am 30. Mai 2022 19:45:26 UTC schrieb "Philippe Mathieu-Daudé" :
>On 30/5/22 21:11, Mark Cave-Ayland wrote:
>> On 29/05/2022 14:02, Bernhard Beschow wrote:
>
>>> Oh wait - I see now it's just the cover letter which is missing the
>>> additional
>>> maintainer addresses :) If you could add
There's a debian bugreport open - now against qemu -
https://bugs.debian.org/988333 -
which initially said VGA Intel IGD Passthrough to Debian Xen HVM DomUs not
working
but worked okay with windows DomUs.
The most interesting comment in there is the last one,
https://bugs.debian.org/988333#146
On 4/6/22 06:05, Richard Henderson wrote:
Move the decl from ptw.h to internals.h. Provide an inline
version for user-only, just as we do for arm_stage1_mmu_idx.
Move an endif down to make the definition in helper.c be
system only.
Signed-off-by: Richard Henderson
---
target/arm/internals.h
On 3/6/22 23:38, Richard Henderson wrote:
We had been using the i686 platform string for x86_64.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1041
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 30 +-
1 file changed, 17 insertions(+), 13 de
On Tue, May 24, 2022 at 01:30:54PM -0400, Emanuele Giuseppe Esposito wrote:
> It seems that aio_wait_kick always required a memory barrier
> or atomic operation in the caller, but nobody actually
> took care of doing it.
>
> Let's put the barrier in the function instead, and pair it
> with another
On 4/6/22 05:27, Richard Henderson wrote:
GCC11 from crossbuild-essential-armhf from ubuntu 22.04 errors:
cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU
Signed-off-by: Richard Henderson
---
tests/tcg/arm/Makefile.softmmu-target | 2 +-
1 file changed, 1 insertion(+), 1 de
On 3/6/22 10:59, Gerd Hoffmann wrote:
The pcie host bridge has no io window on microvm,
so io reservations will not work.
Signed-off-by: Gerd Hoffmann
---
hw/i386/microvm.c | 6 ++
1 file changed, 6 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
Le 03/06/2022 à 23:38, Richard Henderson a écrit :
We had been using the i686 platform string for x86_64.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1041
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 30 +-
1 file changed, 17 insertions(
On 6/4/22 03:40, Philippe Mathieu-Daudé wrote:
On 4/6/22 06:05, Richard Henderson wrote:
Move the decl from ptw.h to internals.h. Provide an inline
version for user-only, just as we do for arm_stage1_mmu_idx.
Move an endif down to make the definition in helper.c be
system only.
Signed-off-by:
This issue concerns the value of mtval for illegal
instruction exceptions, and came with a great test case.
The fix is just two lines, in the first patch, but
I noticed some cleanups on the way.
r~
Richard Henderson (3):
target/riscv: Set env->bins in gen_exception_illegal
target/riscv: Rem
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson
---
target/riscv/
The set of instructions that require decode_save_opc for
unwinding is really fairly small -- only insns that can
raise ILLEGAL_INSN at runtime. This includes CSR, anything
that uses a *new* fp rounding mode, and many privileged insns.
Since unwind info is stored as the difference from the
previou
The function doesn't set mtval, it sets badaddr. Move the set
of badaddr directly into gen_exception_inst_addr_mis and use
generate_exception.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/target/risc
From: Lucas Ramage
Buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Lucas Ramage
---
docs/devel/{blkdebug.txt => blkdebug.rst} | 8 +-
docs/devel/{blkverify.txt => blkverify.rst} | 12 ++---
docs/devel/index-build.rst| 2 ++
docs/deve
On Thu, Jun 02, 2022 at 08:39:21AM -0700, Richard Henderson wrote:
> On 5/27/22 10:27, Stafford Horne wrote:
> > +void do_or1k_semihosting(CPUOpenRISCState *env, uint32_t k);
> ...
> > +DEF_HELPER_FLAGS_2(nop, 0, void, env, i32)
>
> Just call the helper "semihosting" and be done with it.
> And the
On Fri, Jun 03, 2022 at 09:05:09AM +0200, Geert Uytterhoeven wrote:
> Hi Stafford,
>
> On Thu, Jun 2, 2022 at 9:59 PM Stafford Horne wrote:
> > On Thu, Jun 02, 2022 at 09:08:52PM +0200, Geert Uytterhoeven wrote:
> > > On Thu, Jun 2, 2022 at 1:42 PM Joel Stanley wrote:
> > > > On Fri, 27 May 2022
On Thu, Jun 02, 2022 at 11:42:30AM +, Joel Stanley wrote:
> Hi Stafford,
>
> On Fri, 27 May 2022 at 17:27, Stafford Horne wrote:
> >
> > This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This
> > platform allows for a convenient CI platform for toolchain, software
> > ports an
On 6/4/22 14:51, Roman Kagan wrote:
On Tue, May 24, 2022 at 01:30:54PM -0400, Emanuele Giuseppe Esposito wrote:
It seems that aio_wait_kick always required a memory barrier
or atomic operation in the caller, but nobody actually
took care of doing it.
Let's put the barrier in the function instea
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