[ Adding Joe ]
On 5/25/22 22:50, Peter Delevoryas wrote:
The AST2600/AST1030 new register mode patches[1] and the I2C slave device
patches[2] will be really useful, but we still need DMA slave device
handling in the new register mode too for the use-cases I'm thinking of
(OpenBIC Zephyr kernel u
On 5/24/2022 2:57 PM, Gerd Hoffmann wrote:
Hi,
Hmm, hooking *vm* initialization into *vcpu* creation looks wrong to me.
That's because for TDX, it has to do VM-scope (feature) initialization
before creating vcpu. This is new to KVM and QEMU, that every feature is
vcpu-scope and configured
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrangé
Cc: Thomas Huth
Cc: Cédric Le Goater
Cc: Dani
On 31/05/2022 20.28, John Snow wrote:
On Mon, May 30, 2022 at 3:33 AM Thomas Huth wrote:
On 26/05/2022 02.09, John Snow wrote:
This is needed to be able to add a venv-building step to 'make check';
the clang-user job in particular needs this to be able to run
check-unit.
Signed-off-by: John
On 5/31/22 18:49, Daniel Henrique Barboza wrote:
The unified pnv-phb-root-port can be used in its place. There is no ABI
breakage in doing so because no official QEMU release introduced user
creatable pnv-phb3-root-port devices.
Signed-off-by: Daniel Henrique Barboza
---
hw/pci-host/pnv_ph
On 6/1/22 09:27, Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
Cc: Daniel P. Berrangé
Cc: Thomas
On Wed, Jun 01, 2022 at 03:20:46PM +0800, Xiaoyao Li wrote:
> On 5/24/2022 2:57 PM, Gerd Hoffmann wrote:
> >Hi,
> > Maybe it's a bit more work to add VM-scope initialization support to
> > qemu.
>
> If just introducing VM-scope initialization to QEMU, it would be easy. What
> matters is what n
On 01.06.22 04:17, zhenwei pi wrote:
> On 5/31/22 12:08, Jue Wang wrote:
>> On Mon, May 30, 2022 at 8:49 AM Peter Xu wrote:
>>>
>>> On Mon, May 30, 2022 at 07:33:35PM +0800, zhenwei pi wrote:
A VM uses RAM of 2M huge page. Once a MCE(@HVAy in [HVAx,HVAz)) occurs, the
2M([HVAx,HVAz)) of h
On 01.06.22 02:20, Tong Zhang wrote:
> Hi David,
>
> On Mon, May 30, 2022 at 9:19 AM David Hildenbrand wrote:
>>
>> On 27.04.22 22:51, Tong Zhang wrote:
>>> assert(dbs->acb) is meant to check the return value of io_func per
>>> documented in commit 6bee44ea34 ("dma: the passed io_func does not
>>
On 6/1/22 02:56, Cédric Le Goater wrote:
On 5/31/22 23:49, Daniel Henrique Barboza wrote:
We have two very similar root-port devices, pnv-phb3-root-port and
pnv-phb4-root-port. Both consist of a wrapper around the PCIESlot device
that, until now, has no additional attributes.
The main differ
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
> On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
> > Update max alias to power10 so users can take advantage of a more
> > recent CPU model when '-cpu max' is provided.
> >
> > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038
On 5/31/22 22:43, Mark Cave-Ayland wrote:
On 31/05/2022 10:22, Damien Hedde wrote:
On 5/31/22 10:00, Mark Cave-Ayland wrote:
On 30/05/2022 15:05, Damien Hedde wrote:
On 5/30/22 12:25, Peter Maydell wrote:
On Mon, 30 May 2022 at 10:50, Damien Hedde
wrote:
TYPE_SYS_BUS_DEVICE also comes
On 01.06.22 10:39, Damien Hedde wrote:
>
>
> On 5/31/22 22:43, Mark Cave-Ayland wrote:
>> On 31/05/2022 10:22, Damien Hedde wrote:
>>
>>> On 5/31/22 10:00, Mark Cave-Ayland wrote:
On 30/05/2022 15:05, Damien Hedde wrote:
> On 5/30/22 12:25, Peter Maydell wrote:
>> On Mon, 30 May
On 01/06/2022 10.38, Greg Kurz wrote:
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided.
...
We already have the concept of d
Hello,
I am working on a qemu target under development. and I am wondering how I
should differentiate the MachineState from the MachineClass.
On 2022/5/13 下午2:28, Leonardo Bras wrote:
For CONFIG_LINUX, implement the new zero copy flag and the optional callback
io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
feature is available in the host kernel, which is checked on
qio_channel_socket_connect_sync()
qio_channel_
On Wed, 1 Jun 2022 at 07:40, John Johnson wrote:
>
> > On May 31, 2022, at 2:45 PM, Alex Williamson
> > wrote:
> >
> > On Tue, 31 May 2022 22:03:14 +0100
> > Stefan Hajnoczi wrote:
> >
> >> On Tue, 31 May 2022 at 21:11, Alex Williamson
> >> wrote:
> >>>
> >>> On Tue, 31 May 2022 15:01:57 +
On 31.05.22 20:35, Gautam Agrawal wrote:
> Add a test to check for overflow conditions in s390x.
> This patch is based on the following patches :
> * https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
> * https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
>
> Signed-off-by: G
On 24.05.22 21:02, Matthew Rosato wrote:
> The zpci-interp feature is used to specify whether zPCI interpretation is
> to be used for this guest.
We have
DEF_FEAT(SIE_PFMFI, "pfmfi", SCLP_CONF_CHAR_EXT, 9, "SIE: PFMF
interpretation facility")
and
DEF_FEAT(SIE_SIGPIF, "sigpif", SCLP_CPU, 12, "SI
On 6/1/22 06:25, Thomas Huth wrote:
On 01/06/2022 10.38, Greg Kurz wrote:
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage of a more
recent CPU model when '-cpu max' is provided
Queued, thanks.
Paolo
On 5/31/22 14:44, Igor Mammedov wrote:
Paolo,
can you pick this up if it looks fine, please?
On Tue, 24 May 2022 11:10:18 -0400
Igor Mammedov wrote:
Igor Mammedov (2):
x86: cpu: make sure number of addressable IDs for processor cores
meets the spec
x86: cpu: fixup number of addre
> + @echo " $(MAKE) check-report.junit.xml Generates an aggregated TAP test
> report"
XML now rather than TAP; tweaked and queued, thanks.
Paolo
On 5/27/22 16:27, John Snow wrote:
Paolo: I assume this falls under your jurisdiction...ish, unless Cleber
(avocado) or Alex (tests more broadly) have any specific inputs.
I'm fine with waiting for reviews, but don't know whose bucket this goes to.
I thought it was yours, but I've queued it
On Wed, 1 Jun 2022 11:25:43 +0200
Thomas Huth wrote:
> On 01/06/2022 10.38, Greg Kurz wrote:
> > On Wed, 1 Jun 2022 09:27:31 +0200
> > Thomas Huth wrote:
> >
> >> On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
> >>> Update max alias to power10 so users can take advantage of a more
> >>> re
On 5/26/22 16:34, John Snow wrote:
(1) If check is engaged without running check-venv first and iotests
creates its own venv, the python binary it uses will be whichever one is
your system default, not necessarily the one you configured your build with.
This is reasonable behavior IMO, but if
Hi Damien,
Damien Le Moal 于2022年6月1日周三 13:47写道：
>
> On 6/1/22 11:57, Sam Li wrote:
> > Hi Stefan,
> >
> > Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
> >
> >
> >>
> >> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
> >>>
> >>> Hi everyone,
> >>> I'm Sam Li, working on the Outreachy project which is to
On Tue, May 31, 2022 at 12:15:00PM -0700, Vishal Annapurve wrote:
> On Thu, May 19, 2022 at 8:41 AM Chao Peng wrote:
> >
> > Introduce a new memfd_create() flag indicating the content of the
> > created memfd is inaccessible from userspace through ordinary MMU
> > access (e.g., read/write/mmap). H
From: Song Gao
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_atomic.c.inc | 113 ++
.../loong
From: Song Gao
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
targe
From: Song Gao
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper
From: Song Gao
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 60
target/loongarch/helper.h| 9 +++
target/loongarch/insn_trans/t
From: Song Gao
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_branch.c.inc | 83 +++
target/loongarch/insns.decode
From: Song Gao
This patch gives an introduction to the LoongArch target.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
MAINTAINERS | 6 ++
target/loongarch/README | 10 ++
2 files changed, 16 insertions(+)
create mode 100644
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 230 +++
target/loongarch/cpu.h | 2 +
target/loongarch/internals.h | 2 +
3 files changed, 234 insertions(+)
diff --git a/target/loo
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c | 1 +
target/loongarch/internals.h | 2 +
target/loongarch/machine.c | 85
target/loongarch/meson.build | 6 +++
4 files changed, 94 in
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
MAINTAINERS | 8 +
docs/system/loongarch/loongson3.rst | 41 ++
target/loongarch/README | 54 +
3 files changed, 103 i
From: Song Gao
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
-
From: Song Gao
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h | 4 ++
target/loongarch/insn_trans
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
qapi/machine-target.json | 6 --
target/loongarch/cpu.c | 26 ++
2 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/qapi/machine-target.json b/qapi/machine-target.
This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/csr_helper.c | 87 ++
target/loongarch/disas.c | 101 +++
target/loongarch/helper.h
From: Song Gao
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_shift.c.inc
This patch realize PCH-MSI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
hw/intc/Kconfig | 5 ++
hw/intc/loongarch_pch_msi.c | 73 +
hw/intc/meson.build | 1
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/loongarch/loongson3.c | 45 +++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/hw/loongarch/loongson3.c b/hw/loongarch/loongson3.c
index 3c8fcb828c..658331f604 100644
--- a/hw/loongarc
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
MAINTAINERS| 1 +
hw/loongarch/Kconfig | 1 +
hw/loongarch/loongson3.c | 3 +
hw/rtc/Kconfig | 3 +
hw/rtc/ls7a_rtc.c | 528 +
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
softmmu/qdev-monitor.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c
index 12fe60c467..bb5897fc76 100644
--- a/softmmu/qdev-monitor.c
+
This patch add the irq hierarchy for the virt board.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
hw/loongarch/loongson3.c | 104 +++
1 file changed, 104 insertions(+)
diff --git a/hw/loongarch/loongson3.c b/hw/loo
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig| 3 +
hw/intc/loongarch_extioi.c | 298 +
hw/intc/meson.build| 1 +
hw/intc/trace-events
This includes:
-RDTIME{L/H}.W
-RDTIME.D
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 3 ++
target/loongarch/helper.h | 2 ++
target/loongarch/insn_trans/trans_extra.c.inc | 33 +
Hi All,
As this series only supports running binary files in ELF format, and
does not depend on BIOS and kernel file. so this series are changed from
RFC to patch vX.
The manual:
- https://github.com/loongson/LoongArch-Documentation/releases/tag/2022.03.17
Old series:
- https://patchew.or
From: Song Gao
This patch adds target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/cpu-param.h | 18 ++
target/loongarch/cpu.c
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
hw/loongarch/loongson3.c | 61 ++--
target/loongarch/cpu.h | 2 ++
2 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/hw/loongarch/loongson3.c b/hw/loongar
This patch realize the IPI interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
MAINTAINERS | 2 +
hw/intc/Kconfig | 3 +
hw/intc/loongarch_ipi.c | 242
hw/
This includes:
- TLBSRCH
- TLBRD
- TLBWR
- TLBFILL
- TLBCLR
- TLBFLUSH
- INVTLB
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 18 +
target/loongarch/helper.h | 13 +
.../insn_trans/t
This includes:
-CACOP
-LDDIR
-LDPTE
-ERTN
-DBCL
-IDLE
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/disas.c | 17
target/loongarch/helper.h | 5 +
.../insn_trans/trans_privileged.c.inc
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Acked-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
---
tests/tcg/configure.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 6
From: Song Gao
This patch adds main translation routines and
basic functions for translation.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h| 6 ++
target/loongarch/op_helper.c | 21 +
target/loongarch/translate.c
From: Song Gao
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
target/loongarch/meson.build | 19 +++
target/meson.build | 1 +
2 files changed, 20 insertions(+)
create mode 100644 target/
- We write a very minimal softmmu harness.
- This is a very simple smoke test with no need to run a full Linux/kernel.
- The Makefile.softmmu-target record the rule to run.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
MAINTAINERS
From: Song Gao
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI,
This includes:
- IOCSR{RD/WR}.{B/H/W/D}
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu.c| 44
target/loongarch/cpu.h| 25 +++
target/loongarch/disas.c
1.Add uart,virtio-net,vga and usb for 3A5000.
2.Add irq set and map for the pci host. Non pci device
use irq 0-16, pci device use 16-64.
3.Add some unimplented device to emulate guest unused
memory space.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Acked-by: Richard Henderson
---
hw/l
On 6/1/22 07:03, Greg Kurz wrote:
On Wed, 1 Jun 2022 11:25:43 +0200
Thomas Huth wrote:
On 01/06/2022 10.38, Greg Kurz wrote:
On Wed, 1 Jun 2022 09:27:31 +0200
Thomas Huth wrote:
On 31/05/2022 19.27, Murilo Opsfelder Araujo wrote:
Update max alias to power10 so users can take advantage
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
MAINTAINERS | 1 +
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 431 +
From: Song Gao
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
include/disas/dis-asm.h | 2 +
meson.build | 1 +
target/loongarch/disas.c | 610
From: Song Gao
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Rich
From: Song Gao
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 393 +++
On 01/06/2022 09:39, Damien Hedde wrote:
On 5/31/22 22:43, Mark Cave-Ayland wrote:
On 31/05/2022 10:22, Damien Hedde wrote:
On 5/31/22 10:00, Mark Cave-Ayland wrote:
On 30/05/2022 15:05, Damien Hedde wrote:
On 5/30/22 12:25, Peter Maydell wrote:
On Mon, 30 May 2022 at 10:50, Damien Hedde
On 01/06/2022 10:07, David Hildenbrand wrote:
On 01.06.22 10:39, Damien Hedde wrote:
On 5/31/22 22:43, Mark Cave-Ayland wrote:
On 31/05/2022 10:22, Damien Hedde wrote:
On 5/31/22 10:00, Mark Cave-Ayland wrote:
On 30/05/2022 15:05, Damien Hedde wrote:
On 5/30/22 12:25, Peter Maydell wrot
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-csr.h | 208 +
target/loongarch/cpu.c | 36 +++
target/loongarch/cpu.h | 64
3 files changed, 308 insertions(+)
create mod
Emulate a 3A5000 board use the new loongarch instruction.
3A5000 belongs to the Loongson3 series processors.
The board consists of a 3A5000 cpu model and the virt
bridge. The host 3A5000 board is really complicated and
contains many functions.Now for the tcg softmmu mode
only part functions are emu
ping
On 2022-05-20 11:56, Li Zhang wrote:
When no memory backend is specified in machine options,
a default memory device will be added with default_ram_id.
However, if a memory backend object is added in QEMU options
and id is the same as default_ram_id, a coredump happens.
Command line:
qem
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-param.h | 2 +-
target/loongarch/cpu.c| 24 +++
target/loongarch/cpu.h| 51 ++
target/loongarch/internals.h | 9 +
target/loongarch/machine.c| 17 ++
tar
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
target/loongarch/constant_timer.c | 64 +++
target/loongarch/cpu.c| 2 +
target/loongarch/cpu.h| 4 ++
target/loongarch/internals.h | 6 +++
target
From: Song Gao
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
.../loongarch/insn_trans/trans_fmemory.c.inc | 153 ++
target/loongarch/
On Wed, 1 Jun 2022 at 11:19, Sam Li wrote:
> Damien Le Moal 于2022年6月1日周三 13:47写道：
> > On 6/1/22 11:57, Sam Li wrote:
> > > Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
> > >> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
> > For the zone struct: You may need to add a read-write lock per zone to be
> >
On Wed, 1 Jun 2022 at 06:47, Damien Le Moal
wrote:
>
> On 6/1/22 11:57, Sam Li wrote:
> > Hi Stefan,
> >
> > Stefan Hajnoczi 于2022年5月30日周一 19:19写道：
> >
> >
> >>
> >> On Mon, 30 May 2022 at 06:09, Sam Li wrote:
> >>>
> >>> Hi everyone,
> >>> I'm Sam Li, working on the Outreachy project which is t
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
---
MAINTAINERS | 1 +
configs/targets/loongarch64-softmmu.mak | 1 +
gdb-xml/loongarch-base64.xml| 44 ++
gdb-xml/loongarch-fpu64.xml | 57 +
Cc'ing Igor
On Fri, May 20, 2022 at 11:56 AM Li Zhang wrote:
>
> When no memory backend is specified in machine options,
> a default memory device will be added with default_ram_id.
> However, if a memory backend object is added in QEMU options
> and id is the same as default_ram_id, a coredump h
From: Matheus Ferst
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian hosts is
correct; since the indexes in VRB are in PowerISA-ordering, we should
always invert the value before calling extract64. Also, using the
On Tue, May 31, 2022 at 05:52:21PM +0800, Xie Yongji wrote:
> Currently we use 'id' option as the name of VDUSE device.
> It's a bit confusing since we use one value for two different
> purposes: the ID to identfy the export within QEMU (must be
> distinct from any other exports in the same QEMU pr
Introduce a new memfd_create() flag indicating the content of the
created memfd is inaccessible from userspace through ordinary MMU
access (e.g., read/write/mmap). However, the file content can be
accessed via a different mechanism (e.g. KVM MMU) indirectly.
SEV, TDX, pkvm and software-only
On Tue, May 31, 2022 at 03:06:20AM +, Raphael Norwitz wrote:
> On Wed, May 25, 2022 at 05:00:04PM +0100, Stefan Hajnoczi wrote:
> > On Thu, May 19, 2022 at 06:39:39PM +, Raphael Norwitz wrote:
> > > On Tue, May 17, 2022 at 03:53:52PM +0200, Paolo Bonzini wrote:
> > > > On 5/16/22 19:38, Rap
On Wed, Jun 1, 2022 at 9:03 PM Stefan Hajnoczi wrote:
>
> On Tue, May 31, 2022 at 05:52:21PM +0800, Xie Yongji wrote:
> > Currently we use 'id' option as the name of VDUSE device.
> > It's a bit confusing since we use one value for two different
> > purposes: the ID to identfy the export within QE
On Wed, Jun 01, 2022 at 10:00:50AM +0200, David Hildenbrand wrote:
> On 01.06.22 02:20, Tong Zhang wrote:
> > Hi David,
> >
> > On Mon, May 30, 2022 at 9:19 AM David Hildenbrand wrote:
> >>
> >> On 27.04.22 22:51, Tong Zhang wrote:
> >>> assert(dbs->acb) is meant to check the return value of io_f
On Wed, May 25, 2022 at 09:35:24AM +0200, Klaus Jensen wrote:
>
> +stl_le_p(&n->bar.intms, 0);
> +stl_le_p(&n->bar.intmc, 0);
> +stl_le_p(&n->bar.cc, 0);
Looks fine, though it seems the NVMe spec says the above registers
should be cleared during each reset for VF as well.
On 01.06.22 15:24, Stefan Hajnoczi wrote:
> On Wed, Jun 01, 2022 at 10:00:50AM +0200, David Hildenbrand wrote:
>> On 01.06.22 02:20, Tong Zhang wrote:
>>> Hi David,
>>>
>>> On Mon, May 30, 2022 at 9:19 AM David Hildenbrand wrote:
On 27.04.22 22:51, Tong Zhang wrote:
> assert(dbs->acb
On 6/1/22 5:52 AM, David Hildenbrand wrote:
On 24.05.22 21:02, Matthew Rosato wrote:
The zpci-interp feature is used to specify whether zPCI interpretation is
to be used for this guest.
We have
DEF_FEAT(SIE_PFMFI, "pfmfi", SCLP_CONF_CHAR_EXT, 9, "SIE: PFMF
interpretation facility")
and
DEF_
Hi,
On Wed, May 25, 2022 at 08:49:19AM -0500, Andrea Bolognani wrote:
> On Wed, May 18, 2022 at 02:30:11PM +0200, Markus Armbruster wrote:
> > Victor Toso writes:
> > > IMHO, at this moment, qapi-go is targeting communicating with
> > > QEMU and handling multiple QEMU versions seems reasonable to
On Wed, 1 Jun 2022 at 14:29, David Hildenbrand wrote:
>
> On 01.06.22 15:24, Stefan Hajnoczi wrote:
> > On Wed, Jun 01, 2022 at 10:00:50AM +0200, David Hildenbrand wrote:
> >> On 01.06.22 02:20, Tong Zhang wrote:
> >>> Hi David,
> >>>
> >>> On Mon, May 30, 2022 at 9:19 AM David Hildenbrand
> >>>
On Wed, Jun 01, 2022 at 05:37:10PM +0800, 徐闯 wrote:
>
> On 2022/5/13 下午2:28, Leonardo Bras wrote:
> > For CONFIG_LINUX, implement the new zero copy flag and the optional callback
> > io_flush on QIOChannelSocket, but enables it only when MSG_ZEROCOPY
> > feature is available in the host kernel, wh
On 1/6/22 03:36, Alistair Francis wrote:
From: Alistair Francis
Since commit ad40be27 "target/riscv: Support start kernel directly by
KVM" we have been overflowing the addr_config on "M,MS..."
configurations, as reported https://gitlab.com/qemu-project/qemu/-/issues/1050.
This commit changes t
On 01.06.22 15:48, Matthew Rosato wrote:
> On 6/1/22 5:52 AM, David Hildenbrand wrote:
>> On 24.05.22 21:02, Matthew Rosato wrote:
>>> The zpci-interp feature is used to specify whether zPCI interpretation is
>>> to be used for this guest.
>>
>> We have
>>
>> DEF_FEAT(SIE_PFMFI, "pfmfi", SCLP_CONF_
On 31/05/2022 00:21, Richard Henderson wrote:
Add an interface to perform moves between TCGv_ptr.
Signed-off-by: Richard Henderson
---
This will be required for target/arm FEAT_SME.
r~
---
include/tcg/tcg-op.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/tcg/tcg-op.h b
Hi Kenneth,
On 1/6/22 11:28, Kenneth Adam Miller wrote:
Hello,
I am working on a qemu target under development. and I am wondering how
I should differentiate the MachineState from the MachineClass.
Look at QOM documentation:
https://qemu.readthedocs.io/en/latest/devel/qom.html
MachineClass
+Mark for commit ef96e3ae96.
On 1/6/22 14:53, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
The extract64 arguments are not endian dependent as they are only used
for bitwise operations. The current behavior in little-endian hosts is
correct; since the indexes in VRB are in PowerISA
Thomas Huth writes:
> On 27/05/2022 17.36, Alex Bennée wrote:
>> From: Daniel P. Berrangé
>> This converts the main build and container jobs to use the
>> base job rules, defining the following new variables
>> - QEMU_JOB_SKIPPED - jobs that are known to be currently
>> broken and should
On 6/1/22 10:10 AM, David Hildenbrand wrote:
On 01.06.22 15:48, Matthew Rosato wrote:
On 6/1/22 5:52 AM, David Hildenbrand wrote:
On 24.05.22 21:02, Matthew Rosato wrote:
The zpci-interp feature is used to specify whether zPCI interpretation is
to be used for this guest.
We have
DEF_FEAT(SI
On 25/05/2022 16.58, Eric Farman wrote:
Commit 7a523d96a0 ("virtio-ccw: move vhost_ccw_scsi to a separate file")
introduced a new file hw/s390x/vhost-scsi-ccw.c, which received a
couple comments [1][2] to update MAINTAINERS that were missed.
Fix that by making the vhost CCW entries a wildcard.
On 31/05/2022 20.35, Gautam Agrawal wrote:
Add a test to check for overflow conditions in s390x.
This patch is based on the following patches :
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=5a2e67a691501
* https://git.qemu.org/?p=qemu.git;a=commitdiff;h=fc6e0d0f2db51
Signed-off-by: Gautam Ag
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