[PATCH v1 13/33] build: clean up ninja invocation

From: Paolo Bonzini Fix an incorrect "@@:" and move "-d keepdepfile" to the NINJAFLAGS variable. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-Id: <20220517092616.1272238-3-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- Makefile | 6 +++--- 1 file changed, 3 insert

Re: [PATCH v1 10/33] tests/docker: update debian-ppc64el-cross with lcitool

On Fri, May 27, 2022 at 04:35:40PM +0100, Alex Bennée wrote: > Use lcitool to update debian-ppc64el-cross to a Debian 11 based system. > > Signed-off-by: Alex Bennée > --- > .gitlab-ci.d/container-cross.yml | 3 +- > tests/docker/Makefile.include | 1 - > .../doc

[PATCH v1 33/33] docs/devel: clean-up the CI links in the docs

There where some broken links so fix those up with proper references to the devel docs. I also did a little light copy-editing to reflect the current state and broke up a paragraph to reduce the "wall of text" effect. Signed-off-by: Alex Bennée --- docs/devel/ci-jobs.rst.inc| 2 ++ docs

Re: [PATCH v1 11/33] tests/docker: update debian-amd64 with lcitool

On Fri, May 27, 2022 at 04:35:41PM +0100, Alex Bennée wrote: > The one minor wrinkle we need to account for is the netmap support > still requires building from source. We also include cscope and GNU > global as they are used in one of the builds. > > Signed-off-by: Alex Bennée > Cc: Philippe Mat

[PATCH v1 16/33] configure, meson: move symlinking of ROMs to meson

From: Paolo Bonzini This is useful because pc-bios/meson.build already has a list of all ROM files, and thus does not need to use wildcards. The problems with wildcards are mentioned above the definition of the LINKS variable, but then the recommendation is disattended. Reviewed-by: Richard Hen

[PATCH v2 3/3] memory: fix bh-initiated dma-reentracy issues

This patch leverages the DeviceState engaged_in_io flag to prevent issues due to accesses similar to bh -> dma -> mmio. e.g. CVE-2021-3929 Signed-off-by: Alexander Bulekov --- include/hw/pci/pci.h | 13 +++-- softmmu/dma-helpers.c | 12 2 files changed, 23 insertions(+), 2

Re: [PATCH v6 0/8] Support exporting BDSs via VDUSE

Am 23.05.2022 um 10:46 hat Xie Yongji geschrieben: > Hi all, > > Last few months ago, VDUSE (vDPA Device in Userspace) [1] has > been merged into Linux kernel as a framework that make it > possible to emulate a vDPA device in userspace. This series > aimed at implementing a VDUSE block backend bas

Re: [PATCH v1 32/33] gitlab: don't run CI jobs in forks by default

On Fri, May 27, 2022 at 04:36:02PM +0100, Alex Bennée wrote: > From: Daniel P. Berrangé > > To preserve CI shared runner credits we don't want to run > pipelines on every push. > > This sets up the config so that pipelines are never created > for contributors by default. To override this the QEM

[PATCH v1 19/33] configure: add missing cross compiler fallbacks

From: Paolo Bonzini The arm compiler can be used for armeb, and the sparc64 compiler can be used for sparc. Signed-off-by: Paolo Bonzini Reviewed-by: Richard Henderson Message-Id: <20220517092616.1272238-9-pbonz...@redhat.com> Signed-off-by: Alex Bennée --- configure | 4 +++- 1 file changed

Re: [PATCH v1 08/33] tests/docker: update debian-mipsel-cross with lcitool

On Fri, May 27, 2022 at 04:35:38PM +0100, Alex Bennée wrote: > Use lcitool to update debian-mipsel-cross to a Debian 11 based system. > > Signed-off-by: Alex Bennée > --- > .gitlab-ci.d/container-cross.yml | 3 +- > tests/docker/Makefile.include | 1 - > .../dock

Re: [PATCH v4 10/17] target/m68k: Implement TRAPcc

On 5/25/22 17:15, Laurent Vivier wrote: Le 26/05/2022 à 00:26, Richard Henderson a écrit : On 5/25/22 14:40, Laurent Vivier wrote: +DISAS_INSN(trapcc) +{ +    DisasCompare c; + +    /* Consume and discard the immediate operand. */ +    switch (extract32(insn, 0, 3)) { +    case 2: /* trapcc.w *

[PATCH v1 21/33] configure: introduce --cross-prefix-*=

From: Paolo Bonzini Also in preparation for handling more binaries from the cross binutils, support an option --cross-prefix-ARCH. All cross_cc_* defaults are replaced with cross_prefix_*; the cross_cc_* fallbacks are extended to the cross-compilation prefix, but the compiler fallbacks remain as

Re: [PATCH] iotests: fix source directory location

Am 26.05.2022 um 16:21 hat John Snow geschrieben: > On Thu, May 26, 2022, 3:54 AM Daniel P. Berrangé > wrote: > > > On Wed, May 25, 2022 at 08:25:12PM -0400, John Snow wrote: > > > If you invoke the check script from outside of the tests/qemu-iotests > > > directory, the directories initialized a

[PATCH v1 31/33] gitlab: convert build/container jobs to .base_job_template

From: Daniel P. Berrangé This converts the main build and container jobs to use the base job rules, defining the following new variables - QEMU_JOB_SKIPPED - jobs that are known to be currently broken and should not be run. Can still be manually launched if desired. - QEMU_JOB_AVOCADO -

Re: [libvirt PATCH] tools: add virt-qmp-proxy for proxying QMP clients to libvirt QEMU guests

On Fri, May 27, 2022, 7:32 AM Daniel P. Berrangé wrote: > On Fri, May 27, 2022 at 12:20:39PM +0200, Peter Krempa wrote: > > On Fri, May 27, 2022 at 10:47:58 +0100, Daniel P. Berrangé wrote: > > > Libvirt provides QMP passthrough APIs for the QEMU driver and these are > > > exposed in virsh. It is

Re: [PATCH] qsd: document vduse-blk exports

Am 26.05.2022 um 13:36 hat Yongji Xie geschrieben: > On Wed, May 25, 2022 at 8:19 PM Stefan Hajnoczi wrote: > > > > Document vduse-blk exports in qemu-storage-daemon --help and the > > qemu-storage-daemon(1) man page. > > > > Based-on: <20220523084611.91-1-xieyon...@bytedance.com> > > Cc: Xie Yong

Re: [libvirt PATCH] tools: add virt-qmp-proxy for proxying QMP clients to libvirt QEMU guests

On Fri, May 27, 2022 at 12:07:55PM -0400, John Snow wrote: > On Fri, May 27, 2022, 7:32 AM Daniel P. Berrangé > wrote: > > > On Fri, May 27, 2022 at 12:20:39PM +0200, Peter Krempa wrote: > > > On Fri, May 27, 2022 at 10:47:58 +0100, Daniel P. Berrangé wrote: > > > > Libvirt provides QMP passthrou

[PATCH v2 2/3] memory: fix PIO/MMIO-initiated dma-reentracy issues

Set/check the engaged_in_io DeviceState flag, prior to calling MemoryRegion handlers. Signed-off-by: Alexander Bulekov --- softmmu/memory.c | 15 +++ softmmu/trace-events | 1 + 2 files changed, 16 insertions(+) diff --git a/softmmu/memory.c b/softmmu/memory.c index 7ba2048836.

[PATCH v2 0/3] Fix dma-reentrancy issues

A shot at fixing dma-reentrancy issues. Patch 1 adds a flag to track device IO activity to DeviceState. Patch 2 Checks/sets the flag prior to invoking MemoryRegion handlers to prevent the mmio->dma->mmio case Patch 3 Sets the flag in dma-related calls to prevent the bh->dma->mmio case The related

[PATCH v2 1/3] memory: Track whether a Device is engaged in IO

Add a flag to the DeviceState, when a device is engaged in PIO/MMIO/DMA. This flag should be set/checked prior to calling a device's MemoryRegion handlers, and set when device code initiates DMA. The purpose of this flag is to prevent DMA reentrancy issues. E.g.: sdhci pio -> dma write -> sdhci mm

Re: [PATCH v3] block/gluster: correctly set max_pdiscard

On 5/20/22 10:59, Fabian Ebner wrote: On 64-bit platforms, assigning SIZE_MAX to the int64_t max_pdiscard results in a negative value, and the following assertion would trigger Oops. Good catch! down the line (it's not the same max_pdiscard, but computed from the other one): qemu-system-x86_6

[PATCH v5 00/17] target/m68k: Conditional traps + trap cleanup

Changes for v4: - Use ILLTRP for TRAP1-TRAP14. - Use is_error for print_syscall_err. r~ v1: https://lore.kernel.org/qemu-devel/20211130103752.72099-1-richard.hender...@linaro.org/ v2: https://lore.kernel.org/qemu-devel/20211202204900.50973-1-richard.hender...@linaro.org/ v3: https://lo

[PATCH v5 01/17] target/m68k: Raise the TRAPn exception with the correct pc

Rather than adjust the PC in all of the consumers, raise the exception with the correct PC in the first place. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 1 - target/m68k/op_helper.c| 9 - target/m68k/translate.c| 2 +- 3 files

[PATCH v5 03/17] target/m68k: Fix coding style in m68k_interrupt_all

Add parenthesis around & vs &&. Remove assignment to sr in function call argument -- note that sr is unused after the call, so the assignment was never needed, only the result of the & expression. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivi

[PATCH v5 04/17] linux-user/m68k: Handle EXCP_TRAP1 through EXCP_TRAP15

These are raised by guest instructions, and should not fall through into the default abort case. Signed-off-by: Richard Henderson --- linux-user/m68k/cpu_loop.c | 4 1 file changed, 4 insertions(+) diff --git a/linux-user/m68k/cpu_loop.c b/linux-user/m68k/cpu_loop.c index 56417f7401..12e5d

[PATCH v5 07/17] target/m68k: Fix pc, c flag, and address argument for EXCP_DIV0

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Zero Div (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. While the N, Z and V flags are documented to be undefine on DIV0, the C flag is documented a

[PATCH v5 10/17] target/m68k: Implement TRAPcc

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/754 Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/cpu.h | 2 ++ linux-user/m68k/cpu_loop.c | 1 + target/m68k/cpu.c | 1 + target/m68k/op_helper.c| 6 + target/m68k/translate.c

[PATCH v5 08/17] target/m68k: Fix address argument for EXCP_TRACE

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), Trace (and others) is supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create gen_raise_exception_format2 to record the trapping pc in env->mmu.ar. Update m68k_inter

QEMU malfunctioning if built with FORTIFY_SOURCE=3

Hello Everyone! So, I'm not sure how much this would be interesting, but I thought about reporting it anyways, then let's see. A few days ago we started to build openSUSE_Tumbleweed packages with -D_FORTIFY_SOURCES=3 by default (it was =2 before, and it's back to =2 again now, at least for QEMU :

[PATCH v5 05/17] target/m68k: Remove retaddr in m68k_interrupt_all

The only value this variable holds is now env->pc. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 15 ++- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/target/m68k/op_helper.c b/target/m

[PATCH v5 11/17] target/m68k: Implement TPF in terms of TRAPcc

TPF stands for "trap false", and is a long-form nop for ColdFire. Re-use the immediate consumption code from trapcc; the insn will already expand to a nop because of the TCG_COND_NEVER test within do_trapcc. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard H

[PATCH v5 06/17] target/m68k: Fix address argument for EXCP_CHK

According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mm

[PATCH v5 12/17] target/m68k: Implement TRAPV

Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 9 + 1 file changed, 9 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index bb5ed1b7b1..0cd7ef89e3 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c

[PATCH v5 13/17] target/m68k: Implement FTRAPcc

Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/translate.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 0cd7ef89e3..a3141d7f77 100644 --- a/target/m68k/translate.c +++ b/t

[PATCH v5 09/17] target/m68k: Fix stack frame for EXCP_ILLEGAL

According to the M68040 Users Manual, section 8.4.1, Four word stack frame (format 0), includes Illegal Instruction. Use the correct frame format, which does not use the ADDR argument. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 5 - 1 file ch

[PATCH v5 02/17] target/m68k: Switch over exception type in m68k_interrupt_all

Replace an if ladder with a switch for clarity. Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/m68k/op_helper.c | 49 + 1 file changed, 30 insertions(+), 19 deletions(-) diff --git a/target/m6

[PATCH v5 16/17] linux-user/strace: Adjust get_thread_area for m68k

Unlike i386, m68k get_thread_area has no arguments. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- linux-user/strace.list | 5 + 1 file changed, 5 insertions(+) diff --git a/linux-user/strace.list b/linux-user/strace.list index 278596acd1..72e17b1acf 100644 --- a/linux-us

[PATCH v5 17/17] target/m68k: Mark helper_raise_exception as noreturn

Also mark raise_exception_ra and raise_exception, lest we generate a warning about helper_raise_exception returning. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- target/m68k/helper.h| 2 +- target/m68k/op_helper.c | 5 +++-- 2 files c

[PATCH v5 15/17] linux-user/strace: Use is_error in print_syscall_err

Errors are not all negative numbers: use is_error. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- linux-user/strace.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/linux-user/strace.c b/linux-user/strace.c index 9fa681dea9..7d882526da 100644 --- a

[PATCH 5/5] tests/acpi: update tables for new core count test

Changes in the tables (for 275 cores): FACP: + Use APIC Cluster Model (V4) : 1 APIC: +[02Ch 0044 1]Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1]

[PATCH v5 14/17] tests/tcg/m68k: Add trap.c

Test various trap instructions: chk, div, trap, trapv, trapcc, ftrapcc, and the signals and addresses that we expect from them. Reviewed-by: Laurent Vivier Signed-off-by: Richard Henderson --- tests/tcg/m68k/trap.c | 129 + tests/tcg/m68k/Makefile.target

[PATCH 1/5] hw/smbios: add core_count2 to smbios table type 4

In order to use the increased number of cpus, we need to bring smbios tables in line with the SMBIOS 3.0 specification. This allows us to introduce core_count2 which acts as a duplicate of core_count if we have fewer cores than 256, and contains the actual core number per socket if we have more. c

[PATCH] tests/tcg/i386: Use explicit suffix on fist insns

Fixes a number of assembler warnings of the form: test-i386.c: Assembler messages: test-i386.c:869: Warning: no instruction mnemonic suffix given and no register operands; using default for `fist' Signed-off-by: Richard Henderson --- tests/tcg/i386/test-i386-fp-exceptions.c | 24 -

Re: [PULL 01/15] include: move qemu_*_exec_dir() to cutils

On 5/27/22 06:54, marcandre.lur...@redhat.com wrote: From: Marc-André Lureau The function is required by get_relocated_path() (already in cutils), and used by qemu-ga and may be generally useful. Signed-off-by: Marc-André Lureau Reviewed-by: Markus Armbruster Message-Id: <20220525144140.5919

[PATCH 0/5] hw/smbios: add core_count2 to smbios table type 4

The SMBIOS 3.0 specification provides the ability to reflect over 255 cores. The 64-bit entry point has been used for a while, but structure type 4 has not been updated before, so the dmidecode output looked like this (-smp 280): Handle 0x0400, DMI type 4, 42 bytes Processor Information

[PATCH 2/5] bios-tables-test: teach test to use smbios 3.0 tables

Introduce the 64-bit entry point. Since we no longer have a total number of structures, stop checking for the new ones at the EOF structure (type 127). Signed-off-by: Julia Suvorova --- tests/qtest/bios-tables-test.c | 101 - 1 file changed, 75 insertions(+), 26 d

[PATCH 3/5] tests/acpi: allow changes for core_count2 test

Signed-off-by: Julia Suvorova --- tests/qtest/bios-tables-test-allowed-diff.h | 3 +++ tests/data/acpi/q35/APIC.core-count2| 0 tests/data/acpi/q35/DSDT.core-count2| 0 tests/data/acpi/q35/FACP.core-count2| 0 4 files changed, 3 insertions(+) create mode 100644 tests/data

Re: [PATCH v1 04/33] meson.build: fix summary display of test compilers

On 5/27/22 08:35, Alex Bennée wrote: The recent refactoring of configure.sh dropped a number of variables we relied on for printing out information. Make it simpler. Fixes: eebf199c09 (tests/tcg: invoke Makefile.target directly from QEMU's makefile) Signed-off-by: Alex Bennée --- meson.build

[PATCH 4/5] bios-tables-test: add test for number of cores > 255

The new test is run with a large number of cpus and checks if the core_count field in smbios_cpu_test (structure type 4) is correct. Choose q35 as it allows to run with -smp > 255. Signed-off-by: Julia Suvorova --- tests/qtest/bios-tables-test.c | 35 +- 1 file c

[RFC PATCH 0/3] OpenRISC Semihosting and Virt

Hello, I provide 2 options here 2 help with OpenRISC CI testing sush as the wireguard testing that Jason has been working on. The two are: 1. Add semihosting to openrisc to handle l.nop based Halt and Reset 2. Define a new virt platform, this includes widing in the sifive test device that

[RFC PATCH 1/3] target/openrisc: Add basic support for semihosting

For OpenRISC we currently only use semihosting for system exit and reset. This patch implements that. The implementation uses a helper to delegate to the semihosting facility. The helper is marked as having side effects but currently does not have any. I have defined it like this as our other u

[RFC PATCH 2/3] hw/openrisc: Split re-usable boot time apis out to boot.c

These will be shared with the virt platform. Signed-off-by: Stafford Horne --- hw/openrisc/boot.c | 127 + hw/openrisc/meson.build| 1 + hw/openrisc/openrisc_sim.c | 106 ++- include/hw/openrisc/boot.h | 34 ++

[RFC PATCH 3/3] hw/openrisc: Add the OpenRISC virtual machine

This patch add the OpenRISC virtual machine 'virt' for OpenRISC. This platform allows for a convenient CI platform for toolchain, software ports and the OpenRISC linux kernel port. Much of this has been sourced from the m68k and riscv virt platforms. The platform provides: - OpenRISC SMP with u

[PATCH 1/2] backends/tpm: Record the last command sent to the TPM

Record the last command sent to the TPM. Knowing the last command sent to a TPM 2 will allow us to determine whether we need to send a TPM2_Shutdown() command when the VM is reset. Signed-off-by: Stefan Berger --- backends/tpm/tpm_emulator.c | 9 + backends/tpm/tpm_util.c | 9 +++

[PATCH 2/2] backends/tpm: Send TPM2_Shutdown upon VM reset

Send a TPM2_Shutdown(TPM2_SU_CLEAR) command to the TPM emulator when the VM is reset. However, this is only necessary for a TPM 2 and only if the TPM2_Shutdown command has not been sent by the VM as the last command as it would do under normal circumstances. Further, it also doesn't need to be sent

[PATCH 0/2] backend/tpm: Resolve issue with TPM 2 DA lockout

This series of patches resolves an issue with a TPM 2's dictionary attack lockout logic being triggered upon well-timed VM resets. Normally, the OS TPM driver sends a TPM2_Shutdown to the TPM 2 upon reboot and before a VM is reset. However, the OS driver cannot do this when the user resets a VM. In

[PATCH v3 01/15] target/arm: Rename TBFLAG_A64 ZCR_LEN to SVE_LEN

With SME, the vector length does not only come from ZCR_ELx. Comment that this is either the SVE VL, or the Streaming SVE VL. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 ++- target/arm/helper.c| 2 +- target/arm/translate-a64.c | 2 +- 3 files changed, 4 insertio

[PATCH v3 00/15] target/arm: SME prep patches

Based-on: 20220523204742.740932-1-richard.hender...@linaro.org ("target/arm: tidy exception routing") Changes for v3: * Two patch upstream, * Have linux-user use the digested SVE_LEN from hflags (pmm) * Use el_is_in_host in sve_vqm1_for_el, mirror how I intend do use it for streaming sve

[PATCH v3 06/15] target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el

This will be used for both Normal and Streaming SVE, and the value does not necessarily come from ZCR_ELx. While we're at it, emphasize the units in which the value is returned. Patch produced by git grep -l sve_zcr_len_for_el | \ xargs -n1 sed -i 's/sve_zcr_len_for_el/sve_vqm1_for_el/g'

[PATCH v3 12/15] target/arm: Move expand_pred_b to vec_internal.h

Put the inline function near the array declaration. Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 8 +++- target/arm/sve_helper.c | 9 - 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 1d

[PATCH v3 02/15] linux-user/aarch64: Use SVE_LEN from hflags

Use the digested vector length rather than the raw zcr_el[1] value. This fixes an incorrect return from do_prctl_set_vl where we didn't take into account the set of vector lengths supported by the cpu. It also prepares us for Streaming SVE mode, where the vector length comes from a different cpreg

[PATCH v3 03/15] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset

We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2bd74c2ed..0621944167 10064

[PATCH v3 07/15] target/arm: Remove fp checks from sve_exception_el

Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Signed-off-by: Richard Henderson --- target/arm/helper.c | 56 +++-

[PATCH v3 13/15] target/arm: Use expand_pred_b in mve_helper.c

Use the function instead of the array directly. Because the function performs its own masking, via the uint8_t parameter, we need to nothing extra within the users: the bits above the first 2 (_uh) or 4 (_uw) will be discarded by assignment to the local bmask variables, and of course _uq uses the

[PATCH v3 09/15] target/arm: Use el_is_in_host for sve_vqm1_for_el

The ARM pseudocode function NVL uses this predicate now, and I think it's a bit clearer. Simplify the pseudocode condition by noting that IsInHost is always false for EL1. Signed-off-by: Richard Henderson --- target/arm/helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --gi

[PATCH v3 08/15] target/arm: Add el_is_in_host

This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c| 28 2 fi

[PATCH v3 05/15] target/arm: Use uint32_t instead of bitmap for sve vq's

The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing

[PATCH v3 10/15] target/arm: Split out load/store primitives to sve_ldst_internal.h

Begin creation of sve_ldst_internal.h by moving the primitives that access host and tlb memory. Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 127 + target/arm/sve_helper.c| 107 +-- 2 files changed, 128 inse

[PATCH 002/114] target/arm: Move null function and sve check into gen_gvec_ool_zz

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 36 +++- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index dd4a5b23ab..903514cb6a 100644 --- a/target/arm/translate-sve.c +

[PATCH 020/114] target/arm: Introduce gen_gvec_ool_arg_zpz

Use gen_gvec_ool_arg_zpz instead of gen_gvec_ool_zzp when the arguments come from arg_rpr_esz. Replaces do_zpz_ool. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 45 +- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/target/

[PATCH v3 14/15] target/arm: Move expand_pred_h to vec_internal.h

Move the data to vec_helper.c and the inline to vec_internal.h. Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 7 +++ target/arm/sve_helper.c | 29 - target/arm/vec_helper.c | 26 ++ 3 files changed, 33 insertions(+),

[PATCH v3 15/15] target/arm: Export bfdotadd from vec_helper.c

We will need this over in sme_helper.c. Signed-off-by: Richard Henderson --- target/arm/vec_internal.h | 2 ++ target/arm/vec_helper.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/vec_internal.h b/target/arm/vec_internal.h index 43cff5ec7c..5e50c503aa 100644

[PATCH v3 04/15] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller

This function is used only once, and will need modification for Streaming SVE mode. Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 --- target/arm/helper.c| 30 +++--- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git a/target/ar

[PATCH 008/114] target/arm: Move null function and sve check into gen_gvec_ool_zzzz

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 102 ++--- 1 file changed, 38 insertions(+), 64 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 6ec996e7f2..5aaef5b18f 100644 --- a/target/arm/translate-sve.c

[PATCH 022/114] target/arm: Use TRANS_FEAT for do_sve2_zpz_data

Convert SVE translation functions using do_sve2_zpz_data to use TRANS_FEAT and gen_gvec_ool_arg_zpz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 53 ++ 1 file changed, 14 insertions(+), 39 deletions(-) diff --git a/target/arm/translate-s

[PATCH v3 11/15] target/arm: Export sve contiguous ldst support functions

Export all of the support functions for performing bulk fault analysis on a set of elements at contiguous addresses controlled by a predicate. Signed-off-by: Richard Henderson --- target/arm/sve_ldst_internal.h | 94 ++ target/arm/sve_helper.c| 87 ++--

[PATCH 001/114] target/arm: Introduce TRANS, TRANS_FEAT

Steal the idea for these leaf function expanders from PowerPC. Signed-off-by: Richard Henderson --- target/arm/translate.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/target/arm/translate.h b/target/arm/translate.h index 6f0ebdc88e..9f0bb270c5 100644 --- a/target/arm/transla

[PATCH 010/114] target/arm: Introduce gen_gvec_ool_arg_zzzz

Use gen_gvec_ool_arg_ instead of gen_gvec_ool_ when the arguments come from arg__esz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 16 ++-- 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translat

[PATCH 026/114] target/arm: Introduce gen_gvec_ool_arg_zpzz

Use gen_gvec_ool_arg_zpzz instead of gen_gvec_ool_zzzp when the arguments come from arg_rprr_esz. Replaces do_zpzz_ool. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/arm/translate

[PATCH 003/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zz

Convert SVE translation functions using gen_gvec_ool_zz to TRANS_FEAT. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 39 +- 1 file changed, 13 insertions(+), 26 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sv

[PATCH 000/114] target/arm: Rewrite sve feature tests

There are SME instructions within the SVE encoding space, and technically SME does not require SVE. Thus we need to move: if (!dc_isar_feature(aa64_sve, s) || !disas_sve(s, insn)) { into each individual instruction. Use a macro trick similar to what we've been using over in target/ppc/. r

[PATCH 004/114] target/arm: Move null function and sve check into gen_gvec_ool_zzz

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 74 -- 1 file changed, 23 insertions(+), 51 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f7e7a569b7..fd1d749c0e 100644 --- a/target/arm/translate-sve.c

[PATCH 012/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzzz

Convert SVE translation functions directly using gen_gvec_ool_arg_ to TRANS_FEAT. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 47 -- 1 file changed, 10 insertions(+), 37 deletions(-) diff --git a/target/arm/translate-sve.c b/target/a

[PATCH 033/114] target/arm: Use TRANS_FEAT for gen_gvec_fn_arg_zzz

Convert SVE translation functions directly using gen_gvec_fn_arg_zzz to TRANS_FEAT. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 66 +++--- 1 file changed, 11 insertions(+), 55 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm

[PATCH 011/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_ool

Convert SVE translation functions using do_sve2__ool to use TRANS_FEAT and gen_gvec_ool_arg_. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 263 +++-- 1 file changed, 79 insertions(+), 184 deletions(-) diff --git a/target/arm/translate

[PATCH 007/114] target/arm: Use TRANS_FEAT for do_sve2_zzz_ool

Convert SVE translation functions using do_sve2_zzz_ool to use TRANS_FEAT and gen_gvec_ool_arg_zzz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 88 ++ 1 file changed, 31 insertions(+), 57 deletions(-) diff --git a/target/arm/translate-sv

[PATCH 005/114] target/arm: Introduce gen_gvec_ool_arg_zzz

Use gen_gvec_ool_arg_zzz instead of gen_gvec_ool_zzz when the arguments come from arg_rrr_esz. Replaces do_zzw_ool and do_zzz_data_ool. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 48 +- 1 file changed, 21 insertions(+), 27 deletions(-)

[PATCH 035/114] target/arm: Use TRANS_FEAT for RAX1

The decode for RAX1 sets esz to MO_8, because that's what we use by default for "no esz present". We changed that to MO_64 during translation because it is more logical for the operation. However, the esz argument to gen_gvec_rax1 is unused and forces MO_64 within that function, so there is no ne

[PATCH 017/114] target/arm: Use TRANS_FEAT for do_sve2_zzw_data

Convert SVE translation functions using do_sve2_zzw_data to use TRANS_FEAT and gen_gvec_ool_arg_zzz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 297 ++--- 1 file changed, 145 insertions(+), 152 deletions(-) diff --git a/target/arm/translate

[PATCH 006/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzz

Convert SVE translation functions using gen_gvec_ool_arg_zzz to TRANS_FEAT. Remove trivial wrappers do_aese, do_sm4. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 165 ++--- 1 file changed, 45 insertions(+), 120 deletions(-) diff --git a/targ

[PATCH 014/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zzxz

Convert SVE translation functions directly using gen_gvec_ool_arg_zzxz to TRANS_FEAT. Also include BFDOT_zzxz, which was using gen_gvec_ool_. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 48 +++--- 1 file changed, 14 insertions(+), 34 del

[PATCH 036/114] target/arm: Introduce gen_gvec_fn_arg_zzzz

Merge gen_gvec_fn_ with the sve access check and the dereference of arg__esz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 25 ++--- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-

[PATCH 009/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_zzzz

Convert SVE translation functions directly using gen_gvec_ool_ to TRANS_FEAT. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 89 +- 1 file changed, 29 insertions(+), 60 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/t

[PATCH 016/114] target/arm: Use TRANS_FEAT for do_sve2_zzzz_data

Convert SVE translation functions using do_sve2__data to use TRANS_FEAT and gen_gvec_ool_{,zzxz}. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 106 ++--- 1 file changed, 41 insertions(+), 65 deletions(-) diff --git a/target/arm/transl

[PATCH 056/114] target/arm: Use TRANS_FEAT for do_perm_pred2

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 17 +++-- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 413e89b19c..1e6bcedb9d 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/tran

[PATCH 021/114] target/arm: Use TRANS_FEAT for gen_gvec_ool_arg_zpz

Convert SVE translation functions directly using gen_gvec_ool_arg_zpz to TRANS_FEAT. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 189 - 1 file changed, 60 insertions(+), 129 deletions(-) diff --git a/target/arm/translate-sve.c b/target/a

[PATCH 015/114] target/arm: Use TRANS_FEAT for do_sve2_zzz_data

Convert SVE translation functions using do_sve2_zzz_data to use TRANS_FEAT and gen_gvec_ool_zzz. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 69 ++ 1 file changed, 25 insertions(+), 44 deletions(-) diff --git a/target/arm/translate-sve.c

[PATCH 013/114] target/arm: Rename do_zzxz_ool to gen_gvec_ool_arg_zzxz

Rename the function to match gen_gvec_ool_arg_, and move to be adjacent. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 18 +- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index f7367a

[PATCH 025/114] target/arm: Move null function and sve check into gen_gvec_ool_zzzp

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 42 -- 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 10614bf915..fea7164d72 100644 --- a/target/arm/translate-sve.c

[PATCH 058/114] target/arm: Use gen_gvec_ool_arg_zzz for do_zip, do_zip_q

Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 25 +++-- 1 file changed, 7 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index c2ced3e2bb..75c52d8ce1 100644 --- a/target/arm/translate-sve.c +++ b/target/

<    1   2   3   4   >