On Mon, 16 May 2022 at 17:47, Richard Henderson
wrote:
>
> On 5/16/22 08:46, Peter Maydell wrote:
> > On Mon, 16 May 2022 at 16:43, Thomas Huth wrote:
> >>
> >> According to
> >>
> >>
> >> https://lore.kernel.org/qemu-devel/20200921174118.39352-1-richard.hender...@linaro.org/
> >>
> >> there w
Hi Hyman Huang,
I had few doubts regarding this patch series.
1. Why we choose for dirty rate limit per vcpu. I mean it becomes very hard for
user to decide per
vcpu dirty rate limit. For e.g. we have 1Gbps network and 10 vcpu vm. Now
if someone wants to
keep criteria for convergence
qemu-plugins.symbols is now processed in Meson.
Signed-off-by: Paolo Bonzini
---
Makefile | 3 ---
1 file changed, 3 deletions(-)
diff --git a/Makefile b/Makefile
index e5fd1ebdf6..b842dbccdb 100644
--- a/Makefile
+++ b/Makefile
@@ -165,10 +165,7 @@ ifneq ($(filter $(ninja-targets), $(ninja-cmd
From: Konstantin Kostiuk
Signed-off-by: Konstantin Kostiuk
Message-Id: <20220512154906.331399-1-kkost...@redhat.com>
Signed-off-by: Paolo Bonzini
---
qga/vss-win32/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qga/vss-win32/meson.build b/qga/vss-win32/meson.bu
These messages are already emitted by scripts/meson-parse-buildoptions.sh.
Signed-off-by: Paolo Bonzini
---
configure | 4
1 file changed, 4 deletions(-)
diff --git a/configure b/configure
index dda25f05bf..0cc8c876f7 100755
--- a/configure
+++ b/configure
@@ -1043,10 +1043,6 @@ Advanced o
pSeries guests set a handful of machine capabilities on by default, all
of them related to security mitigations, that aren't always available in
the host.
This means that, as is today, running avocado in a Power9 server without
the proper firmware support, and with --disable-tcg, this error will
o
From: Konstantin Kostiuk
volume_name_wchar is allocated by 'void* operator new [](long long unsigned int)
Signed-off-by: Konstantin Kostiuk
Reviewed-by: Marc-André Lureau
Message-Id: <20220512154909.331481-1-kkost...@redhat.com>
Signed-off-by: Paolo Bonzini
---
qga/vss-win32/requester.cpp |
From: Yang Weijiang
In the first generation of Arch LBR, the max support
Arch LBR depth is 32, both host and guest use the value
to set depth MSR. This can simplify the implementation
of patch given the side-effect of mismatch of host/guest
depth MSR: XRSTORS will reset all recording MSRs to 0s
i
Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
Program conventions for vhost-user-scsi") introduced fd-passing support
as part of implementing the vhost-user backend program conventions.
When fd passing is used the UNIX domain socket path is NULL and we must
not call unlink(2
From: Yang Weijiang
The Arch LBR record MSRs and control MSRs will be migrated
to destination guest if the vcpus were running with Arch
LBR active.
Signed-off-by: Yang Weijiang
Message-Id: <20220215195258.29149-8-weijiang.y...@intel.com>
Signed-off-by: Paolo Bonzini
---
target/i386/machine.c
The ``loaded=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``loaded`` was the last option) or caused options to be
effectively ignored as if they were not given. The property is therefore
useless and was deprecated in 6.0; make it read-only now.
The patch is best
On 16/05/2022 15:43, Helge Deller wrote:
On 5/16/22 09:19, Mark Cave-Ayland wrote:
On 12/05/2022 00:50, Helge Deller wrote:
This series adds additional HP fonts to the SeaBIOS-hppa firmware.
And in the qemu artist graphics driver it:
- fixes the vertical postioning of the X11 cursor with HP-
Assigning the machine type via the avocado tag will set self.machine
from QEMUSystemTest and avoid the need to set the machine type by using
self.vm.add_args().
do_test() was changed to receive a 'machine_opts' that will allow the
aarch64 test to pass the additional '-machine gic-version=3' parame
On Mon, May 16, 2022 at 08:55:50PM +0530, manish.mishra wrote:
>
> On 26/04/22 5:08 am, Peter Xu wrote:
> > This is v5 of postcopy preempt series. It can also be found here:
> >
> >https://github.com/xzpeter/qemu/tree/postcopy-preempt
> >
> > RFC:
> > https://lore.kernel.org/qemu-devel/202
On 13/05/2022 06:45, Tsukasa OI wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
Because ext_? members are in bool type, operator `&&' s
On Mon, May 16, 2022 at 04:57:01PM +0100, Stefan Hajnoczi wrote:
> Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend
> Program conventions for vhost-user-scsi") introduced fd-passing support
> as part of implementing the vhost-user backend program conventions.
>
> When fd passin
Hey Stefan,
We've been thinking about ways to accelerate other disk types such as
SATA and IDE rather than translating to SCSI and using QEMU's iSCSI
driver, with existing and more performant backends such as SPDK. We
think there are some options worth exploring:
[1] Keep using the SCSI translati
On 14/05/2022 23:56, Tsukasa OI wrote:
[E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você possa
confirmar o remetente e saber que o conteúdo é seguro. Em caso de e-mail
suspeito entre imediatamente em contato com o DTI.
Because ext_? members are boolean variables, operator `
On 14/05/2022 23:56, Tsukasa OI wrote:
Because "G" virtual extension expands to "IMAFD", we cannot separately
disable extensions like "F" or "D" without disabling "G". Because all
"IMAFD" are enabled by default, it's harmless to disable "G" by default.
Signed-off-by: Tsukasa OI
---
target/ri
On Mon, May 16, 2022 at 12:03 PM Stefano Garzarella wrote:
>
> If the namespace does not exist, rbd_create() fails with -ENOENT and
> QEMU reports a generic "error rbd create: No such file or directory":
>
> $ qemu-img create rbd:rbd/namespace/image 1M
> Formatting 'rbd:rbd/namespace/image
Hi Paolo,
>What are the differences? Is it using the XSAVEC/XSAVES ("compacted") format?
I am not very familiar with the format internals, so I briefly checked whether
I could reuse the general logic from the HVF port. Here's what I got on a
booted Linux VM:
WHvGetVirtualProcessorXsaveState()
On Sat, May 14, 2022 at 10:54 AM Paolo Bonzini wrote:
> But I agree that blk_pwrite_zeros shouldn't be a coroutine_fn, because
> of fuse_fallocate and block_load. Alberto, this function is another
> candidate for adding a blk_co_pwrite_zeros + a matching
> generated_co_wrapper.
Thanks for the he
On 5/16/22 03:35, Michael S. Tsirkin wrote:
The following changes since commit 9de5f2b40860c5f8295e73fea9922df6f0b8d89a:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2022-05-12 10:52:15 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/
On 5/16/22 09:53, Peter Maydell wrote:
https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg07542.html
Is that this one?
https://lore.kernel.org/qemu-devel/87wo0no0wz@linaro.org/
Could well be.
Did we find out why Ubuntu's capstone in particular fell over ?
I vaguely recall that
The QEMU documentation mentions that lines should be up to 80
characters and that the script checkpatch will warn at 100 characters,
but the script warns at 80 characters and throw and error at 90, so
this commit changes to warn at 100.
As to why extend, the argument that resulted in the change of
On 16/05/2022 21.14, Richard Henderson wrote:
On 5/16/22 09:53, Peter Maydell wrote:
https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg07542.html
Is that this one?
https://lore.kernel.org/qemu-devel/87wo0no0wz@linaro.org/
Could well be.
Did we find out why Ubuntu's capstone in
On Mon, May 16, 2022 at 12:01:55PM -0700, Richard Henderson wrote:
> On 5/16/22 03:35, Michael S. Tsirkin wrote:
> > The following changes since commit 9de5f2b40860c5f8295e73fea9922df6f0b8d89a:
> >
> >Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
> > (2022-05-12 10:
On Mon, 16 May 2022 13:22:14 +0200
Juan Quintela wrote:
> Avihai Horon wrote:
> > Currently, if IOMMU of a VFIO container doesn't support dirty page
> > tracking, migration is blocked completely. This is because a DMA-able
> > VFIO device can dirty RAM pages without updating QEMU about it, thus
On Fri, Apr 01, 2022 at 09:23:22AM -0400, Jonah Palmer wrote:
> From: Laurent Vivier
>
> Display feature names instead of bitmaps for host, guest, and
> backend for VirtIODevices.
>
> Display status names instead of bitmaps for VirtIODevices.
>
> Display feature names instead of bitmaps for bac
> From: Eugenio Perez Martin
> Sent: Monday, May 16, 2022 4:51 AM
>
> On Fri, May 13, 2022 at 8:25 PM Parav Pandit wrote:
> >
> > Hi Gautam,
> >
> > Please fix your email client to have right response format.
> > Otherwise, it will be confusing for the rest and us to follow the
> conversation.
On Mon, May 16, 2022 at 11:26:03AM -0400, Igor Mammedov wrote:
> .. and clean up not longer needed conditionals in DSTD build code
> pvpanic-isa AML will be fetched and included when ISA bridge will
> build its own AML code (including attached devices).
>
> Expected AML change:
>the device und
On Mon, May 16, 2022 at 11:25:35AM -0400, Igor Mammedov wrote:
>
> Series is excerpt form larger refactoring that does
> the same for PCI devices, but it's too large at this
> point, so I've split off a relatively self-contained
> ISA/SMBUS patches into a smaller separate series, and
> PCI refacto
Changes from pull v1:
dropped introspection patches from the pull
The following changes since commit 9de5f2b40860c5f8295e73fea9922df6f0b8d89a:
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
(2022-05-12 10:52:15 -0700)
are available in the Git repository at:
From: Jason Wang
error_setg_errno() expects a normal errno value, not a negated
one, so we should use ENOTSUP instead of -ENOSUP.
Fixes: Coverity CID 1487174
Fixes: ("intel_iommu: support snoop control")
Signed-off-by: Jason Wang
Message-Id: <20220401022824.9337-1-jasow...@redhat.com>
Reviewed-
From: Halil Pasic
Unlike most virtio features ACCESS_PLATFORM is considered mandatory by
QEMU, i.e. the driver must accept it if offered by the device. The
virtio specification says that the driver SHOULD accept the
ACCESS_PLATFORM feature if offered, and that the device MAY fail to
operate if AC
From: Ben Widawsky
A CXL component is a hardware entity that implements CXL component
registers from the CXL 2.0 spec (8.2.3). Currently these represent 3
general types.
1. Host Bridge
2. Ports (root, upstream, downstream)
3. Devices (memory, other)
A CXL component can be conceptually thought of
From: Ben Widawsky
Using the previously implemented stubbed helpers, it is now possible to
easily add the missing, required commands to the implementation.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144110.25167-9-jonathan.came...
From: Ben Widawsky
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignme
From: Ben Widawsky
A CXL 2.0 component is any entity in the CXL topology. All components
have a analogous function in PCIe. Except for the CXL host bridge, all
have a PCIe config space that is accessible via the common PCIe
mechanisms. CXL components are enumerated via DVSEC fields in the
extende
From: Jonathan Cameron
There are going to be some potential overheads to CXL enablement,
for example the host bridge region reserved in memory maps.
Add a machine level control so that CXL is disabled by default.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144
From: Ben Widawsky
The easiest way to differentiate a CXL bus, and a PCIE bus is using a
flag. A CXL bus, in hardware, is backward compatible with PCIE, and
therefore the code tries pretty hard to keep them in sync as much as
possible.
The other way to implement this would be to try to cast the
From: Ben Widawsky
This works like adding a typical pxb device, except the name is
'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as
follows:
-device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1
A CXL PXB is backward compatible with PCIe. What this means in practice
is that an ope
From: Ben Widawsky
This is the beginning of implementing mailbox support for CXL 2.0
devices. The implementation recognizes when the doorbell is rung,
handles the command/payload, clears the doorbell while returning error
codes and data.
Generally the mailbox mechanism is designed to permit comm
From: Jonathan Cameron
The CXL emulation will be jointly maintained by Ben Widawsky
and Jonathan Cameron. Broken out as a separate patch
to improve visibility.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144110.25167-4-jonathan.came...@huawei.com>
---
MAINTA
From: Ben Widawsky
Errata F4 to CXL 2.0 clarified the meaning of the timer as the
sum of the value set with the timestamp set command and the number
of nano seconds since it was last set.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <2022042
From: Ben Widawsky
A CXL device is a type of CXL component. Conceptually, a CXL device
would be a leaf node in a CXL topology. From an emulation perspective,
CXL devices are the most complex and so the actual implementation is
reserved for discrete commits.
This new device type is specifically c
From: Jonathan Cameron
Initial test with just pxb-cxl. Other tests will be added
alongside functionality.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Tested-by: Alex Bennée
Message-Id: <20220429144110.25167-16-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-
From: Ben Widawsky
This opens up the possibility for more types of expanders (other than
PCI and PCIe). We'll need this to create a CXL expander.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144110.25167-12-jonathan.came...@huawei.c
From: Ben Widawsky
Memory devices implement extra capabilities on top of CXL devices. This
adds support for that.
A large part of memory devices is the mailbox/command interface. All of
the mailbox handling is done in the mailbox-utils library. Longer term,
new CXL devices that are being emulate
From: Ben Widawsky
CXL specification provides for the ability to obtain logs from the
device. Logs are either spec defined, like the "Command Effects Log"
(CEL), or vendor specific. UUIDs are defined for all log types.
The CEL is a mechanism to provide information to the host about which
command
From: Ben Widawsky
Implement get and set handlers for the Label Storage Area
used to hold data describing persistent memory configuration
so that it can be ensured it is seen in the same configuration
after reboot.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Message-Id: <202204
From: Jonathan Cameron
This adds code to instantiate the slightly extended ACPI root port
description in DSDT as per the CXL 2.0 specification.
Basically a cut and paste job from the i386/pc code.
Signed-off-by: Jonathan Cameron
Signed-off-by: Ben Widawsky
Reviewed-by: Alex Bennée
Message-Id
From: Ben Widawsky
This adds just enough of a root port implementation to be able to
enumerate root ports (creating the required DVSEC entries). What's not
here yet is the MMIO nor the ability to write some of the DVSEC entries.
This can be added with the qemu commandline by adding a rootport to
From: Ben Widawsky
CXL 2.0 specification adds 2 new dwords to the existing _OSC definition
from PCIe. The new dwords are accessed with a new uuid. This
implementation supports what is in the specification.
iasl -d decodes the result of this patch as:
Name (SUPP, Zero)
Name (CTRL, Zero)
Name (SU
From: Ben Widawsky
This should introduce no change. Subsequent work will make use of this
new class member.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-21-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. T
From: Ben Widawsky
A CXL memory device (AKA Type 3) is a CXL component that contains some
combination of volatile and persistent memory. It also implements the
previously defined mailbox interface as well as the memory device
firmware interface.
Although the memory device is configured like a no
From: Jonathan Cameron
Add exceptions for the DSDT and the new CEDT tables
specific to a new CXL test in the following patch.
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-37-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
From: Jonathan Cameron
Once a read or write reaches a CXL type 3 device, the HDM decoders
on the device are used to establish the Device Physical Address
which should be accessed. These functions peform the required maths
and then use a device specific address space to access the
hostmem->mr to
From: Jonathan Cameron
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144110.25167-23-jonathan.came...@huawei.com>
Reviewed-by: Michael S.
From: Ben Widawsky
A device's volatile and persistent memory are known Host Defined Memory
(HDM) regions. The mechanism by which the device is programmed to claim
the addresses associated with those regions is through dedicated logic
known as the HDM decoder. In order to allow the OS to properly
From: Eugenio Pérez
The device could have access to modify them, and it definitely have
access when we implement packed vq. Harden SVQ maintaining a private
copy of the descriptor chain. Other fields like buffer addresses are
already maintained sepparatedly.
Signed-off-by: Eugenio Pérez
Message
From: Ben Widawsky
CXL host bridges themselves may have MMIO. Since host bridges don't have
a BAR they are treated as special for MMIO. This patch includes
i386/pc support.
Also hook up the device reset now that we have have the MMIO
space in which the results are visible.
Note that we duplicat
From: Eugenio Pérez
Only the first one of them were properly enqueued back.
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez
Message-Id: <20220512175747.142058-3-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Ben Widawsky
GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to
info already returned in the IDENTIFY command. To have a more robust
implementation, add those.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-20-jonathan.
From: Ben Widawsky
The CXL Early Discovery Table is defined in the CXL 2.0 specification as
a way for the OS to get CXL specific information from the system
firmware.
CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host
bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware
From: Eugenio Pérez
With the introduction of MQ the index of the vq needs to be calculated
with the device model vq_index.
Signed-off-by: Eugenio Pérez
Acked-by: Jason Wang
Message-Id: <20220512175747.142058-5-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsir
From: Ben Widawsky
The CEDT CXL Fixed Window Memory Window Structures (CFMWs)
define regions of the host phyiscal address map which
(via an impdef means) are configured such that they have
a particular interleave setup across one or more CXL Host Bridges.
Reported-by: Alison Schofield
Signed-of
From: David Woodhouse
The check on x86ms->apic_id_limit in pc_machine_done() had two problems.
Firstly, we need KVM to support the X2APIC API in order to allow IRQ
delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(),
which was done elsewhere in *some* cases but not all.
Secon
From: Eugenio Pérez
Coverity rightly reports that is not free in that case.
Fixes: Coverity CID 1487559
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez
Message-Id: <20220512175747.142058-7-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signe
From: Jonathan Cameron
Both registers and the CFMWS entries in CDAT use simple encodings
for the number of interleave ways and the interleave granularity.
Introduce simple conversion functions to/from the unencoded
number / size. So far the iw decode has not been needed so is
it not implemented.
From: Jason Wang
We need check whether passthrough is enabled during
vtd_switch_address_space() by checking the context entries. This
requires the root_scalable to be set correctly otherwise we may try to
check legacy rsvd bits instead of scalable ones.
Fixing this by updating root_scalable befo
From: David Woodhouse
By setting none of the SAGAW bits we can indicate to a guest that DMA
translation isn't supported. Tested by booting Windows 10, as well as
Linux guests with the fix at https://git.kernel.org/torvalds/c/c40c10
Signed-off-by: David Woodhouse
Reviewed-by: Peter Xu
Acked
From: Jonathan Cameron
Simple function to search a PCIBus to find a port by
it's port number.
CXL interleave decoding uses the port number as a target
so it is necessary to locate the port when doing interleave
decoding.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20
From: Jonathan Cameron
The concept of these is introduced in [1] in terms of the
description the CEDT ACPI table. The principal is more general.
Unlike once traffic hits the CXL root bridges, the host system
memory address routing is implementation defined and effectively
static once observable b
From: David Woodhouse
We don't need to check kvm_enable_x2apic(). It's perfectly OK to support
interrupt remapping even if we can't address CPUs above 254. Kind of
pointless, but still functional.
The check on kvm_enable_x2apic() needs to happen *anyway* in order to
allow CPUs above 254 even wit
From: Ben Widawsky
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-35-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-b
From: Jason Wang
We need to update iq_dw according to the DMA_IRQ_REG during post
load. Otherwise we may get wrong IOTLB invalidation descriptor after
migration.
Fixes: fb43cf739e ("intel_iommu: scalable mode emulation")
Signed-off-by: Jason Wang
Message-Id: <20220317080522.14621-2-jasow...@red
From: Jonathan Cameron
Add the CFMWs memory regions to the memorymap and adjust the
PCI window to avoid hitting the same memory.
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-36-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Jonathan Cameron
Accessor to get hold of the cxl state for a CXL host bridge
without exposing the internals of the implementation.
Signed-off-by: Jonathan Cameron
Reviewed-by: Alex Bennée
Message-Id: <20220429144110.25167-32-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
S
From: David Woodhouse
We should probably check if we were meant to be exposing IR, before
letting the guest turn the IRE bit on.
Signed-off-by: David Woodhouse
Reviewed-by: Peter Xu
Acked-by: Jason Wang
Message-Id: <20220314142544.150555-3-dw...@infradead.org>
Reviewed-by: Michael S. Tsirkin
From: Paolo Bonzini
This section is using the word "back-end" to refer to the
"slave's back-end", and talking about the "client" for
what the rest of the document calls the "slave".
Rework it to free the use of the term "back-end", which in
the next patch will replace "slave".
Signed-off-by: Pa
From: Jonathan Cameron
These memops perform interleave decoding, walking down the
CXL topology from CFMWS described host interleave
decoder via CXL host bridge HDM decoders, through the CXL
root ports and finally call CXL type 3 specific read and write
functions.
Note that, whilst functional the
From: Jason Wang
This fault reason is not used and is duplicated with SPT.2 condition
code. So let's remove it.
Signed-off-by: Jason Wang
Message-Id: <20220210092815.45174-1-jasow...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
Reviewed-by: Peter Xu
---
hw/i
From: Jonathan Cameron
Tables that differ from normal Q35 tables when running the CXL test.
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-39-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
tests/qtest/bios-tables-test-all
From: Paolo Bonzini
It is not necessary to mention which side is sending/receiving
each payload; it is more interesting to say which is the request
and which is the reply. This also matches what vhost-user-gpu.rst
already does.
While at it, ensure that all messages list both the request and
the
From: Si-Wei Liu
When the control virtqueue feature is absent or not negotiated,
vhost_net_start() still tries to set up vhost_dev and install
vhost notifiers for the control virtqueue, which results in
erroneous ioctl calls with incorrect queue index sending down
to driver. Do that only when nee
From: Jonathan Cameron
The DSDT includes several CXL specific elements and the CEDT
table is only present if we enable CXL.
The test exercises all current functionality with several
CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC
entries in DSDT.
Signed-off-by: Jonathan Cameron
From: Eugenio Pérez
Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ")
Acked-by: Jason Wang
Signed-off-by: Eugenio Pérez
Message-Id: <20220512175747.142058-4-epere...@redhat.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/vhost-vdpa.c | 4
From: Si-Wei Liu
The vhost_vdpa_one_time_request() branch in
vhost_vdpa_set_backend_cap() incorrectly sends down
ioctls on vhost_dev with non-zero index. This may
end up with multiple VHOST_SET_BACKEND_FEATURES
ioctl calls sent down on the vhost-vdpa fd that is
shared between all these vhost_dev'
From: Ben Widawsky
Add CXL Fixed Memory Windows to the CXL tests.
Signed-off-by: Ben Widawsky
Co-developed-by: Jonathan Cameron
Signed-off-by: Jonathan Cameron
Message-Id: <20220429144110.25167-40-jonathan.came...@huawei.com>
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Michael S. Tsirkin
From: Jason Wang
According to vtd spec v3.3 3.14:
"""
Software must not program paging-structure entries to remap any
address to the interrupt address range. Untranslated requests and
translation requests that result in an address in the interrupt range
will be blocked with condition code LGN.4
From: Paolo Bonzini
This matches the nomenclature that is generally used. Also commonly used
is client/server, but it is not as clear because sometimes the front-end
exposes a passive (server) socket that the back-end connects to.
Signed-off-by: Paolo Bonzini
Message-Id: <20210226143413.188046
From: Jonathan Cameron
Provide an introduction to the main components of a CXL system,
with detailed explanation of memory interleaving, example command
lines and kernel configuration.
This was a challenging document to write due to the need to extract
only that subset of CXL information which i
From: Alex Bennée
These are useful when trying to debug the initial vhost-user
negotiation, especially when it hard to get logging from the low level
library on the other side.
Signed-off-by: Alex Bennée
Message-Id: <20220321153037.3622127-4-alex.ben...@linaro.org>
Reviewed-by: Michael S. Tsir
From: Alex Bennée
While writing my own VirtIO devices I've gotten confused with how
things are structured and what sort of shared infrastructure there is.
If we can document how everything is supposed to work we can then
maybe start cleaning up inconsistencies in the code.
Signed-off-by: Alex Be
From: Philippe Mathieu-Daudé
Per
https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
The old API took the size of the memory to duplicate as a guint,
whereas most memory functions take memory sizes as a gsize. This
made it easy to accidentally pass a gsize t
From: Alex Bennée
This allows other device classes that will be exposed via PCI to be
able to do so in the appropriate hw/ directory. I resisted the
temptation to re-order headers to be more aesthetically pleasing.
Signed-off-by: Alex Bennée
Message-Id: <20200925125147.26943-4-alex.ben...@linar
From: Alex Bennée
Previously we would silently suppress VHOST_USER_PROTOCOL_F_CONFIG
during the protocol negotiation if the QEMU stub hadn't implemented
the vhost_dev_config_notifier. However this isn't the only way we can
handle config messages, the existing vdc->get/set_config can do this
as we
On 5/16/22 08:37, Dr. David Alan Gilbert (git) wrote:
From: "Dr. David Alan Gilbert"
The following changes since commit 10c2a0c5e7d48e590d945c017b5b8af5b4c89a3c:
Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu
into staging (2022-05-15 16:56:27 -0700)
are availa
we switched to front-end/back-end, but newer patches
reintroduced old language. Fix this up.
Signed-off-by: Michael S. Tsirkin
---
docs/interop/vhost-user.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst
index 73e71
301 - 400 of 483 matches
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