Re: [PATCH v2 2/5] hw: aspeed: Add uarts_num SoC attribute

On 5/16/22 08:23, Peter Delevoryas wrote: AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13. Signed-off-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed_ast10x0.c | 1 + hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_soc.c

Re: [PATCH v2 0/5] hw: aspeed: Init all UART's with serial devices

On 5/16/22 08:23, Peter Delevoryas wrote: v2: - Rebased on Cedric's irq proposal. [1] - Added "Introduce common UART init function" patch - Added "Add uarts_num SoC attribute" patch - Rewrote last commit's message for clarity Looks good to me. I tried testing this by running acceptance tests,

Re: [PATCH v3 04/15] qga: flatten safe_open_or_create()

marcandre.lur...@redhat.com writes: > From: Marc-André Lureau > > There is a bit too much nesting in the function, this can be simplified > a bit to improve readability. > > This also helps with the following error handling changes. > > Signed-off-by: Marc-André Lureau > --- > qga/commands-posi

Re: [PATCH 0/6] hppa: Artist graphics driver fixes for HP-UX

On 12/05/2022 00:50, Helge Deller wrote: This series adds additional HP fonts to the SeaBIOS-hppa firmware. And in the qemu artist graphics driver it: - fixes the vertical postioning of the X11 cursor with HP-UX - allows X11 to blank the screen (e.g. screensaver) - allows the X11 driver to turn

Re: [PATCH v2 1/5] hw: aspeed: Add missing UART's

On 5/16/22 08:23, Peter Delevoryas wrote: This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030. This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later c

Re: [PATCH v2 4/5] hw: aspeed: Introduce common UART init function

On 5/16/22 08:23, Peter Delevoryas wrote: Signed-off-by: Peter Delevoryas Reviewed-by: Cédric Le Goater Thanks, C. --- hw/arm/aspeed_ast10x0.c | 7 ++- hw/arm/aspeed_ast2600.c | 7 ++- hw/arm/aspeed_soc.c | 16 include/hw/arm/aspeed_soc.h

Re: [PATCH v2 3/5] hw: aspeed: Ensure AST1030 respects uart-default

On 5/16/22 08:23, Peter Delevoryas wrote: The AST1030 machine initialization was not respecting the Aspeed SoC property "uart-default", which specifies which UART should be connected to the first serial device, it was just always connecting UART5. This doesn't change any behavior, because the def

Re: [PATCH v3 06/15] qga: use qemu_open_cloexec() for safe_open_or_create()

marcandre.lur...@redhat.com writes: > From: Marc-André Lureau > > The function takes care of setting CLOEXEC, and reporting error. > > The reported error message will differ, from: > "failed to open file 'foo' (mode: 'r')" > to: > "Failed to open file 'foo'" > > Signed-off-by: Marc-André Lure

Re: [PATCH v2 5/5] hw: aspeed: Init all UART's with serial devices

On 5/16/22 08:23, Peter Delevoryas wrote: Background: AspeedMachineClass.uart_default specifies the serial console UART, which usually corresponds to the "stdout-path" in the device tree. The default value is UART5, since most boards use UART5 for this: amc->uart_default = ASPEED_DEV_UART

[PULL 03/11] qapi: Fix comment indentation

From: Andrea Bolognani It should start on the very first column. Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster Message-Id: <20220503073737.84223-3-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster --- qapi/ui.json | 30 +++-

[PULL 06/11] qapi: Drop unnecessary empty lines outside of comments

From: Andrea Bolognani Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster Message-Id: <20220503073737.84223-6-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster --- qapi/audio.json | 1 - qapi/block-core.json | 11 --- qapi/

Re: [PATCH v3 07/15] qga: throw an Error in ga_channel_open()

marcandre.lur...@redhat.com writes: > From: Marc-André Lureau > > Allow for a single point of error reporting, and further refactoring. > > Signed-off-by: Marc-André Lureau > --- > qga/channel-posix.c | 43 ++- > 1 file changed, 18 insertions(+), 25 delet

[PULL 11/11] qapi/pragma: Tidy up comments

Commit 05ebf841ef "qapi: Enforce command naming rules" inserted new code between a comment and the code it applies to. Move the comment back to its code, and add one for the new code. Signed-off-by: Markus Armbruster Message-Id: <20220510081433.3289762-1-arm...@redhat.com> --- qapi/pragma.json

[PULL 00/11] QAPI patches patches for 2022-05-16

The following changes since commit 10c2a0c5e7d48e590d945c017b5b8af5b4c89a3c: Merge tag 'or1k-pull-request-20220515' of https://github.com/stffrdhrn/qemu into staging (2022-05-15 16:56:27 -0700) are available in the Git repository at: git://repo.or.cz/qemu/armbru.git tags/pull-qapi-2022-05-1

[PULL 10/11] docs/devel/qapi-code-gen: Belatedly document feature naming rules

Signed-off-by: Markus Armbruster Message-Id: <20220510061645.3209195-3-arm...@redhat.com> --- docs/devel/qapi-code-gen.rst | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst index 7b968433a6..cd9b544376 100644 -

[PULL 09/11] qapi/expr: Enforce feature naming rules again

Commit e42648dccd "qapi/expr.py: Remove single-letter variable" accidentally removed the check for "only lower case letters and hyphens". Restore it. Fixes: e42648dccdd1defe8f35f247966cd7283f865cd6 Signed-off-by: Markus Armbruster Message-Id: <20220510061645.3209195-2-arm...@redhat.com> --- scr

[PULL 01/11] qapi: Fix malformed "Since:" section tags

"Since X.Y" is not recognized as a tagged section, and therefore not formatted as such in generated documentation. Fix by adding the required colon. Signed-off-by: Markus Armbruster Message-Id: <20220422132807.1704411-1-arm...@redhat.com> Reviewed-by: Andrea Bolognani --- qapi/crypto.json

[PULL 04/11] qapi: Add missing separators between sections

From: Andrea Bolognani This only affects readability. The generated documentation doesn't change. Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster Message-Id: <20220503073737.84223-4-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster --- qapi/

[PULL 08/11] qapi: Stop using whitespace for alignment in comments

From: Andrea Bolognani Perfectly aligned things look pretty, but keeping them that way as the schema evolves requires churn, and in some cases newly-added lines are not aligned properly. Overall, trying to align things is just not worth the trouble. Signed-off-by: Andrea Bolognani Message-Id:

[PULL 02/11] qapi: Drop stray trailing symbol

From: Andrea Bolognani Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster Message-Id: <20220503073737.84223-2-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster --- qapi/run-state.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff -

[PULL 07/11] qapi: Drop unnecessary whitespace in comments

From: Andrea Bolognani The only instances that get changed are those in which the additional whitespace was not (or couldn't possibly be) used for alignment purposes. Signed-off-by: Andrea Bolognani Message-Id: <20220503073737.84223-7-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-

[PULL 05/11] qapi: Drop unnecessary empty lines in comments

From: Andrea Bolognani Signed-off-by: Andrea Bolognani Reviewed-by: Markus Armbruster Message-Id: <20220503073737.84223-5-abolo...@redhat.com> Reviewed-by: Markus Armbruster Signed-off-by: Markus Armbruster --- qapi/block-core.json | 4 qapi/block.json | 1 - qapi/char.json

[PATCH v2] block/nvme: separate nvme_get_free_req cases for coroutine/non-coroutine context

nvme_get_free_req has very difference semantics when called in coroutine context (when it waits) and in non-coroutine context (when it doesn't). Split the two cases to make it clear what is being requested. Cc: qemu-bl...@nongnu.org Reviewed-by: Alberto Faria Signed-off-by: Paolo Bonzini --- b

Re: [RFC PATCH] gitlab-ci: Switch the 'check-patch' & 'check-dco' jobs to use python-container

On 04/05/2022 11.20, Daniel P. Berrangé wrote: On Wed, May 04, 2022 at 11:18:30AM +0200, Thomas Huth wrote: On 04/05/2022 11.12, Daniel P. Berrangé wrote: On Tue, May 03, 2022 at 10:36:21PM +0200, Thomas Huth wrote: The 'check-patch' and 'check-dco' jobs only need Python and git for checking t

Re: [RFC PATCH 9/9] iotests: use tests/venv for running tests

On 5/14/22 17:55, John Snow wrote: On Fri, May 13, 2022, 11:33 AM Paolo Bonzini > wrote: IIRC we have some cases (FreeBSD?) where only the python3.x executable is available.  This is why we 1) default to Meson's Python 3 if neither --meson nor --python are

[PATCH v2] gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobs

The 'check-patch' and 'check-dco' jobs only need Python and git for checking the patches, so it's not really necessary to use a container here that has all the other build dependencies installed. By using a lightweight Alpine container, we can improve the runtime here quite a bit, cutting it down f

Re: [PULL 00/16] migration queue

* Leonardo Bras Soares Passos (leob...@redhat.com) wrote: > On Wed, May 11, 2022 at 5:55 AM Dr. David Alan Gilbert > wrote: > > > > * Leonardo Bras Soares Passos (leob...@redhat.com) wrote: > > > From a previous thread: > > > > > > On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert > > > wrot

Re: [PATCH v2] gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobs

On Mon, May 16, 2022 at 10:23:10AM +0200, Thomas Huth wrote: > The 'check-patch' and 'check-dco' jobs only need Python and git for > checking the patches, so it's not really necessary to use a container > here that has all the other build dependencies installed. By using a > lightweight Alpine cont

Re: [PULL 00/16] migration queue

On Wed, May 11, 2022 at 12:40:07AM -0300, Leonardo Bras Soares Passos wrote: > From a previous thread: > > On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert > wrote: > > > > Leo: > > Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY > > one I guess is the simpler one; I

Re: About restoring the state in vhost-vdpa device

On Fri, May 13, 2022 at 8:25 PM Parav Pandit wrote: > > Hi Gautam, > > Please fix your email client to have right response format. > Otherwise, it will be confusing for the rest and us to follow the > conversation. > > More below. > > > From: Gautam Dawar > > Sent: Friday, May 13, 2022 1:48 PM >

[PATCH v3 0/8] qmp, hmp: statistics subsystem and KVM suport.

This patchset adds QEMU support for querying fd-based KVM statistics. This allows the user to analyze the behavior of the VM without access to debugfs. However, instead of adding an ad hoc command, the new QMP entry point can be extended in the future to more statistics provider than KVM (for exam

[PATCH v3 1/8] qmp: Support for querying stats

From: Mark Kanda Gathering statistics is important for development, for monitoring and for performance measurement. There are tools such as kvm_stat that do this and they rely on the _user_ knowing the interesting data points rather than the tool (which can treat them as opaque). The commands i

[PATCH v3 3/8] qmp: add filtering of statistics by target vCPU

Introduce a simple filtering of statistics, that allows to retrieve statistics for a subset of the guest vCPUs. This will be used for example by the HMP monitor, in order to retrieve the statistics for the currently selected CPU. Example: { "execute": "query-stats", "arguments": { "target":

[PATCH v3 6/8] hmp: add filtering of statistics by provider

Allow the user to request statistics for a single provider of interest. Extracted from a patch by Mark Kanda. Signed-off-by: Paolo Bonzini --- hmp-commands-info.hx | 7 --- monitor/hmp-cmds.c | 41 ++--- 2 files changed, 38 insertions(+), 10 deletions(-

[PATCH v3 2/8] kvm: Support for querying fd-based stats

From: Mark Kanda Add support for querying fd-based KVM stats - as introduced by Linux kernel commit: cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data") This allows the user to analyze the behavior of the VM without access to debugfs. Signed-off-by: Mark Kanda Signed-off-b

[PATCH v3 2/8] kvm: Support for querying fd-based stats

From: Mark Kanda Add support for querying fd-based KVM stats - as introduced by Linux kernel commit: cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data") This allows the user to analyze the behavior of the VM without access to debugfs. Signed-off-by: Mark Kanda Signed-off-b

[PATCH v3 5/8] qmp: add filtering of statistics by provider

Allow retrieving the statistics from a specific provider only. This can be used in the future by HMP commands such as "info sync-profile" or "info profile". The next patch also adds filter-by-provider capabilities to the HMP equivalent of query-stats, "info stats". Example: { "execute": "query-s

[PATCH v3 7/8] qmp: add filtering of statistics by name

Allow retrieving only a subset of statistics. This can be useful for example in order to plot a subset of the statistics many times a second. KVM publishes ~40 statistics for each vCPU on x86; retrieving and serializing all of them would be useless Another use will be in HMP in the following pat

[PATCH v3 4/8] hmp: add basic "info stats" implementation

From: Mark Kanda Add an HMP command to retrieve statistics collected at run-time. The command will retrieve and print either all VM-level statistics, or all vCPU-level statistics for the currently selected CPU. Signed-off-by: Paolo Bonzini --- hmp-commands-info.hx | 13 +++ include/monitor/h

[PATCH v3 8/8] hmp: add filtering of statistics by name

Allow the user to request only a specific subset of statistics. This can be useful when working on a feature or optimization that is known to affect that statistic. Extracted from a patch by Mark Kanda. Signed-off-by: Paolo Bonzini --- hmp-commands-info.hx | 8 monitor/hmp-cmds.c |

Re: [PULL 00/16] migration queue

On Mon, May 16, 2022 at 09:51:12AM +0100, Stefan Hajnoczi wrote: > On Wed, May 11, 2022 at 12:40:07AM -0300, Leonardo Bras Soares Passos wrote: > > From a previous thread: > > > > On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert > > wrote: > > > > > > Leo: > > > Unfortunately this is fail

KVM call for 2022-05-17th

Hi I know it is a bit late for the call for topics, but it appears that there are people who wants to discuss live migration improvements. If we got an agenda, can we have a call tomorrow? Please, send any topic that you are interested in covering. At the end of Monday I will send an email w

Re: [PATCH v1 2/4] xlnx_dp: Introduce a vblank signal

On Tue, 3 May 2022 at 16:27, wrote: > > From: Sai Pavan Boddu > > Add a periodic timer which raises vblank at a frequency of 30Hz. > > Signed-off-by: Sai Pavan Boddu > Signed-off-by: Edgar E. Iglesias > Changes by fkonrad: > - Switched to transaction-based ptimer API. > - Added the DP_INT_V

[PATCH] block/rbd: report a better error when namespace does not exist

If the namespace does not exist, rbd_create() fails with -ENOENT and QEMU reports a generic "error rbd create: No such file or directory": $ qemu-img create rbd:rbd/namespace/image 1M Formatting 'rbd:rbd/namespace/image', fmt=raw size=1048576 qemu-img: rbd:rbd/namespace/image: error rb

Re: [PATCH 2/2] migration: Calculate ram size once

David Hildenbrand wrote: > On 11.05.22 01:17, Juan Quintela wrote: >> We are recalculating ram size continously, when we know that it don't >> change during migration. Create a field in RAMState to track it. Hi > We do have resizable RAM, which triggers ram_mig_ram_block_resized() on > resizes

Re: [PULL 00/16] migration queue

On Mon, May 16, 2022 at 10:40:15AM +0100, Daniel P. Berrangé wrote: > On Mon, May 16, 2022 at 09:51:12AM +0100, Stefan Hajnoczi wrote: > > On Wed, May 11, 2022 at 12:40:07AM -0300, Leonardo Bras Soares Passos wrote: > > > From a previous thread: > > > > > > On Thu, Apr 28, 2022 at 1:20 PM Dr. Davi

[PATCH] ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY

The traditional ptimer behaviour includes a collection of weird edge case behaviours. In 2016 we improved the ptimer implementation to fix these and generally make the behaviour more flexible, with ptimers opting in to the new behaviour by passing an appropriate set of policy flags to ptimer_init(

[PULL 00/91] virtio,pc,pci: fixes,cleanups,features

The following changes since commit 9de5f2b40860c5f8295e73fea9922df6f0b8d89a: Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging (2022-05-12 10:52:15 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_upstream for

[PULL 01/91] virtio: fix feature negotiation for ACCESS_PLATFORM

From: Halil Pasic Unlike most virtio features ACCESS_PLATFORM is considered mandatory by QEMU, i.e. the driver must accept it if offered by the device. The virtio specification says that the driver SHOULD accept the ACCESS_PLATFORM feature if offered, and that the device MAY fail to operate if AC

[PULL 02/91] intel-iommu: correct the value used for error_setg_errno()

From: Jason Wang error_setg_errno() expects a normal errno value, not a negated one, so we should use ENOTSUP instead of -ENOSUP. Fixes: Coverity CID 1487174 Fixes: ("intel_iommu: support snoop control") Signed-off-by: Jason Wang Message-Id: <20220401022824.9337-1-jasow...@redhat.com> Reviewed-

[PULL 05/91] MAINTAINERS: Add entry for Compute Express Link Emulation

From: Jonathan Cameron The CXL emulation will be jointly maintained by Ben Widawsky and Jonathan Cameron. Broken out as a separate patch to improve visibility. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-4-jonathan.came...@huawei.com> --- MAINTA

[PULL 03/91] hw/pci/cxl: Add a CXL component type (interface)

From: Ben Widawsky A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of

[PULL 06/91] hw/cxl/device: Introduce a CXL device (8.2.8)

From: Ben Widawsky A CXL device is a type of CXL component. Conceptually, a CXL device would be a leaf node in a CXL topology. From an emulation perspective, CXL devices are the most complex and so the actual implementation is reserved for discrete commits. This new device type is specifically c

[PULL 04/91] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)

From: Ben Widawsky A CXL 2.0 component is any entity in the CXL topology. All components have a analogous function in PCIe. Except for the CXL host bridge, all have a PCIe config space that is accessible via the common PCIe mechanisms. CXL components are enumerated via DVSEC fields in the extende

[PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only.

From: Jonathan Cameron Initial test with just pxb-cxl. Other tests will be added alongside functionality. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Tested-by: Alex Bennée Message-Id: <20220429144110.25167-16-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-

[PULL 08/91] hw/cxl/device: Implement basic mailbox (8.2.8.4)

From: Ben Widawsky This is the beginning of implementing mailbox support for CXL 2.0 devices. The implementation recognizes when the doorbell is rung, handles the command/payload, clears the doorbell while returning error codes and data. Generally the mailbox mechanism is designed to permit comm

[PULL 10/91] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1)

From: Ben Widawsky Using the previously implemented stubbed helpers, it is now possible to easily add the missing, required commands to the implementation. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-9-jonathan.came...

[PULL 07/91] hw/cxl/device: Implement the CAP array (8.2.8.1-2)

From: Ben Widawsky This implements all device MMIO up to the first capability. That includes the CXL Device Capabilities Array Register, as well as all of the CXL Device Capability Header Registers. The latter are filled in as they are implemented in the following patches. Endianness and alignme

[PULL 18/91] hw/cxl/rp: Add a root port

From: Ben Widawsky This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to

[PULL 11/91] hw/cxl/device: Timestamp implementation (8.2.9.3)

From: Ben Widawsky Errata F4 to CXL 2.0 clarified the meaning of the timer as the sum of the value set with the timestamp set command and the number of nano seconds since it was last set. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <2022042

[PULL 09/91] hw/cxl/device: Add memory device utilities

From: Ben Widawsky Memory devices implement extra capabilities on top of CXL devices. This adds support for that. A large part of memory devices is the mailbox/command interface. All of the mailbox handling is done in the mailbox-utils library. Longer term, new CXL devices that are being emulate

[PULL 13/91] hw/pxb: Use a type for realizing expanders

From: Ben Widawsky This opens up the possibility for more types of expanders (other than PCI and PCIe). We'll need this to create a CXL expander. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-12-jonathan.came...@huawei.c

RE: [PATCH v1 2/4] xlnx_dp: Introduce a vblank signal

> -Original Message- > From: Peter Maydell > Sent: 16 May 2022 10:57 > To: Frederic Konrad > Cc: qemu-devel@nongnu.org; alist...@alistair23.me; > edgar.igles...@gmail.com; qemu-...@nongnu.org; Sai Pavan Boddu > ; Edgar Iglesias ; > fkon...@amd.com; Sai Pavan Boddu ; Edgar Iglesias > >

[PULL 12/91] hw/cxl/device: Add log commands (8.2.9.4) + CEL

From: Ben Widawsky CXL specification provides for the ability to obtain logs from the device. Logs are either spec defined, like the "Command Effects Log" (CEL), or vendor specific. UUIDs are defined for all log types. The CEL is a mechanism to provide information to the host about which command

[PULL 21/91] hw/cxl/device: Add some trivial commands

From: Ben Widawsky GET_FW_INFO and GET_PARTITION_INFO, for this emulation, is equivalent to info already returned in the IDENTIFY command. To have a more robust implementation, add those. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-20-jonathan.

[PULL 28/91] hw/cxl/component: Add utils for interleave parameter encoding/decoding

From: Jonathan Cameron Both registers and the CFMWS entries in CDAT use simple encodings for the number of interleave ways and the interleave granularity. Introduce simple conversion functions to/from the unencoded number / size. So far the iw decode has not been needed so is it not implemented.

[PULL 20/91] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12)

From: Ben Widawsky A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly

[PULL 14/91] hw/pci/cxl: Create a CXL bus type

From: Ben Widawsky The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the

[PULL 23/91] hw/cxl/device: Implement get/set Label Storage Area (LSA)

From: Ben Widawsky Implement get and set handlers for the Label Storage Area used to hold data describing persistent memory configuration so that it can be ensured it is seen in the same configuration after reboot. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Message-Id: <202204

[PULL 26/91] acpi/cxl: Add _OSC implementation (9.14.2)

From: Ben Widawsky CXL 2.0 specification adds 2 new dwords to the existing _OSC definition from PCIe. The new dwords are accessed with a new uuid. This implementation supports what is in the specification. iasl -d decodes the result of this patch as: Name (SUPP, Zero) Name (CTRL, Zero) Name (SU

[PULL 29/91] hw/cxl/host: Add support for CXL Fixed Memory Windows.

From: Jonathan Cameron The concept of these is introduced in [1] in terms of the description the CEDT ACPI table. The principal is more general. Unlike once traffic hits the CXL root bridges, the host system memory address routing is implementation defined and effectively static once observable b

[PULL 15/91] cxl: Machine level control on whether CXL support is enabled

From: Jonathan Cameron There are going to be some potential overheads to CXL enablement, for example the host bridge region reserved in memory maps. Add a machine level control so that CXL is disabled by default. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144

[PULL 25/91] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142)

From: Ben Widawsky CXL host bridges themselves may have MMIO. Since host bridges don't have a BAR they are treated as special for MMIO. This patch includes i386/pc support. Also hook up the device reset now that we have have the MMIO space in which the results are visible. Note that we duplicat

[PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests

From: Jonathan Cameron At this stage we can boot configurations with host bridges, root ports and type 3 memory devices, so add appropriate tests. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-23-jonathan.came...@huawei.com> Reviewed-by: Michael S.

[PULL 27/91] acpi/cxl: Create the CEDT (9.14.1)

From: Ben Widawsky The CXL Early Discovery Table is defined in the CXL 2.0 specification as a way for the OS to get CXL specific information from the system firmware. CXL 2.0 specification adds an _HID, ACPI0016, for CXL capable host bridges, with a _CID of PNP0A08 (PCIe host bridge). CXL aware

[PULL 30/91] acpi/cxl: Introduce CFMWS structures in CEDT

From: Ben Widawsky The CEDT CXL Fixed Window Memory Window Structures (CFMWs) define regions of the host phyiscal address map which (via an impdef means) are configured such that they have a particular interleave setup across one or more CXL Host Bridges. Reported-by: Alison Schofield Signed-of

[PULL 16/91] hw/pxb: Allow creation of a CXL PXB (host bridge)

From: Ben Widawsky This works like adding a typical pxb device, except the name is 'pxb-cxl' instead of 'pxb-pcie'. An example command line would be as follows: -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1 A CXL PXB is backward compatible with PCIe. What this means in practice is that an ope

[PULL 31/91] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl

From: Jonathan Cameron This adds code to instantiate the slightly extended ACPI root port description in DSDT as per the CXL 2.0 specification. Basically a cut and paste job from the i386/pc code. Signed-off-by: Jonathan Cameron Signed-off-by: Ben Widawsky Reviewed-by: Alex Bennée Message-Id

[PULL 35/91] cxl/cxl-host: Add memops for CFMWS region.

From: Jonathan Cameron These memops perform interleave decoding, walking down the CXL topology from CFMWS described host interleave decoder via CXL host bridge HDM decoders, through the CXL root ports and finally call CXL type 3 specific read and write functions. Note that, whilst functional the

[PULL 36/91] hw/cxl/component Add a dumb HDM decoder handler

From: Ben Widawsky Add a trivial handler for now to cover the root bridge where we could do some error checking in future. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-35-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-b

[PULL 33/91] CXL/cxl_component: Add cxl_get_hb_cstate()

From: Jonathan Cameron Accessor to get hold of the cxl state for a CXL host bridge without exposing the internals of the implementation. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20220429144110.25167-32-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin S

[PULL 19/91] hw/cxl/device: Add a memory device (8.2.8.5)

From: Ben Widawsky A CXL memory device (AKA Type 3) is a CXL component that contains some combination of volatile and persistent memory. It also implements the previously defined mailbox interface as well as the memory device firmware interface. Although the memory device is configured like a no

[PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing

From: Ben Widawsky This should introduce no change. Subsequent work will make use of this new class member. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-21-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. T

[PULL 37/91] i386/pc: Enable CXL fixed memory windows

From: Jonathan Cameron Add the CFMWs memory regions to the memorymap and adjust the PCI window to avoid hitting the same memory. Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-36-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL 34/91] mem/cxl_type3: Add read and write functions for associated hostmem.

From: Jonathan Cameron Once a read or write reaches a CXL type 3 device, the HDM decoders on the device are used to establish the Device Physical Address which should be accessed. These functions peform the required maths and then use a device specific address space to access the hostmem->mr to

[PULL 44/91] vhost: Fix device's used descriptor dequeue

From: Eugenio Pérez Only the first one of them were properly enqueued back. Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding") Signed-off-by: Eugenio Pérez Message-Id: <20220512175747.142058-3-epere...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn()

From: Jonathan Cameron Simple function to search a PCIBus to find a port by it's port number. CXL interleave decoding uses the port number as a target so it is necessary to locate the port when doing interleave decoding. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Bennée Message-Id: <20

[PULL 40/91] tests/acpi: Add tables for CXL emulation.

From: Jonathan Cameron Tables that differ from normal Q35 tables when running the CXL test. Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-39-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- tests/qtest/bios-tables-test-all

[PULL 41/91] qtest/cxl: Add more complex test cases with CFMWs

From: Ben Widawsky Add CXL Fixed Memory Windows to the CXL tests. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-40-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin

[PULL 47/91] hw/virtio: Replace g_memdup() by g_memdup2()

From: Philippe Mathieu-Daudé Per https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538 The old API took the size of the memory to duplicate as a guint, whereas most memory functions take memory sizes as a gsize. This made it easy to accidentally pass a gsize t

[PULL 49/91] target/i386: Fix sanity check on max APIC ID / X2APIC enablement

From: David Woodhouse The check on x86ms->apic_id_limit in pc_machine_done() had two problems. Firstly, we need KVM to support the X2APIC API in order to allow IRQ delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(), which was done elsewhere in *some* cases but not all. Secon

[PULL 38/91] tests/acpi: q35: Allow addition of a CXL test.

From: Jonathan Cameron Add exceptions for the DSDT and the new CEDT tables specific to a new CXL test in the following patch. Signed-off-by: Jonathan Cameron Message-Id: <20220429144110.25167-37-jonathan.came...@huawei.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin ---

[PULL 42/91] docs/cxl: Add initial Compute eXpress Link (CXL) documentation.

From: Jonathan Cameron Provide an introduction to the main components of a CXL system, with detailed explanation of memory interleaving, example command lines and kernel configuration. This was a challenging document to write due to the need to extract only that subset of CXL information which i

[PULL 50/91] intel_iommu: Support IR-only mode without DMA translation

From: David Woodhouse By setting none of the SAGAW bits we can indicate to a guest that DMA translation isn't supported. Tested by booting Windows 10, as well as Linux guests with the fix at https://git.kernel.org/torvalds/c/c40c10 Signed-off-by: David Woodhouse Reviewed-by: Peter Xu Acked

[PULL 48/91] vhost: Fix element in vhost_svq_add failure

From: Eugenio Pérez Coverity rightly reports that is not free in that case. Fixes: Coverity CID 1487559 Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding") Signed-off-by: Eugenio Pérez Message-Id: <20220512175747.142058-7-epere...@redhat.com> Reviewed-by: Michael S. Tsirkin Signe

[PULL 39/91] qtests/bios-tables-test: Add a test for CXL emulation.

From: Jonathan Cameron The DSDT includes several CXL specific elements and the CEDT table is only present if we enable CXL. The test exercises all current functionality with several CFMWS, CHBS structures in CEDT and ACPI0016/ACPI00017 and _OSC entries in DSDT. Signed-off-by: Jonathan Cameron

[PULL 43/91] vhost: Track descriptor chain in private at SVQ

From: Eugenio Pérez The device could have access to modify them, and it definitely have access when we implement packed vq. Harden SVQ maintaining a private copy of the descriptor chain. Other fields like buffer addresses are already maintained sepparatedly. Signed-off-by: Eugenio Pérez Message

[PULL 51/91] intel_iommu: Only allow interrupt remapping to be enabled if it's supported

From: David Woodhouse We should probably check if we were meant to be exposing IR, before letting the guest turn the IRE bit on. Signed-off-by: David Woodhouse Reviewed-by: Peter Xu Acked-by: Jason Wang Message-Id: <20220314142544.150555-3-dw...@infradead.org> Reviewed-by: Michael S. Tsirkin

[PULL 53/91] intel-iommu: remove VTD_FR_RESERVED_ERR

From: Jason Wang This fault reason is not used and is duplicated with SPT.2 condition code. So let's remove it. Signed-off-by: Jason Wang Message-Id: <20220210092815.45174-1-jasow...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin Reviewed-by: Peter Xu --- hw/i

[PULL 45/91] vdpa: Fix bad index calculus at vhost_vdpa_get_vring_base

From: Eugenio Pérez Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ") Acked-by: Jason Wang Signed-off-by: Eugenio Pérez Message-Id: <20220512175747.142058-4-epere...@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- hw/virtio/vhost-vdpa.c | 4

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