[PATCH v13 6/8] multifd: multifd_send_sync_main now returns negative on error

Even though multifd_send_sync_main() currently emits error_reports, it's callers don't really check it before continuing. Change multifd_send_sync_main() to return -1 on error and 0 on success. Also change all it's callers to make use of this change and possibly fail earlier. (This change is impo

Re: [PATCH v2] block/gluster: correctly set max_pdiscard

Am 12.05.22 um 18:05 schrieb Stefano Garzarella: > On Thu, May 12, 2022 at 05:44:13PM +0200, Stefano Garzarella wrote: >> On Thu, May 12, 2022 at 12:30:48PM +0200, Fabian Ebner wrote: >>> On 64-bit platforms, SIZE_MAX is too large for max_pdiscard, which is >> >> The main problem is that SIZE_MAX f

Re: [PATCH 0/9] vfio/migration: Implement VFIO migration protocol v2

On Thu, May 12 2022, Alex Williamson wrote: > On Thu, 12 May 2022 18:43:11 +0300 > Avihai Horon wrote: > >> Hello, >> >> Following VFIO migration protocol v2 acceptance in kernel, this series >> implements VFIO migration according to the new v2 protocol and replaces >> the now deprecated v1 imp

[PATCH v13 8/8] multifd: Implement zero copy write in multifd migration (multifd-zero-copy)

Implement zero copy send on nocomp_send_write(), by making use of QIOChannel writev + flags & flush interface. Change multifd_send_sync_main() so flush_zero_copy() can be called after each iteration in order to make sure all dirty pages are sent before a new iteration is started. It will also flus

Re: [PATCH] qga-vss: Add auto generated headers to dependencies

Queued, thanks. Paolo

Re: [PATCH] qga-vss: Use a proper function for free memory

Queued, thanks. Paolo

Re: [PATCH v5 3/4] vdpa: add vdpa-dev support

On Fri, May 13, 2022 at 10:17:41AM +0800, Longpeng (Mike, Cloud Infrastructure Service Product Dept.) wrote: 在 2022/5/12 22:36, Stefano Garzarella 写道: On Thu, May 12, 2022 at 02:21:02PM +0800, Longpeng(Mike) wrote: From: Longpeng Supports vdpa-dev, we can use the deivce directly: -M micro

Re: [PATCH 2/9] vfio: Fix compilation errors caused by VFIO migration v1 deprecation

On Thu, May 12 2022, Alex Williamson wrote: > On Thu, 12 May 2022 18:43:13 +0300 > Avihai Horon wrote: > >> @@ -767,9 +767,10 @@ static void vfio_migration_state_notifier(Notifier >> *notifier, void *data) >> case MIGRATION_STATUS_CANCELLED: >> case MIGRATION_STATUS_FAILED: >>

Re: [PATCH 7/7] block: Add bdrv_co_pwrite_sync()

On 5/13/22 01:51, Alberto Faria wrote: Also convert bdrv_pwrite_sync() to being implemented using generated_co_wrapper. Signed-off-by: Alberto Faria --- block/io.c | 5 +++-- include/block/block-io.h | 8 ++-- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/

Re: [PULL v2 18/24] ACPI ERST: support for ACPI ERST feature

On Thu, May 12, 2022 at 9:59 PM Peter Maydell wrote: > > On Sun, 6 Feb 2022 at 09:38, Michael S. Tsirkin wrote: > > > > From: Eric DeVolder > > > > This implements a PCI device for ACPI ERST. This implements the > > non-NVRAM "mode" of operation for ERST as it is supported by > > Linux and Windo

Re: [PATCH 5/7] block: Make 'bytes' param of bdrv_co_{pread, pwrite, preadv, pwritev}() an int64_t

On 5/13/22 01:51, Alberto Faria wrote: For consistency with other I/O functions, and in preparation to implement bdrv_{pread,pwrite}() using generated_co_wrapper. unsigned int fits in int64_t, so all callers remain correct. Reviewed-by: Paolo Bonzini Signed-off-by: Alberto Faria --- bloc

Re: [PATCH 1/7] block: Add a 'flags' param to bdrv_{pread, pwrite, pwrite_sync}()

On 5/13/22 01:38, Alberto Faria wrote: For consistency with other I/O functions, and in preparation to implement them using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression child, offset, buf, bytes; @@ - bdrv_pread(child, offset, buf, bytes)

Re: [PATCH 4/7] block: Make bdrv_co_pwrite() take a const buffer

On 5/13/22 01:51, Alberto Faria wrote: It does not mutate the buffer. Signed-off-by: Alberto Faria --- include/block/block_int-io.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/block/block_int-io.h b/include/block/block_int-io.h index bb454200e5..d4d3bed783 100

Re: [PATCH 2/7] block: Change bdrv_{pread, pwrite, pwrite_sync}() param order

On 5/13/22 01:38, Alberto Faria wrote: Swap 'buf' and 'bytes' around for consistency with bdrv_co_{pread,pwrite}(), and in preparation to implement these functions using generated_co_wrapper. Callers were updated using this Coccinelle script: @@ expression child, offset, buf, bytes, flags;

Re: [PATCH 6/7] block: Implement bdrv_{pread, pwrite, pwrite_zeroes}() using generated_co_wrapper

On 5/13/22 01:51, Alberto Faria wrote: Signed-off-by: Alberto Faria --- block/io.c | 41 include/block/block-io.h | 15 +-- 2 files changed, 9 insertions(+), 47 deletions(-) diff --git a/block/io.c b/block/io.c index 78a2891

Re: [RFC PATCH qemu] spapr/docs: Add a few words about x-vof

On 5/12/22 23:40, Daniel Henrique Barboza wrote: On 5/12/22 00:10, Alexey Kardashevskiy wrote: On 5/12/22 06:42, Daniel Henrique Barboza wrote: On 5/6/22 02:51, Alexey Kardashevskiy wrote: The alternative small firmware needs a few words of what it can and absolutely cannot do; this a

Re: [PATCH v5 10/10] test: tpm-tis: Add Sysbus TPM-TIS device test

On Thu, 12 May 2022 17:05:41 +0100 Peter Maydell wrote: > On Thu, 12 May 2022 at 16:59, Eric Auger wrote: > > > > Hi Peter, > > > > On 5/12/22 15:08, Peter Maydell wrote: > > > On Thu, 5 Mar 2020 at 16:52, Eric Auger wrote: > > >> The tests themselves are the same as the ISA device ones. >

Re: [PATCH 3/7] block: Make bdrv_{pread, pwrite}() return 0 on success

On 5/13/22 01:38, Alberto Faria wrote: @@ -113,7 +113,7 @@ static ssize_t qcow2_crypto_hdr_read_func(QCryptoBlock *block, size_t offset, error_setg_errno(errp, -ret, "Could not read encryption header"); return -1; } -return ret; +return buflen; } @@ -174,7 +1

Re: [RFC PATCH 2/9] tests: add "TESTS_PYTHON" variable to Makefile

On 5/13/22 02:06, John Snow wrote: This is a convenience feature: $(PYTHON) points to the Python executable we were instructed to use by the configure script. We use that Python to create a virtual environment with the "check-venv" target in tests/Makefile.include. $(TESTS_PYTHON) points to the

Re: [RFC PATCH 3/9] tests: install "qemu" namespace package into venv

On 5/13/22 02:06, John Snow wrote: diff --git a/tests/requirements.txt b/tests/requirements.txt index a21b59b4439..0ba561b6bdf 100644 --- a/tests/requirements.txt +++ b/tests/requirements.txt @@ -1,5 +1,6 @@ # Add Python module requirements, one per line, to be installed # in the tests/venv P

Re: [RFC PATCH 4/9] tests: silence pip upgrade warnings during venv creation

On 5/13/22 02:06, John Snow wrote: diff --git a/tests/Makefile.include b/tests/Makefile.include index dbbf1ba535b..dfb678d379f 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -109,11 +109,11 @@ $(TESTS_VENV_DIR): $(TESTS_VENV_REQ) $(SRC_PATH)/python/setup.cfg $(P

Re: [PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

On 2022/5/10 上午1:56, Richard Henderson wrote: On 5/9/22 04:38, yangxiaojuan wrote: You are not considering CSR[0x420][49], which changes the format of this mapping. Thanks very much, I will consider the mapping format by read iocsr[0x420][49] like this: static uint64_t map_format(void) {   

Re: [RFC PATCH 5/9] tests: use tests/venv to run basevm.py-based scripts

On 5/13/22 02:06, John Snow wrote: This patch co-opts the virtual environment being used by avocado tests to also run the basevm.py tests. This is being done in preparation for for the qemu.qmp package being removed from qemu.git. As part of the change, remove any sys.path() hacks and treat "qem

Re: [RFC PATCH 8/9] iotests: fix source directory location

On 5/13/22 02:06, John Snow wrote: # called from the source tree -self.source_iotests = os.getcwd() +self.source_iotests = str(Path(__file__, '../').resolve()) '../' could be just '..', otherwise Reviewed-by: Paolo Bonzini Paolo

Re: [RFC PATCH 0/9] tests: run python tests under the build/tests/venv environment

On Thu, May 12, 2022 at 08:06:00PM -0400, John Snow wrote: > RFC: This is a very early, crude attempt at switching over to an > external Python package dependency for QMP. This series does not > actually make the switch in and of itself, but instead just switches to > the paradigm of using a venv i

Re: [RFC PATCH 9/9] iotests: use tests/venv for running tests

On 5/13/22 02:06, John Snow wrote: Essentially, this: (A) adjusts the python binary to be the one found in the venv (which is a symlink to the python binary chosen at configure time) (B) adds a new VIRTUAL_ENV export variable (C) changes PATH to front-load the venv binary directory. If the ve

Re: [RFC PATCH 6/9] tests: add check-venv as a dependency of check and check-block

On 5/13/22 02:06, John Snow wrote: meson, create the python venv for block tests. +.PHONY: check-block +check-block: check-venv + @echo # Without some rule, this doesn't run at all. Why? + + # Consolidated targets .PHONY: check check-clean get-vm-images -check: +check: check-venv

Re: [RFC PATCH 1/9] python: update for mypy 0.950

On 5/13/22 02:06, John Snow wrote: typeshed (included in mypy) recently updated to improve the typing for WriteTransport objects. I was working around this, but now there's a version where I shouldn't work around it. Unfortunately this creates some minor ugliness if I want to support both pre- a

Re: [PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC)

On 2022/5/12 上午9:58, maobibo wrote: 在 2022/5/11 22:14, Richard Henderson 写道: On 5/11/22 02:54, yangxiaojuan wrote: On 2022/5/10 上午1:56, Richard Henderson wrote: +    case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1: +    index = (offset - EXTIOI_IPMAP_START) >> 2; +    s->ipmap[inde

Re: [RFC PATCH 7/9] tests: add check-venv to build-tcg-disabled CI recipe

On 5/13/22 02:06, John Snow wrote: Signed-off-by: John Snow --- .gitlab-ci.d/buildtest.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml index 0aea7ab84c2..5c6201847f1 100644 --- a/.gitlab-ci.d/buildtest.yml +++ b/.gitlab-ci.d/buil

[RFC PATCH v4 1/4] target/riscv: Add smstateen support

Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 +

[RFC PATCH v4 0/4] RISC-V Smstateen support

This series adds support for the Smstateen specification which provides a mechanism plug potential covert channels which are opened by extensions that add to processor state that may not get context-switched. Currently access to AIA registers, *envcfg registers and floating point(fcsr) is controlle

[RFC PATCH v4 3/4] target/riscv: smstateen check for fcsr

If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 24 1 file changed, 24 insertions(+) diff --git a/target/riscv/csr.c b/target/r

[RFC PATCH v4 2/4] target/riscv: smstateen check for h/senvcfg

Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 84 ++ 1 file changed, 78 in

[RFC PATCH v4 4/4] target/riscv: smstateen check for AIA/IMSIC

If smstateen is implemented then accesses to AIA registers CSRS, IMSIC CSRs and other IMSIC registers is controlled by setting of corresponding bits in mstateen/hstateen registers. Otherwise an illegal instruction trap or virtual instruction trap is generated. Signed-off-by: Mayuresh Chitale ---

Re: [RFC PATCH 0/9] tests: run python tests under the build/tests/venv environment

On 5/13/22 10:35, Daniel P. Berrangé wrote: The tests is an area where we still have too much taking place in Makefiles, as opposed to meson. Can we put a rule in tests/meson.build to trigger the ven creation ? Gets us closer to being able to run ninja without using make as a wrapper. I don't t

[PATCH 2/5] target/riscv: Disable "G" by default

Because "G" virtual extension expands to "IMAFD", we cannot separately disable extensions like "F" or "D" without disabling "G". Because all "IMAFD" are enabled by default, it's harmless to disable "G" by default. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insert

[PATCH 4/5] target/riscv: FP extension requirements

QEMU allowed inconsistent configurations that made floating point arithmetic effectively unusable. This commit adds certain checks for consistent FP arithmetic: - F requires Zicsr - Zfinx requires Zicsr - Zfh/Zfhmin require F - D requires F - V requires D Because F/D/Zicsr are enabled

[PATCH 5/5] target/riscv: Move/refactor ISA extension checks

We should separate "check" and "configure" steps as possible. This commit separates both steps except vector/Zfinx-related checks. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/

[PATCH 0/5] target/riscv: Enhanced ISA extension checks

Hello, This is another patchset for RISC-V ISA extension / feature handling. Aside from coding style fix / refactoring patch (PATCH 1 and 5), this patchset contains two changes: 1. "G" extension handling 1.A. "G" extension expansion (PATCH 3) On ISA version 20190608 or later, "G" expands to

[PATCH 3/5] target/riscv: Change "G" expansion

On ISA version 20190608 or later, "G" expands to "IMAFD_Zicsr_Zifencei". Both "Zicsr" and "Zifencei" are enabled by default and "G" is supposed to be (virtually) enabled as well, it should be safe to change its expansion. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 7 +-- 1 file chang

Re: [PATCH] hw/adc/zynq-xadc: Use qemu_irq typedef

On Mon, 9 May 2022 at 21:20, Philippe Mathieu-Daudé wrote: > > From: Philippe Mathieu-Daudé > > Except hw/core/irq.c which implements the forward-declared opaque > qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not > using the typedef. Fix this single exception. > > Signed-off-by:

[PATCH 1/5] target/riscv: Fix "G" extension expansion typing

Because ext_? members are in bool type, operator `&&' should be used instead of `&'. Signed-off-by: Tsukasa OI --- target/riscv/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ccacdee215..00bf26ec8b 100644 --- a/target/r

[RFC PATCH 0/1] target/riscv: Make property names lowercase and add capitalized aliases

Hello, While I'm reviewing Dao Lu's Zihintpause patch, I noticed something. c.f. While some CPU configuration properties have capitalized names but others have lowercase names. See riscv_cpu_properties in target/riscv/cpu.c f

[RFC PATCH 1/1] target/riscv: Make property names lowercase

Many properties for extension names are just in lowercase. On the other hand, following extension properties and "Counters" are capitalized. - Zifencei - Zicsr - Zfh - Zfhmin - Zve32f - Zve64f This commit chooses lowercase as primary property names but keeps capitalized names as alia

[PATCH 1/2] target/riscv: Make CPU config error handling generous (virt/spike)

If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more gene

[PATCH 0/2] hw/riscv: Make CPU config error handling generous

Hello, This patchset involves error handling on RISC-V CPU configuration error. For instance: -cpu rv64,f=on,zfinx=on This is an example of invalid CPU configuration because "F" and "Zfinx" cannot coexist. Detecting such error is a good thing. The bad thing is, it aborts when such invalid

[PATCH 2/2] target/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)

If specified CPU configuration is not valid, not just it prints error message, it aborts and generates core dumps (depends on the operating system). This kind of error handling should be used only when a serious runtime error occurs. This commit makes error handling on CPU configuration more gene

Re: [RFC PATCH v4 1/4] target/riscv: Add smstateen support

On 2022/05/13 17:51, Mayuresh Chitale wrote: > Smstateen extension specifies a mechanism to close > the potential covert channels that could cause security issues. > > This patch adds the CSRs defined in the specification and > the corresponding predicates and read/write functions. > > Signed-off

Re: [PATCH] Fix aarch64 debug register names.

On Thu, 12 May 2022 at 10:42, Chris Howard wrote: > > From 5de17d5aacb9cf21de4c9736b227b0498c607709 Mon Sep 17 00:00:00 2001 > From: CHRIS HOWARD > Date: Thu, 12 May 2022 11:35:17 +0200 > Subject: [PATCH] Fix aarch64 debug register names. > > Signed-off-by: CHRIS HOWARD Thanks for sending the p

Re: [PATCH v2 07/15] qga: use qemu_open_cloexec() for safe_open_or_create()

Hi On Thu, May 5, 2022 at 1:33 PM Markus Armbruster wrote: > > marcandre.lur...@redhat.com writes: > > > From: Marc-André Lureau > > > > The function takes care of setting CLOEXEC, and reporting error. > > > > Signed-off-by: Marc-André Lureau > > --- > > qga/commands-posix.c | 11 +++ >

Emulating CPUs with larger atomic accesses

What's QEMU's approach to emulating CPU instructions that atomatically operate on values larger than what is supported by the host CPU? I assume that for full system emulation, this is not a problem, but qemu-user will not achieve atomic behavior on shared memory mappings. How much of a problem is

Re: [PATCH 1/2] target/arm: Enable FEAT_HCX for -cpu max

On Tue, 10 May 2022 at 01:05, Richard Henderson wrote: > > This feature adds a new register, HCRX_EL2, which controls > many of the newer AArch64 features. So far the register is > effectively RES0, because none of the new features are done. > > Signed-off-by: Richard Henderson > --- > target/a

Re: [PATCH v5 0/8] Support exporting BDSs via VDUSE

On Wed, May 04, 2022 at 03:40:43PM +0800, Xie Yongji wrote: > Hi all, > > Last few months ago, VDUSE (vDPA Device in Userspace) [1] has > been merged into Linux kernel as a framework that make it > possible to emulate a vDPA device in userspace. This series > aimed at implementing a VDUSE block ba

Re: [PATCH 2/2] target/arm: Use FIELD definitions for CPACR, CPTR_ELx

On Tue, 10 May 2022 at 01:06, Richard Henderson wrote: > > We had a few CPTR_* bits defined, but missed quite a few. > Complete all of the fields up to ARMv9.2. > Use FIELD_EX64 instead of manual extract32. > > Signed-off-by: Richard Henderson > --- > target/arm/cpu.h| 44 +++

Re: [PATCH v1 00/13] various virtio docs, fixes and tweaks

On Mon, Mar 21, 2022 at 03:30:24PM +, Alex Bennée wrote: > contrib/vhost-user-blk: fix 32 bit build and enable I applied up to this point. Pls respond to Philippe's comment. -- MST

Re: [PATCH v10 00/45] CXl 2.0 emulation Support

On Fri, Apr 29, 2022 at 03:40:25PM +0100, Jonathan Cameron wrote: > Note that due to a bug in the kernel handling of Mem_Enable > in the CXL Device DVSEC a fix is needed to sucessfully use these > patches with Linux. > https://lore.kernel.org/linux-cxl/capcyv4gfww9s6r9kuol-_p9qnazsjbmz+ecmfy+0g1nhr

Re: [PATCH v5 0/9] Introduce akcipher service for virtio-crypto

On Thu, Apr 28, 2022 at 09:59:34PM +0800, zhenwei pi wrote: > Hi, Lei & MST > > Daniel has started to review the akcipher framework and nettle & gcrypt > implementation, this part seems to be ready soon. Thanks a lot to Daniel! > > And the last patch "crypto: Introduce RSA algorithm" handles akci

Re: [RFC PATCH 0/9] tests: run python tests under the build/tests/venv environment

On 5/13/22 02:06, John Snow wrote: The only downside I am really frowning at is that I will have to replicate some "update the venv if it's outdated" logic that is usually handled by the Make system in the venv bootstrapper. Still, I think it's probably the only way to hit all of the requirements

Re: [PATCH v5 0/9] Introduce akcipher service for virtio-crypto

On Fri, May 13, 2022 at 06:19:10AM -0400, Michael S. Tsirkin wrote: > On Thu, Apr 28, 2022 at 09:59:34PM +0800, zhenwei pi wrote: > > Hi, Lei & MST > > > > Daniel has started to review the akcipher framework and nettle & gcrypt > > implementation, this part seems to be ready soon. Thanks a lot to

Re: [RFC PATCH 0/9] tests: run python tests under the build/tests/venv environment

On Fri, May 13, 2022 at 09:35:23AM +0100, Daniel P. Berrangé wrote: > On Thu, May 12, 2022 at 08:06:00PM -0400, John Snow wrote: > > RFC: This is a very early, crude attempt at switching over to an > > external Python package dependency for QMP. This series does not > > actually make the switch in

Re: [PATCH 01/11] hw/rtc/mc146818rtc: Inline isa_connect_gpio_out() and remove it

Am 11. Mai 2022 10:24:58 UTC schrieb Mark Cave-Ayland : >On 05/05/2022 17:17, Bernhard Beschow wrote: > >> Commit 250263033c5343012b2cd6f01210ffb5b908a159 'isa: introduce wrapper >> isa_connect_gpio_out' introduced it in 2016. Since then, its only user >> remained mc146818rtc. Remove this one-off s

Re: [PATCH v5 8/9] tests/crypto: Add test suite for RSA keys

On Thu, Apr 28, 2022 at 09:59:42PM +0800, zhenwei pi wrote: > From: Lei He > > As Daniel suggested, Add tests suite for rsakey, as a way to prove > that we can handle DER errors correctly. > > Signed-off-by: lei he > --- > tests/unit/test-crypto-akcipher.c | 285 +-

Re: [PATCH RESEND 0/2] Resolve some redundant property accessors

Am 5. Mai 2022 16:52:13 UTC schrieb Bernhard Beschow : >Am 1. März 2022 22:52:18 UTC schrieb Bernhard Beschow : >>No changes. Just also CC'ed to qemu-trivial. >> >>The QOM API already provides appropriate accessors, so reuse them. >> >>Testing done: >> >> :$ make check >> Ok: 570

[PATCH v2] qga: add guest-get-diskstats command for Linux guests

Add a new 'guest-get-diskstats' command for report disk io statistics for Linux guests. This can be usefull for getting io flow or handling IO fault, no need to enter guests. Signed-off-by: luzhipeng --- Changes v1->v2: v1:https://patchew.org/QEMU/20220512011930.214-1-luzhip...@cestc.cn/ qga/

Re: [PATCH 2/5] virtio-net: prepare for variable RSS key and indir table lengths

On Fri, Apr 15, 2022 at 01:39:04PM +0800, Jason Wang wrote: > > 在 2022/4/8 20:28, Maxime Coquelin 写道: > > This patch is a preliminary rework to support RSS with > > Vhost-user backends. It enables supporting different types > > of hashes, key lengths and indirection table lengths. > > > > This pa

Re: [PATCH v2] qga: add guest-get-diskstats command for Linux guests

On Fri, May 13, 2022 at 1:40 PM luzhipeng wrote: > Add a new 'guest-get-diskstats' command for report disk io statistics > for Linux guests. This can be usefull for getting io flow or handling > IO fault, no need to enter guests. > > Signed-off-by: luzhipeng > > --- > Changes v1->v2: > v1:https

Re: [PATCH v5 5/9] crypto: Implement RSA algorithm by hogweed

On Thu, Apr 28, 2022 at 09:59:39PM +0800, zhenwei pi wrote: > From: Lei He > > Implement RSA algorithm by hogweed from nettle. Thus QEMU supports > a 'real' RSA backend to handle request from guest side. It's > important to test RSA offload case without OS & hardware requirement. > > Signed-off-

[PATCH] vhost-user: more master/slave things

we switched to front-end/back-end, but newer patches reintroduced old language. Fix this up. Signed-off-by: Michael S. Tsirkin --- docs/interop/vhost-user.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/interop/vhost-user.rst b/docs/interop/vhost-user.rst index 73e71

Re: [PATCH v5 6/9] crypto: Implement RSA algorithm by gcrypt

On Thu, Apr 28, 2022 at 09:59:40PM +0800, zhenwei pi wrote: > From: Lei He > > Added gcryt implementation of RSA algorithm, RSA algorithm > implemented by gcrypt has a higher priority than nettle because > it supports raw padding. > > Signed-off-by: lei he > --- > crypto/akcipher-gcrypt.c.inc

Re: [PATCH] vhost-user-scsi: avoid unlink(NULL) with fd passing

On Thu, May 12, 2022 at 04:57:13PM +0100, Peter Maydell wrote: > On Wed, 27 Apr 2022 at 11:04, Stefan Hajnoczi wrote: > > > > Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend > > Program conventions for vhost-user-scsi") introduced fd-passing support > > as part of implementing

Re: [RFC PATCH v2 2/8] qapi: net: introduce a way to bypass qemu_opts_parse_noisily()

Laurent Vivier writes: > As qemu_opts_parse_noisily() flattens the QAPI structures ("type" field > of Netdev structure can collides with "type" field of SocketAddress), To remember how this works, I have to write a more verbose version of the above. Why not post it then, so here goes. qemu_ini

Re: [PATCH] pc: q35: Bump max_cpus to 512

On Mon, May 09, 2022 at 09:12:49AM +0200, Igor Mammedov wrote: > On Wed, 4 May 2022 08:16:39 -0500 > Suravee Suthikulpanit wrote: > > > This is the maximum number of vCPU supported by > > the AMD x2APIC virtualization. > > > > Signed-off-by: Suravee Suthikulpanit > > --- > > hw/i386/pc_q35.c |

Re: [PATCH 1/3] hw/ide/piix: Remove redundant "piix3-ide-xen" device class

On Sun, May 08, 2022 at 12:34:30PM +0200, Bernhard Beschow wrote: > Commit 0f8445820f11a69154309863960328dda3dc1ad4 'xen: piix reuse pci > generic class init function' already resolved redundant code which in > turn rendered piix3-ide-xen redundant. > > Signed-off-by: Bernhard Beschow Cc xen mai

Re: [PATCH 00/11] Random cleanup patches

On Thu, May 05, 2022 at 06:17:54PM +0200, Bernhard Beschow wrote: > This patch series contains random cleanups that I made while studying the > code. > > Bernhard Beschow (11): > hw/rtc/mc146818rtc: Inline isa_connect_gpio_out() and remove it > hw: Reuse TYPE_I8042 define > hw/audio/cs4231a

Re: [RFC PATCH v2 3/8] qapi: net: add stream and dgram netdevs

Laurent Vivier writes: > Copied from socket netdev file and modified to use SocketAddress > to be able to introduce new features like unix socket. > > "udp" and "mcast" are squashed into dgram netdev, multicast is detected > according to the IP address type. > "listen" and "connect" modes are man

[PATCH qemu v18 02/16] target/riscv: rvv: Prune redundant access_type parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen --- target/riscv/vector_helper.c | 35 --- 1 file changed, 16 insertions(+), 19 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 85dd611

[PATCH qemu v18 08/16] target/riscv: rvv: Add tail agnostic for vector integer shift instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 3 ++- target/riscv/vector_helper.c| 11 +++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/target

[PATCH qemu v18 04/16] target/riscv: rvv: Early exit when vstart >= vl

From: eopXD According to v-spec (section 5.4): When vstart ≥ vl, there are no body elements, and no elements are updated in any destination vector register group, including that no tail elements are updated with agnostic values. vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv

[PATCH qemu v18 03/16] target/riscv: rvv: Rename ambiguous esz

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 76 ++-- 1 file changed, 38 insertions(+), 38 deletions(-) diff

[PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions

According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". An option 'rvv_ta_all_1s' is added to ena

[PATCH qemu v18 10/16] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 12 target/riscv/vector_helper.c| 20 2 files changed, 28 insertions(+), 4 deletions(-)

[PATCH qemu v18 01/16] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed

From: eopXD No functional change intended in this commit. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 1132 +- 1 file changed, 565 insertions(+), 567 deletions(-) di

[PATCH qemu v18 05/16] target/riscv: rvv: Add tail agnostic for vv instructions

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PATCH qemu v18 06/16] target/riscv: rvv: Add tail agnostic for vector load / store instructions

From: eopXD Destination register of unit-stride mask load and store instructions are always written with a tail-agnostic policy. A vector segment load / store instruction may contain fractional lmul with nf * lmul > 1. The rest of the elements in the last register should be treated as tail eleme

[PATCH qemu v18 12/16] target/riscv: rvv: Add tail agnostic for vector floating-point instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 17 + target/riscv/vector_helper.c| 4

[PATCH qemu v18 07/16] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions

From: eopXD `vmadc` and `vmsbc` produces a mask value, they always operate with a tail agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 13 +- target/riscv/internals.h

[PATCH qemu v4 01/10] target/riscv: rvv: Add mask agnostic for vv instructions

From: Yueh-Ting (eop) Chen According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are m

[PATCH qemu v18 13/16] target/riscv: rvv: Add tail agnostic for vector reduction instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 20 1 file changed, 20 insertions(+) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 8ac7fabb

[PATCH qemu v18 11/16] target/riscv: rvv: Add tail agnostic for vector fix-point arithmetic instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 220 ++- 1 file changed, 114 insertions(+), 106 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/r

[PATCH qemu v4 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang --- target/riscv/insn_trans/trans_rvv.c.inc | 5 target/riscv/vector_helper.c| 35 + 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/target/riscv/insn_trans/tr

[PATCH qemu v4 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/

[PATCH qemu v4 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 1 + target/riscv/vector_helper.c| 10 ++ 2 files changed, 11 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.i

[PATCH qemu v18 09/16] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions

From: eopXD Compares write mask registers, and so always operate under a tail- agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/vector_helper.c | 18 ++ 1 file changed, 18 insertions(+) diff

[PATCH qemu v18 15/16] target/riscv: rvv: Add tail agnostic for vector permutation instructions

From: eopXD Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 7 +++-- target/riscv/vector_helper.c| 40 + 2 files changed, 45 insertions(+), 2 deletions(-) di

[PATCH qemu v4 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/vector_helper.c | 26 -- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c inde

[PATCH qemu v18 14/16] target/riscv: rvv: Add tail agnostic for vector mask instructions

From: eopXD The tail elements in the destination mask register are updated under a tail-agnostic policy. Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li Acked-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 6 + target/riscv/vector_helper.c

[PATCH qemu v4 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 3 +++ target/riscv/vector_helper.c| 11 +++ 2 files changed, 14 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.

[PATCH qemu v18 16/16] target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable optional tail agnostic behavior

From: eopXD According to v-spec, tail agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of tail policies, QEMU should be able to simulate the tail agnostic behavior as "set tail elements' bits to all 1s". There are multiple possibi

[PATCH qemu v4 03/10] target/riscv: rvv: Add mask agnostic for vx instructions

From: Yueh-Ting (eop) Chen Signed-off-by: eop Chen Reviewed-by: Frank Chang Reviewed-by: Weiwei Li --- target/riscv/insn_trans/trans_rvv.c.inc | 2 ++ target/riscv/vector_helper.c| 3 +++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/tar

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