The vsock callbacks .vhost_vsock_set_guest_cid and
.vhost_vsock_set_running are the only ones to be conditional
on #ifdef CONFIG_VHOST_VSOCK. This is different from any other
device-dependent callbacks like .vhost_scsi_set_endpoint, and it
also broke when CONFIG_VHOST_VSOCK was changed to a per-ta
> +if png.found()
> + softmmu_ss.add(png)
> +endif
Queued, thanks. However, this can be just "softmmu_ss.add(png) without
the if, so I adjusted that.
Paolo
Thank you! Grateful for it.
Regards,
Kshitij Suri
On 11/05/22 1:16 pm, Paolo Bonzini wrote:
+if png.found()
+ softmmu_ss.add(png)
+endif
Queued, thanks. However, this can be just "softmmu_ss.add(png) without
the if, so I adjusted that.
Paolo
* Michal Privoznik (mpriv...@redhat.com) wrote:
> When allocating large amounts of memory the task is offloaded
> onto threads. These threads then use various techniques to
> allocate the memory fully (madvise(), writing into the memory).
> However, these threads are free to run on any CPU, which b
From: Mark Kanda
Introduce QMP support for querying stats. Provide a framework for adding new
stats and support for the following commands:
- query-stats
Returns a list of all stats per target type (only VM and vCPU to start), with
additional options for specifying stat names, vCPU qom paths, an
From: Mark Kanda
Add support for querying fd-based KVM stats - as introduced by Linux kernel
commit:
cb082bfab59a ("KVM: stats: Add fd-based API to read binary stats data")
This allows the user to analyze the behavior of the VM without access
to debugfs.
Signed-off-by: Mark Kanda
Signed-off-b
From: Mark Kanda
Add an HMP command to retrieve statistics collected at run-time.
The command will retrieve and print either all VM-level statistics,
or all vCPU-level statistics for the currently selected CPU.
Signed-off-by: Paolo Bonzini
---
hmp-commands-info.hx | 13 +++
include/monitor/h
This patchset adds QEMU support for querying fd-based KVM statistics.
This allows the user to analyze the behavior of the VM without access
to debugfs.
However, instead of adding an ad hoc command, the new QMP entry point
can be extended in the future to more statistics provider than KVM
(for exam
Introduce a simple filtering of statistics, that allows to retrieve
statistics for a subset of the guest vCPUs. This will be used for
example by the HMP monitor, in order to retrieve the statistics
for the currently selected CPU.
Example:
{ "execute": "query-stats",
"arguments": {
"target":
Allow the user to request statistics for a single provider of interest.
Extracted from a patch by Mark Kanda.
Signed-off-by: Paolo Bonzini
---
monitor/hmp-cmds.c | 39 +--
1 file changed, 33 insertions(+), 6 deletions(-)
diff --git a/monitor/hmp-cmds.c b/moni
Allow retrieving only a subset of statistics. This can be useful
for example in order to plot a subset of the statistics many times
a second.
KVM publishes ~40 statistics for each vCPU on x86; retrieving and
serializing all of them would be useless
Another use will be in HMP in the following pat
Allow retrieving the statistics from a specific provider only.
This can be used in the future by HMP commands such as "info
sync-profile" or "info profile". The next patch also adds
filter-by-provider capabilities to the HMP equivalent of
query-stats, "info stats".
Example:
{ "execute": "query-s
Allow the user to request only a specific subset of statistics.
This can be useful when working on a feature or optimization that is
known to affect that statistic.
Extracted from a patch by Mark Kanda.
Signed-off-by: Paolo Bonzini
---
hmp-commands-info.hx | 7 ---
monitor/hmp-cmds.c | 3
* Leonardo Bras Soares Passos (leob...@redhat.com) wrote:
> From a previous thread:
>
> On Thu, Apr 28, 2022 at 1:20 PM Dr. David Alan Gilbert
> wrote:
> >
> > Leo:
> > Unfortunately this is failing a couple of CI tests; the MSG_ZEROCOPY
> > one I guess is the simpler one; I think Stefanha mana
On Tue, May 10, 2022 at 8:24 PM Andrew Melnichenko wrote:
>
> Hi all,
> The ebpf/rss.bpf.skeleton.h is generetad by bpftool from tools/ebpf/rss.bpf.c.
> To generate the skeleton - would require dependencies of llvm and bpftool.
> RSS eBPF solution, for now, is only for Linux hosts.
>
> > Andrew, w
On Wed, May 11, 2022 at 2:10 PM Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
>
>
>
> 在 2022/5/11 10:56, Jason Wang 写道:
> > On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
> >>
> >> From: Longpeng
> >>
> >> Supports vdpa-dev.
> >>
> >> Signed-off-by: Longpeng
> >> ---
On Wed, May 11, 2022 at 04:56:23PM +0800, Jason Wang wrote:
On Wed, May 11, 2022 at 2:32 PM Stefano Garzarella wrote:
On Wed, May 11, 2022 at 10:56:02AM +0800, Jason Wang wrote:
>On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
>>
>> From: Longpeng
>>
>> Supports vdpa-dev.
>>
>> Signed-
On Wed, May 11, 2022 at 2:32 PM Stefano Garzarella wrote:
>
> On Wed, May 11, 2022 at 10:56:02AM +0800, Jason Wang wrote:
> >On Tue, May 10, 2022 at 8:59 PM Longpeng(Mike) wrote:
> >>
> >> From: Longpeng
> >>
> >> Supports vdpa-dev.
> >>
> >> Signed-off-by: Longpeng
> >> ---
> >> hw/virtio/Kco
On Tue, May 10, 2022 at 08:55:33AM +0200, Michal Privoznik wrote:
> When allocating large amounts of memory the task is offloaded
> onto threads. These threads then use various techniques to
> allocate the memory fully (madvise(), writing into the memory).
> However, these threads are free to run o
On Wed, May 11, 2022 at 09:34:07AM +0100, Dr. David Alan Gilbert wrote:
> * Michal Privoznik (mpriv...@redhat.com) wrote:
> > When allocating large amounts of memory the task is offloaded
> > onto threads. These threads then use various techniques to
> > allocate the memory fully (madvise(), writin
On Tue, May 10, 2022 at 09:56:12PM +0200, Thomas Huth wrote:
> According to our "Supported build platforms" policy, we now do not support
> Ubuntu 18.04 anymore. Remove the related files and entries from our CI.
>
> Signed-off-by: Thomas Huth
> ---
> Seems like nobody touched the 18.04-based tes
On 11.05.22 01:17, Juan Quintela wrote:
> We are recalculating ram size continously, when we know that it don't
> change during migration. Create a field in RAMState to track it.
We do have resizable RAM, which triggers ram_mig_ram_block_resized() on
resizes when changing block->used_length.
ram
Hi Jason,
Do you mind taking this single patch via your networking tree?
Otherwise I Cc'ed qemu-trivial :)
Thanks!
On Thu, Mar 10, 2022 at 5:56 PM Helge Deller wrote:
>
> The MAC of the tulip card is stored in the EEPROM and at startup
> tulip_fill_eeprom() is called to initialize the EEPROM wi
>> Long story short, management application has no way of learning
>> TIDs of allocator threads so it can't make them run NUMA aware.
>
> This feels like the key issue. The preallocation threads are
> invisible to libvirt, regardless of whether we're doing coldplug
> or hotplug of memory-backends.
On Wed, May 11, 2022 at 11:31:23AM +0200, David Hildenbrand wrote:
> >> Long story short, management application has no way of learning
> >> TIDs of allocator threads so it can't make them run NUMA aware.
> >
> > This feels like the key issue. The preallocation threads are
> > invisible to libvirt
We haven't revisited the minimum required versions of pixman
since quite a while. Let's check whether we can rule out some
old versions that nobody tests anymore...
For pixman, per repology.org, currently shipping versions are:
CentOS 8 / RHEL-8 : 0.38.4
Fedora 34: 0.40.0
On 2022/5/10 上午1:56, Richard Henderson wrote:
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ s->ipmap[index] = val;
+ break;
Do you need to recompute the entire interrupt map when ipmap changes?
Sorry, could you ex
On 11.05.22 11:34, Daniel P. Berrangé wrote:
> On Wed, May 11, 2022 at 11:31:23AM +0200, David Hildenbrand wrote:
Long story short, management application has no way of learning
TIDs of allocator threads so it can't make them run NUMA aware.
>>>
>>> This feels like the key issue. The prea
On Wed, May 11, 2022 at 12:03:24PM +0200, David Hildenbrand wrote:
> On 11.05.22 11:34, Daniel P. Berrangé wrote:
> > On Wed, May 11, 2022 at 11:31:23AM +0200, David Hildenbrand wrote:
> Long story short, management application has no way of learning
> TIDs of allocator threads so it can'
Hello,
cc'ing Paul and Nick for clarification on the behaviour of xsrsp (see below)
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
> The FI bit in FPSCR is said to be a non-sticky bit on Power ISA.
> One could think this means that, if an instruction is said to modify
> the FPSCR regis
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
> This patch fixes another not-so-clear situation in Power ISA
> regarding the inexact bits in FPSCR. The ISA states that:
>
> """
> When Overflow Exception is disabled (OE=0) and an
> Overflow Exception occurs, the following actions are
> t
On Tue, 2022-05-10 at 17:46 -0300, Víctor Colombo wrote:
> The bit FI fix used the sfprf flag as a flag for the set_fi parameter
> in do_float_check_status where applicable. Now, this patch rename
> this
> flag to sfifprf to state this dual usage.
>
> Signed-off-by: Víctor Colombo
>
> ---
>
> v
On Wed, May 11, 2022 at 5:41 PM Philippe Mathieu-Daudé wrote:
>
> Hi Jason,
>
> Do you mind taking this single patch via your networking tree?
> Otherwise I Cc'ed qemu-trivial :)
I've queued this.
Thanks
>
> Thanks!
>
> On Thu, Mar 10, 2022 at 5:56 PM Helge Deller wrote:
> >
> > The MAC of the
On 05/05/2022 17:17, Bernhard Beschow wrote:
Commit 250263033c5343012b2cd6f01210ffb5b908a159 'isa: introduce wrapper
isa_connect_gpio_out' introduced it in 2016. Since then, its only user
remained mc146818rtc. Remove this one-off solution.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c
On Wed, 11 May 2022 at 10:50, Thomas Huth wrote:
>
> We haven't revisited the minimum required versions of pixman
> since quite a while. Let's check whether we can rule out some
> old versions that nobody tests anymore...
>
> For pixman, per repology.org, currently shipping versions are:
>
>
+Robert
On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
wrote:
>
> On Tue, May 10, 2022 at 09:56:12PM +0200, Thomas Huth wrote:
> > According to our "Supported build platforms" policy, we now do not support
> > Ubuntu 18.04 anymore. Remove the related files and entries from our CI.
> >
> > S
On 11/05/2022 12.28, Peter Maydell wrote:
On Wed, 11 May 2022 at 10:50, Thomas Huth wrote:
We haven't revisited the minimum required versions of pixman
since quite a while. Let's check whether we can rule out some
old versions that nobody tests anymore...
For pixman, per repology.org, current
On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
+Robert
On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
wrote:
On Tue, May 10, 2022 at 09:56:12PM +0200, Thomas Huth wrote:
According to our "Supported build platforms" policy, we now do not support
Ubuntu 18.04 anymore. Remove the rel
On 5/11/22 12:10, Daniel P. Berrangé wrote:
If all we needs is NUMA affinity, not CPU affinity, then it would
be sufficient to create 1 I/O thread per host NUMA node that the
VM needs to use. The job running in the I/O can spawn further
threads and inherit the NUMA affinity. This might be more c
+Fam
On Wed, May 11, 2022 at 1:03 PM Thomas Huth wrote:
> On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
> > +Robert
> >
> > On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
> > wrote:
> >>
> >> On Tue, May 10, 2022 at 09:56:12PM +0200, Thomas Huth wrote:
> >>> According to our "Supporte
On 11/05/2022 13.13, Philippe Mathieu-Daudé wrote:
+Fam
On Wed, May 11, 2022 at 1:03 PM Thomas Huth wrote:
On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
+Robert
On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
wrote:
On Tue, May 10, 2022 at 09:56:12PM +0200, Thomas Huth wrote:
On Dienstag, 10. Mai 2022 17:35:10 CEST Shi, Guohuai wrote:
> Let's force on the security issue:
>
> Firstly, this answer (
> https://stackoverflow.com/questions/32138524/is-there-a-windows-equivalent->
> of-openat ) is useless for QEMU. It uses Windows native API NtCreateFile()
> and accesses fi
On Wed, May 11, 2022 at 12:56:45PM +0200, Thomas Huth wrote:
> On 11/05/2022 12.28, Peter Maydell wrote:
> > On Wed, 11 May 2022 at 10:50, Thomas Huth wrote:
> > >
> > > We haven't revisited the minimum required versions of pixman
> > > since quite a while. Let's check whether we can rule out som
Hello QEMU devs,
Currently to launch an SEV guest there are certain requirements for the VM
configuration. One such is that ROM option needs to be disabled for virtio-net
devices [1]. The tools like virt-install or libvirt rely on the QEMU defaults if
the ROM value is not provided (the default for
On 5/6/22 21:33, Peter Delevoryas wrote:
Add fby35 to the list of Aspeed boards.
Signed-off-by: Peter Delevoryas
---
docs/system/arm/aspeed.rst | 1 +
1 file changed, 1 insertion(+)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 60ed94f187..fa98549c11 100644
---
This was found when running linux crypto algorithm selftests used by
wireguard. We found that randomly the tests would fail. We found
through investigation that a combination of a tick timer interrupt,
raised when executing a delay slot instruction at a page boundary caused
the issue.
This was c
The "-display sdl" option still used a hand-crafted parser for its
parameters since some of them used underscores which is forbidden
in QAPI. Now that they've been deprecated and the deprecation period
is over, we can remove the problematic parameters and switch to use
the QAPI parser instead.
Sig
On Tue, 10 May 2022 15:35:10 +
"Shi, Guohuai" wrote:
> Let's force on the security issue:
>
Please don't top post, especially when all previous comments were
made inline, so that someone who steps in this thread now has a
chance to catch-up.
> Firstly, this answer (
> https://stackoverflo
On Wed, May 11, 2022 at 02:17:25PM +0200, Thomas Huth wrote:
> The "-display sdl" option still used a hand-crafted parser for its
> parameters since some of them used underscores which is forbidden
> in QAPI. Now that they've been deprecated and the deprecation period
> is over, we can remove the p
Jason Wang writes:
> On Tue, May 10, 2022 at 8:24 PM Andrew Melnichenko wrote:
>>
>> Hi all,
>> The ebpf/rss.bpf.skeleton.h is generetad by bpftool from
>> tools/ebpf/rss.bpf.c.
>> To generate the skeleton - would require dependencies of llvm and bpftool.
>> RSS eBPF solution, for now, is only
On 11/05/2022 14.40, Daniel P. Berrangé wrote:
On Wed, May 11, 2022 at 02:17:25PM +0200, Thomas Huth wrote:
The "-display sdl" option still used a hand-crafted parser for its
parameters since some of them used underscores which is forbidden
in QAPI. Now that they've been deprecated and the depre
On 2022-05-11 13:13, Philippe Mathieu-Daudé via wrote:
> +Fam
> On Wed, May 11, 2022 at 1:03 PM Thomas Huth wrote:
> > On 11/05/2022 12.46, Philippe Mathieu-Daudé wrote:
> > > +Robert
> > >
> > > On Wed, May 11, 2022 at 11:30 AM Daniel P. Berrangé
> > > wrote:
> > >>
> > >> On Tue, May 10, 2022
On 5/10/22 11:12, Daniel P. Berrangé wrote:
> On Tue, May 10, 2022 at 08:55:33AM +0200, Michal Privoznik wrote:
>> When allocating large amounts of memory the task is offloaded
>> onto threads. These threads then use various techniques to
>> allocate the memory fully (madvise(), writing into the me
Daniel P. Berrangé writes:
> On Mon, May 02, 2022 at 10:01:41AM -0400, Andrea Bolognani wrote:
>> > Times how many naming conventions?
>>
>> Yeah, I don't think requiring all possible permutations to be spelled
>> out in the schema is the way to go. That's exactly why my proposal
>> was to offer
On 5/11/22 02:54, yangxiaojuan wrote:
On 2022/5/10 上午1:56, Richard Henderson wrote:
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ s->ipmap[index] = val;
+ break;
Do you need to recompute the entire interrupt map w
Daniel P. Berrangé writes:
> On Tue, May 10, 2022 at 02:02:56PM +0200, Markus Armbruster wrote:
>> Daniel P. Berrangé writes:
>>
>> > On Tue, Apr 26, 2022 at 01:14:28PM +0200, Markus Armbruster wrote:
>> >> We need to look at "following the QEMU releases" a bit more closely.
>> >>
>> >> Mergin
Daniel P. Berrangé writes:
> On Tue, May 10, 2022 at 01:34:03PM +0100, Daniel P. Berrangé wrote:
>> On Tue, May 10, 2022 at 02:02:56PM +0200, Markus Armbruster wrote:
>> > > For a minimum viable use case, this doesn't feel all that difficult, as
>> > > conceptually instead of deleting the field f
On 5/11/22 05:05, Stafford Horne wrote:
+static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+cpu->env.pc = tb->pc;
+}
If mips is a guide, you'd want to set dflag
On 10/05/2022 23:24, Stefano Brivio wrote:
...
I don't know if this is an issue, but I couldn't figure out the reason
for this difference either:
- with the old socket option, I can pass something like:
-net socket,fd=5 -net nic,model=virtio
and frames are sent to/received from socket
On Wed, May 11, 2022 at 04:17:43PM +0200, Markus Armbruster wrote:
> Daniel P. Berrangé writes:
>
> > On Tue, May 10, 2022 at 01:34:03PM +0100, Daniel P. Berrangé wrote:
> > Having said that, a different way to approach the problem is to expose
> > the versioning directly in the generated code.
>
When hypervisor and VS CSRs are accessed from VS-mode or VU-mode,
the riscv_csrrw_check() function should generate virtual instruction
trap instead illegal instruction trap.
Fixes: 0a42f4c44088 (" target/riscv: Fix CSR perm checking for HS mode")
Signed-off-by: Anup Patel
Reviewed-by: Alistair Fr
This series does fixes and improvements to have nested virtualization
on QEMU RISC-V.
These patches can also be found in riscv_nested_fixes_v2 branch at:
https://github.com/avpatel/qemu.git
The RISC-V nested virtualization was tested on QEMU RISC-V using
Xvisor RISC-V which has required hyperviso
We should write transformed instruction encoding of the trapped
instruction in [m|h]tinst CSR at time of taking trap as defined
by the RISC-V privileged specification v1.12.
Signed-off-by: Anup Patel
---
target/riscv/cpu_helper.c | 168 +-
target/riscv/instmap
Currently, QEMU does not set hstatus.GVA bit for traps taken from
HS-mode into HS-mode which breaks the Xvisor nested MMU test suite
on QEMU. This was working previously.
This patch updates riscv_cpu_do_interrupt() to fix the above issue.
Fixes: 86d0c457396b ("target/riscv: Fixup setting GVA")
Si
Currently, the [m|s]tval CSRs are set with trapping instruction encoding
only for illegal instruction traps taken at the time of instruction
decoding.
In RISC-V world, a valid instructions might also trap as illegal or
virtual instruction based to trapping bits in various CSRs (such as
mstatus.TVM
The riscv_cpu_realize() sets priv spec verion to v1.12 when it is
when "env->priv_ver == 0" (i.e. default v1.10) because the enum
value of priv spec v1.10 is zero.
Due to above issue, the sifive_u machine will see priv spec v1.12
instead of priv spec v1.10.
To fix this issue, we set latest priv s
We should disable extensions in riscv_cpu_realize() if minimum required
priv spec version is not satisfied. This also ensures that machines with
priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter
extensions.
Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the
When both APLIC and IMSIC are present in virt machine, the APLIC should
be used as parent interrupt controller for dynamic platform devices.
In case of multiple sockets, we should prefer interrupt controller of
socket0 for dynamic platform devices.
Fixes: 3029fab64309 ("hw/riscv: virt: Add suppo
The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For
implementation that don't want to implement can simply have a dummy
mcountinhibit which always zero.
Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in
the CSR ops.")
Signed-off-by: Anup Patel
Reviewed-by:
>>
>> The very last cases is the only one where this patch can potentially
>> be beneficial. The problem is that because libvirt is in charge of
>> enforcing CPU affinity, IIRC, we explicitly block QEMU from doing
>> anything with CPU affinity. So AFAICT, this patch should result in
>> an error fro
On 2022/5/10 下午10:08, Yi Liu wrote:
On 2022/5/10 20:45, Jason Gunthorpe wrote:
On Tue, May 10, 2022 at 08:35:00PM +0800, Zhangfei Gao wrote:
Thanks Yi and Eric,
Then will wait for the updated iommufd kernel for the PCI MMIO region.
Another question,
How to get the iommu_domain in the ioctl.
Cleaned up with scripts/clean-header-guards.pl.
Signed-off-by: Markus Armbruster
Message-Id: <20220506134911.2856099-5-arm...@redhat.com>
Reviewed-by: Richard Henderson
---
bsd-user/arm/target.h | 2 +-
bsd-user/x86_64/target.h | 2 +-
chardev/chardev-inte
Leading underscores are ill-advised because such identifiers are
reserved. Trailing underscores are merely ugly. Strip both.
Our header guards commonly end in _H. Normalize the exceptions.
Macros should be ALL_CAPS. Normalize the exception.
Done with scripts/clean-header-guards.pl.
include/
The following changes since commit 178bacb66d98d9ee7a702b9f2a4dfcd88b72a9ab:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2022-05-09 11:07:04 -0700)
are available in the Git repository at:
git://repo.or.cz/qemu/armbru.git tags/pull-misc-2022-05-11
for yo
We commonly define the header guard symbol without an explicit value.
Normalize the exceptions.
Done with scripts/clean-header-guards.pl.
Signed-off-by: Markus Armbruster
Message-Id: <20220506134911.2856099-4-arm...@redhat.com>
Reviewed-by: Richard Henderson
---
include/exec/memopidx.h |
Header guard symbols should match their file name to make guard
collisions less likely.
Cleaned up with scripts/clean-header-guards.pl, followed by some
renaming of new guard symbols picked by the script to better ones.
Signed-off-by: Markus Armbruster
Message-Id: <20220506134911.2856099-2-arm..
On Wed, May 11, 2022 at 03:16:55PM +0200, Michal Prívozník wrote:
> On 5/10/22 11:12, Daniel P. Berrangé wrote:
> > On Tue, May 10, 2022 at 08:55:33AM +0200, Michal Privoznik wrote:
> >> When allocating large amounts of memory the task is offloaded
> >> onto threads. These threads then use various
On Tue, May 10, 2022 at 01:51:05PM +0100, Daniel P. Berrangé wrote:
> In 7.0.0 we can now generate
>
>type BlockResizeArguments struct {
>V500 *BlockResizeArgumentsV500
>V520 *BlockResizeArgumentsV520
>V700 *BlockResizeArgumentsV700
>}
>
>type BlockResizeArgument
On Wed, May 11, 2022 at 08:38:04AM -0700, Andrea Bolognani wrote:
> On Tue, May 10, 2022 at 01:51:05PM +0100, Daniel P. Berrangé wrote:
> > In 7.0.0 we can now generate
> >
> >type BlockResizeArguments struct {
> >V500 *BlockResizeArgumentsV500
> >V520 *BlockResizeArgumentsV520
On 10/05/2022 23:24, Stefano Brivio wrote:
On Mon, 9 May 2022 19:36:13 +0200
Laurent Vivier wrote:
Signed-off-by: Laurent Vivier
---
include/qemu/sockets.h | 2 ++
net/net.c | 62 ++
2 files changed, 34 insertions(+), 30 deletions(-)
On 31/03/22 8:38 pm, Peter Xu wrote:
LGTM
This patch enables postcopy-preempt feature.
It contains two major changes to the migration logic:
(1) Postcopy requests are now sent via a different socket from precopy
background migration stream, so as to be isolated from very high page
r
> -Original Message-
> From: Greg Kurz
> Sent: 2022年5月11日 20:19
> To: Shi, Guohuai
> Cc: Christian Schoenebeck ; qemu-devel@nongnu.org;
> Meng,
> Bin ; Bin Meng
> Subject: Re: [PATCH 5/9] hw/9pfs: Add a 'local' file system backend driver for
> Windows
>
> [Please note: This e-mail is
On Wed, May 11, 2022 at 04:50:35PM +0100, Daniel P. Berrangé wrote:
> This would lead to a situation where every struct is duplicated
> for every version, even though 90% of the time they'll be identical
> across multiple versions. This is not very ammenable to the desire
> to be able to dynamicall
On Wed, May 11, 2022 at 09:22:36AM -0700, Andrea Bolognani wrote:
> On Wed, May 11, 2022 at 04:50:35PM +0100, Daniel P. Berrangé wrote:
> > This would lead to a situation where every struct is duplicated
> > for every version, even though 90% of the time they'll be identical
> > across multiple ver
On 11.05.22 17:08, Daniel P. Berrangé wrote:
> On Wed, May 11, 2022 at 03:16:55PM +0200, Michal Prívozník wrote:
>> On 5/10/22 11:12, Daniel P. Berrangé wrote:
>>> On Tue, May 10, 2022 at 08:55:33AM +0200, Michal Privoznik wrote:
When allocating large amounts of memory the task is offloaded
>>
Signed-off-by: Paolo Bonzini
---
scripts/kvm/vmxcap | 17 +
1 file changed, 17 insertions(+)
diff --git a/scripts/kvm/vmxcap b/scripts/kvm/vmxcap
index f140040104..ce27f5e635 100755
--- a/scripts/kvm/vmxcap
+++ b/scripts/kvm/vmxcap
@@ -23,6 +23,7 @@ MSR_IA32_VMX_TRUE_PROCBASED_CT
On Wed, May 11, 2022 at 01:07:47PM +0200, Paolo Bonzini wrote:
> On 5/11/22 12:10, Daniel P. Berrangé wrote:
> > If all we needs is NUMA affinity, not CPU affinity, then it would
> > be sufficient to create 1 I/O thread per host NUMA node that the
> > VM needs to use. The job running in the I/O can
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s". An option
'rvv_ta_all_1s' is added to ena
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 220 ++-
1 file changed, 114 insertions(+), 106 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/r
From: eopXD
According to v-spec (section 5.4):
When vstart ≥ vl, there are no body elements, and no elements are
updated in any destination vector register group, including that
no tail elements are updated with agnostic values.
vmsbf.m, vmsif.m, vmsof.m, viota.m, vcompress instructions themselv
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 76 ++--
1 file changed, 38 insertions(+), 38 deletions(-)
diff
From: eopXD
Destination register of unit-stride mask load and store instructions are
always written with a tail-agnostic policy.
A vector segment load / store instruction may contain fractional lmul
with nf * lmul > 1. The rest of the elements in the last register should
be treated as tail eleme
From: eopXD
According to v-spec, tail agnostic behavior can be either kept as
undisturbed or set elements' bits to all 1s. To distinguish the
difference of tail policies, QEMU should be able to simulate the tail
agnostic behavior as "set tail elements' bits to all 1s".
There are multiple possibi
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
target/riscv/vector_helper.c| 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/target
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
target/riscv/vector_helper.c| 20
2 files changed, 28 insertions(+), 4 deletions(-)
LGTM
On 26/04/22 5:08 am, Peter Xu wrote:
Create a new socket for postcopy to be prepared to send postcopy requested
pages via this specific channel, so as to not get blocked by precopy pages.
A new thread is also created on dest qemu to receive data from this new channel
based on the ram_load_
From: eopXD
`vmadc` and `vmsbc` produces a mask value, they always operate with
a tail agnostic policy.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvv.c.inc | 13 +-
target/riscv/internals.h
From: eopXD
No functional change intended in this commit.
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Reviewed-by: Alistair Francis
---
target/riscv/vector_helper.c | 1132 +-
1 file changed, 565 insertions(+), 567 deletions(-)
di
From: eopXD
Signed-off-by: eop Chen
Reviewed-by: Frank Chang
Reviewed-by: Weiwei Li
Acked-by: Alistair Francis
---
target/riscv/vector_helper.c | 20
1 file changed, 20 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5acbe68b
1 - 100 of 210 matches
Mail list logo
