Hi Cédric,
On 18/3/22 14:28, Cédric Le Goater wrote:
The initial eMMC support from Vincent Palatin was largely reworked to
match the current SD framework. The parameters mimick a real 4GB eMMC,
but it can be set to various sizes.
This adds a new QOM object class for EMMC devices.
Signed-off-by
On 5/9/22 10:54, Peter Maydell wrote:
@@ -841,6 +841,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
t = FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level
Historically, The mtimer/mtimecmp has been part of the CPU because
they are per hart entities. However, they actually belong to aclint
which is a MMIO device.
Move them to the ACLINT device. This also emulates the real hardware
more closely.
Signed-off-by: Atish Patra
---
hw/intc/riscv_aclint.c
This series implements Sstc extension[1] which was ratified recently.
The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
on top of upstream commit (faee5441a038).
The series can also be found at
https://github.
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 8
target/riscv/cpu.h | 7 +++
target/riscv/cpu_
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h |
On 9/5/22 23:14, Taylor Simpson wrote:
Remove encodings guarded by ifdef that is not defined
Signed-off-by: Taylor Simpson
---
target/hexagon/imported/encode_pp.def | 23 ---
1 file changed, 23 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Daniel,
I found a way to make the monitor arguments in array type (['uint32']).
And I know how to retrieve monitor values from it but I could not find
how to pass the monitor values when starting qemu. Like,
qemu-system-x86_64 . gtk,gl=on.monitor=
I tried several different things but
On 9/5/22 23:14, Taylor Simpson wrote:
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet comm
On 5/9/22 07:48, Víctor Colombo wrote:
-static inline void float_inexact_excp(CPUPPCState *env)
+static inline void float_inexact_excp(CPUPPCState *env, bool set_fi)
{
CPUState *cs = env_cpu(env);
-env->fpscr |= FP_FI;
+if (set_fi) {
+env->fpscr |= FP_FI;
+}
On 5/9/22 18:17, Mark Cave-Ayland wrote:
On 07/05/2022 20:06, Daniel Henrique Barboza wrote:
Hi,
Since the 7.0.0 release cycle we have a desire to use the powernv
emulation with libvirt. To do that we need to enable user creatable
pnv-phb devices to allow more user customization an to avoid
On Fri, Apr 22, 2022 at 06:56:12PM +0800, Chao Peng wrote:
> Great thanks for the discussions. I summarized the requirements/gaps and the
> potential changes for next step. Please help to review.
Hi Chao,
Thanks for writing this up. I've been meaning to respond, but wanted to
make a bit more prog
Hi, Peter.
> Shuuichirou, Itaru: do either of you know the right setting for the A64FX for
> this? If
> you can find what the hardware value of the ICC_CTLR_EL3 or ICC_CTLR_EL1
> register is (more specifically, the PRIBits subfield) that should be enough
> to tell
> us.
The value of the PRIbits
On 5/9/22 07:48, Víctor Colombo wrote:
This patch fixes another not-so-clear situation in Power ISA
regarding the inexact bits in FPSCR. The ISA states that:
"""
When Overflow Exception is disabled (OE=0) and an
Overflow Exception occurs, the following actions are
taken:
...
2. Inexact Exception
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
fill_thread_info() takes a pointer to const.
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/elfload.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/strace.c | 202 ++--
linux-user/strace.h | 4 +-
linux-user/syscall.c| 32 +++---
linux-user/uname.c
On 5/9/22 15:57, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c| 49 +
linux-user/uname.c | 2 +-
linux-user/user-internals.h | 2 +-
3 files changed, 25 inserti
On Mon, May 09, 2022, Michael Roth wrote:
> On Fri, Apr 22, 2022 at 06:56:12PM +0800, Chao Peng wrote:
> > Requirements & Gaps
> > -
> > - Confidential computing(CC): TDX/SEV/CCA
> > * Need support both explicit/implicit conversions.
> > * Need support
We had a few CPTR_* bits defined, but missed quite a few.
Complete all of the fields up to ARMv9.2.
Use FIELD_EX64 instead of manual extract32.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 44 +++-
hw/arm/boot.c | 2 +-
target/arm/cpu.c| 1
Add HCRX_EL2 with no supported bits, and bit definitions for CPACR*.
Just trying to keep the queue smaller.
r~
Richard Henderson (2):
target/arm: Enable FEAT_HCX for -cpu max
target/arm: Use FIELD definitions for CPACR, CPTR_ELx
target/arm/cpu.h| 64 ---
hw/ar
This feature adds a new register, HCRX_EL2, which controls
many of the newer AArch64 features. So far the register is
effectively RES0, because none of the new features are done.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 20 ++
target/arm/cpu64.c | 1 +
target
> -Original Message-
> From: Greg Kurz
> Sent: 2022年5月10日 0:20
> To: Shi, Guohuai
> Cc: Bin Meng ; Christian Schoenebeck
> ;
> qemu-devel@nongnu.org; Meng, Bin
> Subject: Re: [PATCH 5/9] hw/9pfs: Add a 'local' file system backend driver for
> Windows
>
> [Please note: This e-mail is
Ping
https://patchew.org/QEMU/20220321055618.4026-1-lu@verisilicon.com/
Please help review the patch.
Thanks.
B.R.
-邮件原件-
发件人: Gao, Lu
发送时间: Monday, April 25, 2022 9:35 AM
收件人: Gao, Lu; qemu-devel@nongnu.org
抄送: Wen, Jianxian; Philippe Mathieu-Daudé; Bin Meng; open list:SD (Secure C
在 2022/5/10 02:25, Richard Henderson 写道:
> On 5/9/22 13:04, Peter Maydell wrote:
>> On Mon, 9 May 2022 at 18:56, Richard Henderson
>> wrote:
>>> I'm not 100% sure how this "Other configuration control register" should be
>>> handled, but
>>> definitely not like this.
>>>
>>> I see you're putti
在 2022/5/10 10:54, maobibo 写道:
>
>
> 在 2022/5/10 02:25, Richard Henderson 写道:
>> On 5/9/22 13:04, Peter Maydell wrote:
>>> On Mon, 9 May 2022 at 18:56, Richard Henderson
>>> wrote:
I'm not 100% sure how this "Other configuration control register" should
be handled, but
definit
Hi Zhangfei,
On 2022/5/9 22:24, Zhangfei Gao wrote:
Hi, Alex
On 2022/4/27 上午12:35, Alex Williamson wrote:
On Tue, 26 Apr 2022 12:43:35 +
Shameerali Kolothum Thodi wrote:
-Original Message-
From: Eric Auger [mailto:eric.au...@redhat.com]
Sent: 26 April 2022 12:45
To: Shameerali K
On 5/9/22 19:54, maobibo wrote:
how about put address_space_iocsr as board rather than percpu since there is no
concept
of "cpu package".
"cpu package" works ok as a device on the board.
I don't know if it's possible to have the iocsr address space controlled by the device,
especially since
On Sat, May 7, 2022 at 10:28 AM Si-Wei Liu wrote:
>
> The name vhost_vdpa_one_time_request() was confusing. No
> matter whatever it returns, its typical occurrence had
> always been at requests that only need to be applied once.
> And the name didn't suggest what it actually checks for.
> Change i
Commit e42648dccd "qapi/expr.py: Remove single-letter variable"
accidentally removed the check for "only lower case letters and
hyphens". Restore it.
Fixes: e42648dccdd1defe8f35f247966cd7283f865cd6
Signed-off-by: Markus Armbruster
---
scripts/qapi/expr.py | 2 +-
1 file changed, 1 insertion(+),
Signed-off-by: Markus Armbruster
---
docs/devel/qapi-code-gen.rst | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/docs/devel/qapi-code-gen.rst b/docs/devel/qapi-code-gen.rst
index 7b968433a6..cd9b544376 100644
--- a/docs/devel/qapi-code-gen.rst
+++ b/docs/devel/qapi-c
Markus Armbruster (2):
qapi/expr: Enforce feature naming rules again
docs/devel/qapi-code-gen: Belatedly document feature naming rules
docs/devel/qapi-code-gen.rst | 9 +
scripts/qapi/expr.py | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
--
2.35.1
On 09/05/2022 19.59, Maciej S. Szmigiero wrote:
On 6.05.2022 07:31, Thomas Huth wrote:
On 05/05/2022 21.36, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This way there is at least some contact point for incoming patches.
We'll see whether the code still gets just a random patch a f
Hi Hi, Zhangfei,
On 5/10/22 05:17, Yi Liu wrote:
> Hi Zhangfei,
>
> On 2022/5/9 22:24, Zhangfei Gao wrote:
>> Hi, Alex
>>
>> On 2022/4/27 上午12:35, Alex Williamson wrote:
>>> On Tue, 26 Apr 2022 12:43:35 +
>>> Shameerali Kolothum Thodi wrote:
>>>
> -Original Message-
> From: Er
When allocating large amounts of memory the task is offloaded
onto threads. These threads then use various techniques to
allocate the memory fully (madvise(), writing into the memory).
However, these threads are free to run on any CPU, which becomes
problematic on NUMA machines because it may happe
On Wed, 4 May 2022 08:16:39 -0500
Suravee Suthikulpanit wrote:
> This is the maximum number of vCPU supported by
> the AMD x2APIC virtualization.
>
> Signed-off-by: Suravee Suthikulpanit
> ---
> hw/i386/pc_q35.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/i386/
The following changes since commit 554623226f800acf48a2ed568900c1c968ec9a8b:
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into
staging (2022-05-08 17:03:26 -0500)
are available in the Git repository at:
https://gitlab.com/thuth/qemu.git tags/pull-request-2022-05-09
f
STEXI and ETEXI is not used anymore since we switched to Sphinx.
Replace them in the example with SRST and ERST, too.
Message-Id: <20220506150146.564244-1-th...@redhat.com>
Reviewed-by: Markus Armbruster
Signed-off-by: Thomas Huth
---
docs/devel/writing-monitor-commands.rst | 11 ---
1
From: Gautam Agrawal
A global boolean variable "vga_interface_created"(declared in softmmu/globals.c)
has been used to track the creation of vga interface. If the vga flag is passed
in the command line "default_vga"(declared in softmmu/vl.c) variable is set to
0.
To warn user, the condition chec
On 08/05/2022 11:34, Bernhard Beschow wrote:
This function was declared in a generic and public header, implemented
in a device-specific source file but only used in xen_platform. Given its
'aux' parameter, this function is more xen-specific than piix-specific.
Also, the hardcoded magic constants
On Thu, May 5, 2022 at 1:38 PM Leif Lindholm wrote:
>
> NUVIA was acquired by Qualcomm in March 2021, but kept functioning on
> separate infrastructure for a transitional period. We've now switched
> over to contributing as Qualcomm Innocation Center (quicinc), so update
> my email address to refl
On Fri, May 06 2022, Janis Schoetterl-Glausch wrote:
> Make use of the storage key support of the MEMOP ioctl, if available,
> in order to support storage key checking during emulation.
>
> I did not update all the headers, since that broke the build,
> not sure what the best way of dealing with
Hi,
On 5/4/22 17:20, Eric Auger wrote:
> Up to now the virt-machine node only contains a virtio-mmio
> driver node but no driver that eventually produces any pci-bus
> interface.
>
> Hence, PCI libqos tests cannot be run with aarch64 binary.
>
> This series brings the pieces needed to be able to r
On Fri, May 6, 2022 at 11:16 PM Dylan Reid wrote:
>
> VS mode access to hypervisor CSRs should generate virtual, not illegal,
> instruction exceptions.
>
> Don't return early and indicate an illegal instruction exception when
> accessing a hypervisor CSR from VS mode. Instead, fall through to the
On Fri, May 06, 2022 at 07:28:17PM -0700, Si-Wei Liu wrote:
The name vhost_vdpa_one_time_request() was confusing. No
matter whatever it returns, its typical occurrence had
always been at requests that only need to be applied once.
And the name didn't suggest what it actually checks for.
Change it
On Mon, 9 May 2022 at 06:30, Markus Armbruster wrote:
> Always, always, *always* document your reasons for doing stuff right in
> the commit message, unless they are blindingly obvious. I understand
> reasons can be obvious enough to the author. Document them anyway if
> there is any chance they
From: Philippe Mathieu-Daudé
"qom/object.h" doesn't need to include itself.
Signed-off-by: Philippe Mathieu-Daudé
---
include/qom/object.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/qom/object.h b/include/qom/object.h
index 5f3d5b5bf5..ef7258a5e1 100644
--- a/include/qom/object
On Fri, May 6, 2022 at 11:25 AM Alex Bennée wrote:
>
>
> Bin Meng writes:
>
> > +more
> >
> > On Tue, May 3, 2022 at 11:44 AM Bin Meng wrote:
> >>
> >> On Thu, Apr 28, 2022 at 4:43 PM Bin Meng wrote:
> >> >
> >> > On Fri, Apr 22, 2022 at 11:00 AM Bin Meng wrote:
> >> > >
> >> > > +Richard
> >>
On Mon, May 9, 2022 at 5:07 PM Alistair Francis wrote:
>
> On Fri, May 6, 2022 at 11:25 AM Alex Bennée wrote:
> >
> >
> > Bin Meng writes:
> >
> > > +more
> > >
> > > On Tue, May 3, 2022 at 11:44 AM Bin Meng wrote:
> > >>
> > >> On Thu, Apr 28, 2022 at 4:43 PM Bin Meng wrote:
> > >> >
> > >> >
Signed-off-by: Alistair Francis
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 662ec47246..9ba30cec8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2173,6 +2173,7 @@ Generic Loader
M: Alistair Francis
S: Maintained
F: hw/core/generic-loade
On Fri, May 6, 2022 at 11:16 PM Dylan Reid wrote:
>
> VS mode access to hypervisor CSRs should generate virtual, not illegal,
> instruction exceptions.
>
> Don't return early and indicate an illegal instruction exception when
> accessing a hypervisor CSR from VS mode. Instead, fall through to the
On Thu, May 5, 2022 at 12:36 PM Anup Patel wrote:
>
> On Thu, May 5, 2022 at 3:21 PM Alistair Francis wrote:
> >
> > On Fri, Apr 29, 2022 at 1:38 PM Anup Patel wrote:
> > >
> > > Currently, QEMU does not set hstatus.GVA bit for traps taken from
> > > HS-mode into HS-mode which breaks the Xvisor
On Mon, May 9, 2022 at 4:42 PM Peter Maydell wrote:
>
> On Mon, 9 May 2022 at 06:30, Markus Armbruster wrote:
> > Always, always, *always* document your reasons for doing stuff right in
> > the commit message, unless they are blindingly obvious. I understand
> > reasons can be obvious enough to
On Fri, 6 May 2022 at 19:03, Richard Henderson
wrote:
>
> Changes for v6:
> * Expand the commit message for "Drop EL3 no EL2 fallbacks" (pmm)
>
> All patches are reviewed.
>
>
> r~
Applied to target-arm.next, thanks.
-- PMM
Hi Richard,
On 2022/5/7 下午11:31, Richard Henderson wrote:
On 4/29/22 05:07, Xiaojuan Yang wrote:
+ int ipmap_mask = 0xff << ipmap_offset;
...
+ int cpu_mask = 0xff << ipmap_offset;
These two masks are redundant with
+ ipnum = ((s->ipmap[ipmap_index] & ipmap_mask) >> ipmap_offset)
On 5/9/22 10:46, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
"qom/object.h" doesn't need to include itself.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
---
include/qom/object.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/qom/object.h
On Fri, Apr 29, 2022 at 5:36 AM Anup Patel wrote:>
> Currently, the [m|s]tval CSRs are set with trapping instruction encoding
> only for illegal instruction traps taken at the time of instruction
> decoding.
>
> In RISC-V world, a valid instructions might also trap as illegal or
> virtual instruct
On Mon, 9 May 2022 at 09:53, Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> "qom/object.h" doesn't need to include itself.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qom/object.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/include/qom/object.h b/in
On Fri, May 6, 2022 at 7:17 AM ~eopxd wrote:
>
> From: eopXD
>
> Vector whole register load instructions have EEW encoded in the opcode,
> so we shouldn't take SEW here. Vector whole register store instructions
> are always EEW=8.
>
> Signed-off-by: eop Chen
> Reviewed-by: Frank Chang
Acked-by
On Thu, 5 May 2022 at 12:39, Leif Lindholm wrote:
>
> The sbsa-ref machine is continuously evolving. Some of the changes we
> want to make in the near future, to align with real components (e.g.
> the GIC-700), will break compatibility for existing firmware.
>
> Introduce two new properties to the
Philippe Mathieu-Daudé writes:
> From: Philippe Mathieu-Daudé
>
> "qom/object.h" doesn't need to include itself.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qom/object.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/include/qom/object.h b/include/qom/object.h
> index 5f
On Wed, Apr 27, 2022 at 03:35:35PM +0100, Stefan Hajnoczi wrote:
> Nir Soffer reported that virtio-scsi,iothread=... consumes 100% CPU in QEMU
> 7.0. This patch series addresses two bugs in hw/scsi/virtio-scsi.c (see
> patches
> 1 & 2) and follows up with code cleanups.
>
> Stefan Hajnoczi (6):
>
Hi,
> Oh, I see now -- qemu_disable_default_devices() does a
> preliminary scan through of every supplied -device option,
> looking to see if it has a driver=foo that matches some
> value in the default_list[] array; if it does then we
> set default_vga or whatever to false. (So effectively we
>
Am 9. Mai 2022 08:02:13 UTC schrieb "Durrant, Paul" :
>On 08/05/2022 11:34, Bernhard Beschow wrote:
>> This function was declared in a generic and public header, implemented
>> in a device-specific source file but only used in xen_platform. Given its
>> 'aux' parameter, this function is more xen-sp
On Sun, Apr 24, 2022 at 7:22 AM Tsukasa OI wrote:
>
> Because some operating systems don't correctly parse long ISA extension
> string, this commit adds short-isa-string boolean option to disable
> generating long ISA extension strings on Device Tree.
>
> Operating Systems which short-isa-string m
On 5/9/22 08:42, Lukáš Doktor wrote:
Dne 06. 05. 22 v 20:55 Lukáš Doktor napsal(a):
Hello Paolo, folks, I gave it a try (on top of the f9fc8932) and
it's better than the f9fc8932, better than the previous patch by
Stefan, but still I'm not reaching the performance of d7482ffe97
(before the f9fc8
On Fri, May 6, 2022 at 7:17 AM ~eopxd wrote:
>
> From: eopXD
>
> Vector whole register load instructions have EEW encoded in the opcode,
> so we shouldn't take SEW here. Vector whole register store instructions
> are always EEW=8.
>
> Signed-off-by: eop Chen
> Reviewed-by: Frank Chang
Thanks!
The ``loaded=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``loaded`` was the last option) or caused options to be
effectively ignored as if they were not given. The property is therefore
useless and was deprecated in 6.0; make it read-only now.
The patch is best
Hi!
Sorry for taking some time to reply.
On Tue, Apr 19, 2022 at 11:12:28AM -0700, Andrea Bolognani wrote:
> On Sat, Apr 02, 2022 at 12:40:56AM +0200, Victor Toso wrote:
> > Thanks for taking a look, let me know if you have questions, ideas
> > or suggestions.
>
> Full disclosure: I have only gi
On 2022/5/7 下午11:31, Richard Henderson wrote:
+ if (level) {
+ /* if not enable return false */
+ if (((s->enable[enable_index]) & (1 << enable_mask)) == 0) {
+ return;
+ }
+ s->coreisr[cpu][coreisr_index] |= (1 << coreisr_mask);
+ qemu_set_irq(s-
This is the initial result of reviving Marc-André's series at
https://patchew.org/QEMU/20170704220346.29244-1-marcandre.lur...@redhat.com/.
A lot of the patches are similar to the ones that Marc-André wrote,
but due to the changes in the code it was easier to redo them.
For nbd, the patch is on to
qemu_coroutine_get_aio_context inspects a coroutine, but it does
not have to be called from the coroutine itself (or from any
coroutine).
Signed-off-by: Paolo Bonzini
---
include/qemu/coroutine.h | 2 +-
util/qemu-coroutine.c| 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --gi
The ``opened=on`` option in the command line or QMP ``object-add`` either had
no effect (if ``opened`` was the last option) or caused errors. The property
is therefore useless and was deprecated in 6.0; make it read-only now.
Based-on: <20220509101907.212687-1-pbonz...@redhat.com>
Signed-off-by:
This is incorrect because qcow2_mark_clean() calls qcow2_flush_caches().
qcow2_mark_clean() is called from non-coroutine context in
qcow2_inactivate() and qcow2_close().
Signed-off-by: Paolo Bonzini
---
block/qcow2-refcount.c | 4 ++--
block/qcow2.h | 4 ++--
2 files changed, 4 insertio
Signed-off-by: Paolo Bonzini
---
block/blkdebug.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/block/blkdebug.c b/block/blkdebug.c
index bbf2948703..a93ba61487 100644
--- a/block/blkdebug.c
+++ b/block/blkdebug.c
@@ -587,8 +587,8 @@ out:
return ret;
}
nbd_co_establish_connection_cancel() cancels a coroutine but is not called
from coroutine context itself, for example in nbd_cancel_in_flight()
and in timer callbacks reconnect_delay_timer_cb() and open_timer_cb().
Signed-off-by: Paolo Bonzini
---
include/block/nbd.h | 2 +-
1 file changed, 1 in
Signed-off-by: Paolo Bonzini
---
block/iscsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/iscsi.c b/block/iscsi.c
index d707d0b354..b33eeec794 100644
--- a/block/iscsi.c
+++ b/block/iscsi.c
@@ -290,7 +290,7 @@ iscsi_co_generic_cb(struct iscsi_context *iscsi, int sta
Signed-off-by: Paolo Bonzini
---
block/block-backend.c | 18 +-
block/io.c| 24
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/block/block-backend.c b/block/block-backend.c
index fedf2eca83..52009b8949 100644
--- a/block/block
Signed-off-by: Paolo Bonzini
---
block/blkverify.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/blkverify.c b/block/blkverify.c
index e4a37af3b2..020b1ae7b6 100644
--- a/block/blkverify.c
+++ b/block/blkverify.c
@@ -258,7 +258,7 @@ blkverify_co_pwritev(BlockDriverStat
This is incorrect because blk_pwritev_part() is called by
blk_pwrite_zeroes() and blk_pwrite(), neither of which has to be called
from a coroutine.
Signed-off-by: Paolo Bonzini
---
block/block-backend.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/block/block-backe
Signed-off-by: Paolo Bonzini
---
block/parallels.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index 8879b7027a..bee2ff023d 100644
--- a/block/parallels.c
+++ b/block/parallels.c
@@ -165,8 +165,9 @@ static int64_t block_status(BDR
Signed-off-by: Paolo Bonzini
---
block/nfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/nfs.c b/block/nfs.c
index 444c40b458..596ebe98cb 100644
--- a/block/nfs.c
+++ b/block/nfs.c
@@ -223,7 +223,7 @@ static void nfs_process_write(void *arg)
qemu_mutex_unlock(&c
Signed-off-by: Paolo Bonzini
---
block/nbd.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/block/nbd.c b/block/nbd.c
index 6085ab1d2c..fe913a6db4 100644
--- a/block/nbd.c
+++ b/block/nbd.c
@@ -983,11 +983,11 @@ static void nbd_iter_request_error(NBDReplyChunkIter
Signed-off-by: Paolo Bonzini
---
block/file-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/file-posix.c b/block/file-posix.c
index 48cd096624..76eea8d350 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -2158,7 +2158,7 @@ static void raw_aio_unplug(Bl
Signed-off-by: Paolo Bonzini
---
block/quorum.c | 35 ++-
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/block/quorum.c b/block/quorum.c
index f33f30d36b..5ff69d7443 100644
--- a/block/quorum.c
+++ b/block/quorum.c
@@ -161,11 +161,10 @@ static bool
Signed-off-by: Paolo Bonzini
---
block/copy-before-write.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/block/copy-before-write.c b/block/copy-before-write.c
index a8a06fdc09..5ad9693b13 100644
--- a/block/copy-before-write.c
+++ b/block/copy-before-write.c
@@ -165,
Signed-off-by: Paolo Bonzini
---
include/qemu/job.h | 2 +-
job.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/job.h b/include/qemu/job.h
index c105b31076..397ac39608 100644
--- a/include/qemu/job.h
+++ b/include/qemu/job.h
@@ -436,7 +436,7 @@ v
Signed-off-by: Paolo Bonzini
---
block/qcow2-cluster.c | 18 +-
block/qcow2-refcount.c | 2 +-
block/qcow2.c | 4 ++--
block/qcow2.h | 14 +++---
4 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/block/qcow2-cluster.c b/block/qcow2-clust
Signed-off-by: Paolo Bonzini
---
block/nvme.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/block/nvme.c b/block/nvme.c
index 01fb28aa63..6519697e40 100644
--- a/block/nvme.c
+++ b/block/nvme.c
@@ -1234,8 +1234,9 @@ static inline bool nvme_qiov_aligned(BlockDriverState
Signed-off-by: Paolo Bonzini
---
block/qed.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/block/qed.c b/block/qed.c
index f34d9a3ac1..208128d679 100644
--- a/block/qed.c
+++ b/block/qed.c
@@ -259,7 +259,7 @@ static CachedL2Table *qed_new_l2_table(BDRVQEDState *s)
r
Signed-off-by: Paolo Bonzini
---
block/raw-format.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/raw-format.c b/block/raw-format.c
index 69fd650eaf..45440345b6 100644
--- a/block/raw-format.c
+++ b/block/raw-format.c
@@ -411,7 +411,7 @@ static void raw_lock_medium(Blo
Signed-off-by: Paolo Bonzini
---
block/curl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/curl.c b/block/curl.c
index 1e0f609579..cba4c4cac7 100644
--- a/block/curl.c
+++ b/block/curl.c
@@ -855,7 +855,7 @@ out_noclean:
return -EINVAL;
}
-static void curl_setu
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Message-Id: <20170704220346.29244-4-marcandre.lur...@redhat.com>
Signed-off-by: Paolo Bonzini
---
tests/unit/test-coroutine.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/unit/test-coroutine.c b/tests/unit/te
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Acked-by: Greg Kurz
Signed-off-by: Paolo Bonzini
---
hw/9pfs/9p.h | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/9pfs/9p.h b/hw/9pfs/9p.h
index 994f952600..a523ac34a9 100644
--- a/hw/9pfs/9p.h
+++ b/hw/9
Signed-off-by: Paolo Bonzini
---
util/qemu-coroutine-lock.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/util/qemu-coroutine-lock.c b/util/qemu-coroutine-lock.c
index 2669403839..ec55490b52 100644
--- a/util/qemu-coroutine-lock.c
+++ b/util/qemu-coroutine-loc
Signed-off-by: Paolo Bonzini
---
block/throttle.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/block/throttle.c b/block/throttle.c
index 6e8d52fa24..ddd450593a 100644
--- a/block/throttle.c
+++ b/block/throttle.c
@@ -162,7 +162,7 @@ static int coroutine_fn
throttle_co_pwri
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
Reviewed-by: Juan Quintela
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
migration/migration.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/migration/migration.c b/migration/migration.c
index 5a
On Mon, May 09, 2022 at 12:19:07PM +0200, Paolo Bonzini wrote:
> The ``loaded=on`` option in the command line or QMP ``object-add`` either had
> no effect (if ``loaded`` was the last option) or caused options to be
> effectively ignored as if they were not given. The property is therefore
> useles
Signed-off-by: Paolo Bonzini
---
block/vmdk.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/block/vmdk.c b/block/vmdk.c
index 38e5ab3806..2c7f1858f9 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -1793,10 +1793,10 @@ static int coroutine_fn
vmdk_co_b
On Thu, 5 May 2022 at 17:43, Richard Henderson
wrote:
>
> On 5/5/22 03:42, Stefan Hajnoczi wrote:
> > The following changes since commit 9cf289af47bcfae5c75de37d8e5d6fd23705322c:
> >
> >Merge tag 'qga-pull-request' of gitlab.com:marcandre.lureau/qemu into
> > staging (2022-05-04 03:42:49 -070
On Mon, 9 May 2022 at 04:08, Gavin Shan wrote:
>
> Hi Peter and maintainers,
>
> On 5/3/22 10:02 PM, Gavin Shan wrote:
> > When the CPU-to-NUMA association isn't provided by user, the default NUMA
> > node ID for the specific CPU is returned from
> > virt_get_default_cpu_node_id().
> > Unfortunat
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