There are two arrays for each CPU, to store the indexes and values of the
coprocessor registers. Currently, 8 bytes fixed storage space is reserved
for each coprocessor register. However, larger coprocessor registers have
been defined and exposed by KVM. Except SVE registers, no coprocessor
registe
Similar to what we did for TCG, this uses @cpreg_value_indexes[] to
track the storage space for the corresponding coprocessor register.
As all coprocessor register have fixed 8 bytes storage space, so
the indirect and direct addressing mechanisms can co-exist and
interchangeable, even in migration
Similar to what we did for TCG, this uses @cpreg_value_indexes[] to
track the storage space for the corresponding coprocessor register.
As all coprocessor register have fixed 8 bytes storage space, so
the indirect and direct addressing mechanisms can co-exist and
interchangeable, even in migration
This migrates @cpreg_value_array_len and @cpreg_value_indexes, which
are used to indirectly addressing the storage space for the corresponding
coprocessor register.
Signed-off-by: Gavin Shan
---
target/arm/machine.c | 30 --
1 file changed, 24 insertions(+), 6 deletio
With the indirect addressing mechanism, we can support large-sized
coprocessor registers. This calculates the length of @cpreg_values
and allocate the storage space accordingly. @cpreg_value_indexes
is also initialized according to the coprocessor register size.
For those registers whose sizes are
On 4/8/22 18:47, Thomas Huth wrote:
The only one that still seems to be missing a libslirp package is
OpenBSD - but I assume that they can add it to their ports system
quickly if required.
So there is no real urgent need for keeping the slirp submodule in
the QEMU tree anymore. Thus let's drop t
On 11/04/2022 08.57, Bin Meng wrote:
On Mon, Apr 11, 2022 at 2:45 PM Thomas Huth wrote:
On 08/04/2022 21.19, Daniel Henrique Barboza wrote:
On 4/6/22 07:08, Bin Meng wrote:
On Tue, Apr 5, 2022 at 10:36 PM Guo Zhi wrote:
There are still some files in the QEMU PPC code base that use TABs
On 4/11/22 09:11, Paolo Bonzini wrote:
On 4/8/22 18:47, Thomas Huth wrote:
The only one that still seems to be missing a libslirp package is
OpenBSD - but I assume that they can add it to their ports system
quickly if required.
So there is no real urgent need for keeping the slirp submodule in
Hello Jamin,
[ ... ]
Do we want to be in sync with the zephyr naming and use ast10x0.c ?
https://github.com/zephyrproject-rtos/zephyr/tree/main/soc/arm/aspeed
We used aspeed_ast10xx.c to support minibmc family such as ast1030 and
may support ast1060 in the future.
If need, I can submit
On Sat, Apr 9, 2022 at 1:17 AM Si-Wei Liu wrote:
>
>
>
> On 4/8/2022 1:38 AM, Michael Qiu wrote:
> >
> >
> > 在 2022/4/7 15:35, Jason Wang 写道:
> >>
> >> 在 2022/4/2 下午1:14, Michael Qiu 写道:
> >>>
> >>>
> >>> On 2022/4/2 10:38, Jason Wang wrote:
>
> 在 2022/4/1 下午7:06, Michael Qiu 写道:
> >
On Fri, Apr 8, 2022 at 9:02 AM Si-Wei Liu wrote:
>
>
>
> On 4/7/2022 12:05 AM, Jason Wang wrote:
> >
> > 在 2022/4/6 上午3:18, Si-Wei Liu 写道:
> >>
> >>
> >> On 4/1/2022 7:00 PM, Jason Wang wrote:
> >>> On Sat, Apr 2, 2022 at 4:37 AM Si-Wei Liu
> >>> wrote:
>
>
> On 3/31/2022 1:36 AM,
The 04/11/2022 08:23, Cédric Le Goater wrote:
> Hello Jamin,
>
> [ ... ]
>
> >> Do we want to be in sync with the zephyr naming and use ast10x0.c ?
> >>
> >> https://github.com/zephyrproject-rtos/zephyr/tree/main/soc/arm/aspeed
> >>
> > We used aspeed_ast10xx.c to support minibmc family such
On Mon, 11 Apr 2022 at 07:59, Gavin Shan wrote:
>
> There are two arrays for each CPU, to store the indexes and values of the
> coprocessor registers. Currently, 8 bytes fixed storage space is reserved
> for each coprocessor register. However, larger coprocessor registers have
> been defined and e
Hi Peter,
On 4/11/22 5:22 PM, Peter Maydell wrote:
On Mon, 11 Apr 2022 at 07:59, Gavin Shan wrote:
There are two arrays for each CPU, to store the indexes and values of the
coprocessor registers. Currently, 8 bytes fixed storage space is reserved
for each coprocessor register. However, larger
Paolo Bonzini writes:
> The first eight patches simplify and clean up a bit the
> tests/docker/Makefile.include file.
Queued to testing/next, thanks.
--
Alex Bennée
On Mon, 11 Apr 2022 at 10:50, Gavin Shan wrote:
> On 4/11/22 5:22 PM, Peter Maydell wrote:
> > So, can you give an example of coprocessor registers which are
> > not 8 bytes in size? How are they accessed by the guest?
> > If we need to support them then we need to support them, but this
> > cover
On Thu, 31 Mar 2022 at 23:20, Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> This adds the 4 TTC timers in the Xilinx ZynqMP.
> This is for after the 7.0.0 release.
>
> Cheers,
> Edgar
>
> Edgar E. Iglesias (2):
> timer: cadence_ttc: Break out header file to allow embedding
> hw/a
v3 -> v4:
- Coding style fix: Akcipher -> AkCipher, struct XXX -> XXX, Rsa -> RSA,
XXX-alg -> XXX-algo.
- Change version info in qapi/crypto.json, from 7.0 -> 7.1.
- Remove ecdsa from qapi/crypto.json, it would be introduced with the
implemetion later.
- Use QCryptoHashAlgothrim instead of QCrypto
Update header from linux, support akcipher service.
Reviewed-by: Gonglei
Signed-off-by: lei he
Signed-off-by: zhenwei pi
---
.../standard-headers/linux/virtio_crypto.h| 82 ++-
1 file changed, 81 insertions(+), 1 deletion(-)
diff --git a/include/standard-headers/linux/virt
Support basic asymmetric operations: encrypt, decrypt, sign and
verify.
Co-developed-by: lei he
Signed-off-by: lei he
Signed-off-by: zhenwei pi
---
crypto/akcipher.c | 102 +
crypto/akcipherpriv.h | 43 +++
crypto/meson.build| 1 +
include
From: Lei He
Introduce akcipher types, also include RSA related types.
Signed-off-by: Lei He
Signed-off-by: zhenwei pi
---
qapi/crypto.json | 64
1 file changed, 64 insertions(+)
diff --git a/qapi/crypto.json b/qapi/crypto.json
index 1ec54c15c
From: Lei He
Add an ANS.1 decoder which is used to parse asymmetric
cipher keys
Signed-off-by: zhenwei pi
Signed-off-by: Lei He
---
crypto/asn1_decoder.c | 161 ++
crypto/asn1_decoder.h | 75 +++
crypto/meson.build| 1 +
t
On Wed, 6 Apr 2022 at 18:43, Edgar E. Iglesias
wrote:
>
> From: "Edgar E. Iglesias"
>
> This adds the Versal Cortex-R5s in the Real-Time Processing Unit
> (RPU) subsystem.
>
> A model of the Clock/Reset Low-power domain (CRL) is also added
> allowing runtime release of the Cortex-R5s. The RPU sub
There are two parts in this patch:
1, support akcipher service by cryptodev-builtin driver
2, virtio-crypto driver supports akcipher service
In principle, we should separate this into two patches, to avoid
compiling error, merge them into one.
Then virtio-crypto gets request from guest side, and
From: Lei He
Implement RSA algorithm by hogweed from nettle. Thus QEMU supports
a 'real' RSA backend to handle request from guest side. It's
important to test RSA offload case without OS & hardware requirement.
Signed-off-by: Lei He
Signed-off-by: zhenwei pi
---
crypto/akcipher-nettle.c.inc |
From: Lei He
Added gcryt implementation of RSA algorithm, RSA algorithm
implemented by gcrypt has a higher priority than nettle because
it supports raw padding.
Signed-off-by: Lei He
---
crypto/akcipher-gcrypt.c.inc | 531 +++
crypto/akcipher.c| 4
From: lei he
Add unit test and benchmark test for crypto akcipher.
Signed-off-by: lei he
Signed-off-by: zhenwei pi
---
tests/bench/benchmark-crypto-akcipher.c | 161 ++
tests/bench/meson.build | 4 +
tests/bench/test_akcipher_keys.inc | 537 ++
tests
On Wed, 6 Apr 2022 at 23:34, Hao Wu wrote:
>
> Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
> the PWRON STRAP fields in their corresponding module for NPCM7XX.
>
> Signed-off-by: Hao Wu
> Reviewed-by: Patrick Venture
> ---
> include/hw/misc/npcm7xx_gcr.h | 30 +
On Wed, 6 Apr 2022 at 23:34, Hao Wu wrote:
>
> This patch uses the defined fields to describe PWRON STRAPs for
> better readability.
>
> Signed-off-by: Hao Wu
> Reviewed-by: Patrick Venture
> ---
> hw/arm/npcm7xx_boards.c | 24 +++-
> 1 file changed, 19 insertions(+), 5 dele
* jianchunfu (jianchu...@cmss.chinamobile.com) wrote:
> Using macro g_new() to handling potential memory allocation failures
> in dirtyrate.
>
> Signed-off-by: jianchunfu
> ---
> migration/dirtyrate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/migration/dirtyra
On Mon, Apr 11, 2022 at 10:22:59AM +0100, Peter Maydell wrote:
> On Mon, 11 Apr 2022 at 07:59, Gavin Shan wrote:
> >
> > There are two arrays for each CPU, to store the indexes and values of the
> > coprocessor registers. Currently, 8 bytes fixed storage space is reserved
> > for each coprocessor
On Mon, 11 Apr 2022 at 13:02, Andrew Jones wrote:
>
> On Mon, Apr 11, 2022 at 10:22:59AM +0100, Peter Maydell wrote:
> > Also, we support SVE today, and we don't have variable size
> > coprocessor registers. Is there a bug here that we would be
> > fixing ?
>
> SVE registers are KVM_REG_SIZE_U2048
* Maxime Coquelin (maxime.coque...@redhat.com) wrote:
> This patch documents RSS feature in Vhost-user specification.
> Two new requests are introduced backed by a dedicated
> protocol feature.
>
> First one is to query the Vhost-user slave RSS capabilities
> such as supported hash types, maximum
On Sat, 9 Apr 2022 at 01:10, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 15 +++
> 1 file changed, 15 insertions(+)
>
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sat, 9 Apr 2022 at 01:09, Richard Henderson
wrote:
>
> This register is present for either VHE or Debugv8p2, and is
> RES0 from EL3 when EL2 is not present. Move the definition
> out of vhe_reginfo and provide a fallback for missing EL2.
>
> Signed-off-by: Richard Henderson
> ---
> target/ar
On Sat, 9 Apr 2022 at 01:10, Richard Henderson
wrote:
>
> We set this for qemu-system-aarch64, but failed to do so
> for the strictly 32-bit emulation.
>
> Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'")
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu_tcg.c | 4 +++
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Share the code to set AArch32 max features so that we no
> longer have code drift between qemu{-system,}-{arm,aarch64}.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/internals.h | 2 +
> target/arm/cpu64.c | 51 +-
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Update the legacy feature names to the current names.
> Provide feature names for id changes that were not marked.
> Sort the field updates into increasing bitfield order.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
On Sat, 9 Apr 2022 at 01:08, Richard Henderson
wrote:
>
> Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
> during arm_cpu_realizefn.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.c | 22 +-
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
Reviewe
This patch adds tcg accessors for 2 SPRs which were missing on P10:
- the TBU40 register is used to write the upper 40 bits of the
timebase register. It is used by kvm to update the timebase when
entering/exiting the guest on P9 and above. The missing definition was
causing erratic decrementer int
On Sat, 9 Apr 2022 at 01:18, Richard Henderson
wrote:
>
> The only portion of FEAT_Debugv8p2 that is relevant to QEMU
> is CONTEXTIDR_EL2, which is also conditionally implemented
> with FEAT_VHE. The rest of the debug extension concerns the
> External debug interface, which is outside the scope o
On Sat, 9 Apr 2022 at 01:18, Richard Henderson
wrote:
>
> This extension concerns changes to the External Debug interface,
> with Secure and Non-secure access to the debug registers, and all
> of it is outside the scope of QEMU. Indicating support for this
> is mandatory with FEAT_SEL2, which we
On Sat, 9 Apr 2022 at 01:23, Richard Henderson
wrote:
>
> Add the aa64 predicate for detecting RAS support from id registers.
> We already have the aa32 version from the M-profile work.
> Add the 'any' predicate for testing both aa64 and aa32.
>
> Signed-off-by: Richard Henderson
> ---
> target/
Using macro g_new() to handling potential memory allocation failures
in dirtyrate.
Signed-off-by: jianchunfu
---
migration/dirtyrate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/migration/dirtyrate.c b/migration/dirtyrate.c
index aace12a787..0e59aacbb0 100644
--- a/m
On Wed, Apr 06, 2022 at 11:24:10AM -0500, Sakshi Kaushik wrote:
> Signed-off-by: Sakshi Kaushik
> ---
> contrib/vhost-user-scsi/vhost-user-scsi.c | 78 +++
> 1 file changed, 52 insertions(+), 26 deletions(-)
Thanks, I have applied this patch to my block-next branch!
I made a
From: Philippe Mathieu-Daudé
Per
https://discourse.gnome.org/t/port-your-module-from-g-memdup-to-g-memdup2-now/5538
The old API took the size of the memory to duplicate as a guint,
whereas most memory functions take memory sizes as a gsize. This
made it easy to accidentally pass a gsize t
Control virtqueue is used by networking device for accepting various
commands from the driver. It's a must to support multiqueue and other
configurations.
Shadow VirtQueue (SVQ) already makes possible migration of virtqueue
states, effectively intercepting them so qemu can track what regions of me
Fixes: 6d0b222666 ("vdpa: Adapt vhost_vdpa_get_vring_base to SVQ")
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 9e5fe15d03..1f229ff4cb 100644
--- a/hw/virtio/v
From: Anthony PERARD
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as started could be ignored and not transfered to the
des
These functions were not traced properly.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 2 ++
hw/virtio/trace-events | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 8adf7c0b92..9e5fe15d03 100644
--- a/hw/virtio/vhost-vdpa.c
To know the device features is also needed for CVQ SVQ. Extract from
vhost_vdpa_get_max_queue_pairs so we can reuse it.
Report errno in case of failure getting them while we're at it.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 30 --
1 file changed, 20 inser
Finally offering the possibility to enable SVQ from the command line.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 9 -
net/vhost-vdpa.c | 48
2 files changed, 48 insertions(+), 9 deletions(-)
diff --git a/qapi/net.json b/qapi/net
The callback allows SVQ users to know the VirtQueue requests and
responses. QEMU can use this to synchronize virtio device model state,
allowing to migrate it with minimum changes to the migration code.
In the case of networking, this will be used to inspect control
virtqueue messages.
Signed-off
It always returns IOVA_OK so nobody uses it.
Signed-off-by: Eugenio Pérez
---
include/qemu/iova-tree.h | 4 +---
util/iova-tree.c | 4 +---
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/include/qemu/iova-tree.h b/include/qemu/iova-tree.h
index c938fb0793..16bbfdf5f8 1006
This allows qemu to inject packets to the device without guest's notice.
This will be use to inject net CVQ messages to restore status in the destination
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 5 +
hw/virtio/vhost-shadow-virtqueue.c | 179 +++
It's done for both in and out descriptors so it's better placed here.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/hw/virtio/vhost-shadow-virtqueue.c
b/hw/virtio/vhost-shadow-
Only the first one of them were properly enqueued back.
Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding")
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/hw/virtio/vhost-shad
Signed-off-by: Eugenio Pérez
---
include/standard-headers/linux/vhost_types.h | 11 -
linux-headers/linux/vhost.h | 25
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/include/standard-headers/linux/vhost_types.h
b/include/standard-he
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 1f229ff4cb..3f8fa66e8e 100644
--- a/hw/virtio/vhost-vdpa.c
+++ b/hw/virtio/vhost-vdpa.c
@@ -1018,7 +1018,7 @@ static bo
This isolates shadow cvq in its own group.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 8 +++-
net/vhost-vdpa.c | 98 ++--
2 files changed, 100 insertions(+), 6 deletions(-)
diff --git a/qapi/net.json b/qapi/net.json
index 92848e4362..39c245e
It allows to inject custom code on device success start, right before
release lock.
Signed-off-by: Eugenio Pérez
---
include/net/net.h | 2 ++
hw/net/vhost_net.c | 4
2 files changed, 6 insertions(+)
diff --git a/include/net/net.h b/include/net/net.h
index 523136c7ac..2fc3002ab4 100644
--
This allows external vhost-net devices to modify the state of the
VirtIO device model once vhost-vdpa device has acknowledge the control
commands.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio-net.h | 3 ++
hw/net/virtio-net.c| 83 --
2 fi
We can configure ASID per group, but we still use asid 0 for every vdpa
device. Multiple asid support for cvq will be introduced in next
patches
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 4 ++
hw/net/vhost_net.c| 5 ++
hw/virtio/vhost-vdpa.c| 97 +
When change b7711471f5 was made to alias XMMReg to ZMMReg for the
purposes of easing the handling of AVX512 registers we unwittingly
broke the SSE helpers which construct a temporary value on the stack
before copying them out. To avoid this lets encode REG_WIDTH based on
shift and convert the point
This will send CVQ commands in the destination machine, seting up
everything o there is no guest-visible change.
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 63
1 file changed, 63 insertions(+)
diff --git a/net/vhost-vdpa.c b/net/vhost-vd
So SVQ can allocate elements using it
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/virtio.h | 1 +
hw/virtio/virtio.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h
index b31c4507f5..1e85833897 100644
--
The GLib documentation says "a NULL-terminated array of GOptionEntrys"
so we'd better make sure there is a terminator that lets
g_option_context_add_main_entries() know when the end of the array has
been reached.
Signed-off-by: Stefan Hajnoczi
---
contrib/vhost-user-blk/vhost-user-blk.c | 3 ++-
Introduce the control virtqueue support for vDPA shadow virtqueue. This
is needed for advanced networking features like multiqueue.
To demonstrate command handling, VIRTIO_NET_F_CTRL_MACADDR and
VIRTIO_NET_CTRL_MQ are implemented. If vDPA device is started with SVQ
support and virtio-net driver ch
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 21 +++--
hw/virtio/vhost-shadow-virtqueue.c | 8 +++-
hw/virtio/vhost-vdpa.c | 20 +++-
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/hw/virtio/vhost-shadow-vi
Frederic Barrat writes:
> This patch adds tcg accessors for 2 SPRs which were missing on P10:
>
> - the TBU40 register is used to write the upper 40 bits of the
> timebase register. It is used by kvm to update the timebase when
> entering/exiting the guest on P9 and above. The missing definition
Just a simple wrapper so we can find DMAMap entries based on iova
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-iova-tree.h | 2 ++
hw/virtio/vhost-iova-tree.c | 14 ++
2 files changed, 16 insertions(+)
diff --git a/hw/virtio/vhost-iova-tree.h b/hw/virtio/vhost-iova-tree.h
index
This allows SVQ to add metadata to the different queue elements
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 8 --
hw/virtio/vhost-shadow-virtqueue.c | 42 --
2 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/hw/virtio/vhos
On Mon, 11 Apr 2022 at 15:56, Alex Bennée wrote:
>
> When change b7711471f5 was made to alias XMMReg to ZMMReg for the
> purposes of easing the handling of AVX512 registers we unwittingly
> broke the SSE helpers which construct a temporary value on the stack
> before copying them out. To avoid thi
CVQ needs to be in its own group, not shared with any data vq. Enable
the checking of it here, before introducing address space id concepts.
Signed-off-by: Eugenio Pérez
---
include/hw/virtio/vhost.h | 2 +
hw/net/vhost_net.c| 4 +-
hw/virtio/vhost-vdpa.c| 79 ++
Itaru Kitayama writes:
> Good point; however per the SBSA specification, DEN0029F, there's the
> PE architecture requirement at
> each level from 1 to 7, so now I am wondering whether supporting
> cortex-a57 and a72 are good enough to
> set up a fully SBSA level 7 compliant "board" in QMEU.
No
On Thu, Mar 10, 2022 at 10:09:01PM +0800, Chao Peng wrote:
> diff --git a/mm/shmem.c b/mm/shmem.c
> index 9b31a7056009..7b43e274c9a2 100644
> --- a/mm/shmem.c
> +++ b/mm/shmem.c
> @@ -903,6 +903,28 @@ static struct folio *shmem_get_partial_folio(struct
> inode *inode, pgoff_t index)
> return
On Thu, Mar 10, 2022 at 10:08:59PM +0800, Chao Peng wrote:
> From: "Kirill A. Shutemov"
>
> Introduce a new memfd_create() flag indicating the content of the
> created memfd is inaccessible from userspace through ordinary MMU
> access (e.g., read/write/mmap). However, the file content can be
> ac
On Fri, Apr 08, 2022 at 09:02:54PM +0800, Chao Peng wrote:
> > I think the correct approach is to not do the locking automatically for
> > SHM_F_INACCESSIBLE,
> > and instead require userspace to do shmctl(.., SHM_LOCK, ...) if userspace
> > knows the
> > consumers don't support migrate/swap. Th
Richard Henderson writes:
> On 4/9/22 20:58, jianchunfu wrote:
>> Handling potential memory allocation failures in dirtyrate.
>> Signed-off-by: jianchunfu
>> ---
>> migration/dirtyrate.c | 8
>> 1 file changed, 8 insertions(+)
>> diff --git a/migration/dirtyrate.c b/migration/dirty
On Thu, Apr 07, 2022 at 04:05:36PM +, Sean Christopherson wrote:
> Hmm, shmem_writepage() already handles SHM_F_INACCESSIBLE by rejecting the
> swap, so
> maybe it's just the page migration path that needs to be updated?
My early version prevented migration with -ENOTSUPP for
address_space_op
> -Original Message-
> From: Anton Johansson
> Sent: Wednesday, February 9, 2022 11:03 AM
> To: qemu-devel@nongnu.org
> Cc: a...@rev.ng; Taylor Simpson ; Brian Cain
> ; Michael Lambert ;
> bab...@rev.ng; ni...@rev.ng; richard.hender...@linaro.org
> Subject: [PATCH v8 10/12] target/hexag
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Instead of starting with cortex-a15 and adding v8 features to
> a v7 cpu, begin with a v8 cpu stripped of its aarch64 features.
> This fixes the long-standing to-do where we only enabled v8
> features for user-only.
>
> Signed-off-by: Richa
On Mon, Apr 11, 2022 at 04:00:57PM +0100, Stefan Hajnoczi wrote:
> The GLib documentation says "a NULL-terminated array of GOptionEntrys"
> so we'd better make sure there is a terminator that lets
> g_option_context_add_main_entries() know when the end of the array has
> been reached.
>
> Signed-o
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Add only the system registers required to implement zero error
> records. This means we need to save state for ERRSELR, but all
> values are out of range, so none of the indexed error record
> registers need be implemented.
>
> Add the EL2
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Enable writes to the TERR and TEA bits when RAS is enabled.
> These bits are otherwise RES0.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.c | 9 +
> 1 file changed, 9 insertions(+)
Reviewed-by: Peter Maydell
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Virtual SError exceptions are raised by setting HCR_EL2.VSE,
> and are routed to EL1 just like other virtual exceptions.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 2 ++
> target/arm/internals.h | 8
>
On Sat, 9 Apr 2022 at 01:18, Richard Henderson
wrote:
>
> Check for and defer any pending virtual SError.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/helper.h| 1 +
> target/arm/a32.decode | 16 +-
> target/arm/t32.decode | 18 +++
> target/
On 3/29/2022 7:03 AM, Fam Zheng wrote:
> On 2021-08-06 14:43, Steve Sistare wrote:
>> Preserve vfio INTX state across cpr restart. Preserve VFIOINTx fields as
>> follows:
>> pin : Recover this from the vfio config in kernel space
>> interrupt : Preserve its eventfd descriptor across exec.
>>
On 4/11/22 08:37, Peter Maydell wrote:
+/* aarch64_a57_initfn, advertising none of the aarch64 features */
+cpu->dtb_compatible = "arm,cortex-a57";
+set_feature(&cpu->env, ARM_FEATURE_V8);
+set_feature(&cpu->env, ARM_FEATURE_NEON);
+set_feature(&cpu->env, ARM_FEATURE_GENERIC_T
On 4/11/22 10:47, Anthony PERARD wrote:
From: Anthony PERARD
At the moment, there doesn't seems to be any way to know that QEMU
made modification to the command buffer. This is potentially an issue
on Xen while migrating a guest, as modification to the buffer after
the migration as started c
On 4/11/22 04:23, Thomas Huth wrote:
On 11/04/2022 08.57, Bin Meng wrote:
On Mon, Apr 11, 2022 at 2:45 PM Thomas Huth wrote:
On 08/04/2022 21.19, Daniel Henrique Barboza wrote:
On 4/6/22 07:08, Bin Meng wrote:
On Tue, Apr 5, 2022 at 10:36 PM Guo Zhi wrote:
There are still some files
On Sat, 9 Apr 2022 at 01:14, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Peter Maydell
thanks
-- PMM
On Sat, 9 Apr 2022 at 01:11, Richard Henderson
wrote:
>
> Virtual SError exceptions are raised by setting HCR_EL2.VSE,
> and are routed to EL1 just like other virtual exceptions.
>
> Signed-off-by: Richard Henderson
> @@ -10041,6 +10048,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState
>
On Sat, 9 Apr 2022 at 01:23, Richard Henderson
wrote:
>
> This feature is AArch64 only, and applies to physical SErrors,
> which QEMU does not implement, thus the feature is a nop.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --
On Sun, 10 Apr 2022 at 06:58, Richard Henderson
wrote:
>
> This extension concerns branch speculation, which TCG does
> not implement. Thus we can trivially enable this feature.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
Reviewed-by:
On Sun, 10 Apr 2022 at 06:58, Richard Henderson
wrote:
>
> Update isar fields per ARM DDI0487 H.a.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h | 23 +++
> 1 file changed, 23 insertions(+)
> @@ -2067,7 +2087,9 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
> FIELD(
Sure, I will send a v2 patch.
Thanks,
Guo
- Original Message -
From: "Daniel Henrique Barboza"
To: "Thomas Huth" , "Bin Meng"
Cc: "Guo Zhi" , "Cédric Le Goater" ,
"David Gibson" , "Greg Kurz" ,
"qemu-ppc" , "qemu-devel@nongnu.org Developers"
, "Peter Maydell" , "open
list:RISC-V"
On 4/11/22 17:18, Peter Maydell wrote:
Looking a bit more closely, this won't work on big-endian
hosts, because there we want to copy across the last 16
bytes of the struct, not the first 16. So I think we need
some more macro magic:
#if SHIFT == 0
#define COPY_REG(DEST, SRC) (DEST) = (SRC)
#els
On Sun, 10 Apr 2022 at 07:07, Richard Henderson
wrote:
>
> This extension concerns cache speculation, which TCG does
> not implement. Thus we can trivially enable this feature.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu64.c | 1 +
> target/arm/cpu_tcg.c | 1 +
> 2 files chang
Currently, the PWRON STRAP values in NPCM7XX boards are magic
numbers. Similar to the aspeed ones in hw/arm/aspeed.c, we
define bit fields constants for them and use these fields instead
of the magic numbers in the current implementation. The code
should behave exactly the same as the existing one.
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