On Tue, Mar 8, 2022 at 8:28 AM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 03:14:35PM +0800, Jason Wang wrote:
> > On Tue, Mar 8, 2022 at 3:11 PM Michael S. Tsirkin wrote:
> > >
> > > On Tue, Mar 08, 2022 at 02:03:32PM +0800, Jason Wang wrote:
> > > >
> > > > 在 2022/3/7 下午11:33, Eugenio
On Tue, Mar 08, 2022 at 03:34:17PM +0800, Jason Wang wrote:
> On Tue, Mar 8, 2022 at 3:28 PM Michael S. Tsirkin wrote:
> >
> > On Tue, Mar 08, 2022 at 03:14:35PM +0800, Jason Wang wrote:
> > > On Tue, Mar 8, 2022 at 3:11 PM Michael S. Tsirkin wrote:
> > > >
> > > > On Tue, Mar 08, 2022 at 02:03:3
On 3/4/22 19:09, Patrick Williams wrote:
The w25q01jvq is a 128MB part. Support is being added to the kernel[1]
and the two have been tested together.
1. https://lore.kernel.org/lkml/2022022209.23108-1-potin@quantatw.com/
Signed-off-by: Patrick Williams
Cc: Potin Lai
---
hw/block/m
On Tue, Mar 08, 2022 at 08:32:07AM +0100, Eugenio Perez Martin wrote:
> On Tue, Mar 8, 2022 at 8:11 AM Michael S. Tsirkin wrote:
> >
> > On Mon, Mar 07, 2022 at 04:33:34PM +0100, Eugenio Pérez wrote:
> > > Finally offering the possibility to enable SVQ from the command line.
> > >
> > > Signed-off
There are two flash devices on the FMC. I can fix it inline since
it is the only change I would request.
Yes, there are. I think all of the Facebook systems have dual FMC, for
redundancy in hardware, but we can get by in QEMU with just a single one.
yes, the kernel will complain though and
On 07/03/2022 19.16, Paolo Bonzini wrote:
The following changes since commit 99c53410bc9d50e556f565b0960673cccb566452:
Merge remote-tracking branch
'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging (2022-03-01
13:25:54 +)
are available in the Git repository at:
https
tags/qemu-openbios-20220308
for you to fetch changes up to ab71472dfb05eaa11d3e216c24d499b6e64499f9:
roms/openbios: update OpenBIOS images to 0e0afae6 built from submodule
(2022-03-07 23:12:01 +)
qemu-openbios queue
- Fixes for mi
On Tue, Mar 08, 2022 at 09:15:37AM +0100, Eugenio Perez Martin wrote:
> On Tue, Mar 8, 2022 at 8:55 AM Michael S. Tsirkin wrote:
> >
> > On Tue, Mar 08, 2022 at 03:34:17PM +0800, Jason Wang wrote:
> > > On Tue, Mar 8, 2022 at 3:28 PM Michael S. Tsirkin wrote:
> > > >
> > > > On Tue, Mar 08, 2022
On Tue, Mar 8, 2022 at 8:55 AM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 03:34:17PM +0800, Jason Wang wrote:
> > On Tue, Mar 8, 2022 at 3:28 PM Michael S. Tsirkin wrote:
> > >
> > > On Tue, Mar 08, 2022 at 03:14:35PM +0800, Jason Wang wrote:
> > > > On Tue, Mar 8, 2022 at 3:11 PM Mich
On Tue, Mar 8, 2022 at 3:55 PM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 03:34:17PM +0800, Jason Wang wrote:
> > On Tue, Mar 8, 2022 at 3:28 PM Michael S. Tsirkin wrote:
> > >
> > > On Tue, Mar 08, 2022 at 03:14:35PM +0800, Jason Wang wrote:
> > > > On Tue, Mar 8, 2022 at 3:11 PM Mich
On Tue, Mar 8, 2022 at 9:02 AM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 08:32:07AM +0100, Eugenio Perez Martin wrote:
> > On Tue, Mar 8, 2022 at 8:11 AM Michael S. Tsirkin wrote:
> > >
> > > On Mon, Mar 07, 2022 at 04:33:34PM +0100, Eugenio Pérez wrote:
> > > > Finally offering the p
On 08/03/2022 07:20, Richard Henderson wrote:
From: Amir Gonnen
Implement nios2 Vectored Interrupt Controller (VIC).
VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
fields on Nios2CPU before raising an IRQ.
For that purpose, VIC has a "cpu" property which should refer to the
On 08/03/2022 07:20, Richard Henderson wrote:
We want to move data from the heap into Nios2MachineState,
which is not possible with DEFINE_MACHINE.
Signed-off-by: Richard Henderson
---
hw/nios2/10m50_devboard.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions
On 08/03/2022 07:20, Richard Henderson wrote:
Convert to contiguous allocation, as much as possible so far.
The two timer objects are not exposed for subobject allocation.
Signed-off-by: Richard Henderson
---
hw/nios2/10m50_devboard.c | 29 +++--
1 file changed, 15 i
On Tue, Mar 08, 2022 at 03:19:55AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
-Original Message-
From: Stefano Garzarella [mailto:sgarz...@redhat.com]
Sent: Monday, March 7, 2022 8:14 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
Cc
On 08/03/2022 07:20, Richard Henderson wrote:
From: Amir Gonnen
Demonstrate how to use nios2 VIC on a machine.
Introduce a new machine property to attach a VIC.
When VIC is present, let the CPU know that it should use the
External Interrupt Interface instead of the Internal Interrupt Interfac
On Mon, Mar 07, 2022 at 05:18:12PM +, Pedro Alves wrote:
> On 2022-03-07 16:58, Tom Tromey wrote:
> >> "Stefan" == Stefan Hajnoczi writes:
> >
> > Stefan> I hoped that "select-frame address ADDRESS" could be used instead so
> > Stefan> this would work on coredumps too. Unfortunately "sele
On Mon, 7 Mar 2022 at 22:52, Michael S. Tsirkin wrote:
>
> On Mon, Mar 07, 2022 at 05:13:16PM +, Peter Maydell wrote:
> > Also fails on cross-win64-system:
> >
> > https://gitlab.com/qemu-project/qemu/-/jobs/2172339938
> >
> > ../hw/virtio/virtio.c: In function 'qmp_x_query_virtio_vhost_queue_
On Sun, 6 Mar 2022 at 23:27, Philippe Mathieu-Daudé
wrote:
>
> From: Philippe Mathieu-Daudé
>
> The following changes since commit 9d662a6b22a0838a85c5432385f35db2488a33a5:
>
> Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220305' into
> staging (2022-03-05 18:03:15 +)
>
>
On Mon, 7 Mar 2022 at 22:00, Daniel Henrique Barboza
wrote:
>
>
>
> On 3/7/22 17:21, Peter Maydell wrote:
> > On Mon, 7 Mar 2022 at 19:19, Daniel Henrique Barboza
> > wrote:
> >>
> >> Hi,
> >>
> >> I got a lot of noise trying to debug an AIX guest in a pseries machine
> >> when running with
> >>
Eugenio Pérez writes:
> Finally offering the possibility to enable SVQ from the command line.
>
> Signed-off-by: Eugenio Pérez
> ---
> qapi/net.json| 8 +++-
> net/vhost-vdpa.c | 48
> 2 files changed, 47 insertions(+), 9 deletions(-)
>
> -Original Message-
> From: Stefano Garzarella [mailto:sgarz...@redhat.com]
> Sent: Tuesday, March 8, 2022 4:41 PM
> To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
>
> Cc: stefa...@redhat.com; m...@redhat.com; coh...@redhat.com;
> pbonz...@redhat.com; Gonglei (Arei) ;
On Mon, Mar 07, 2022 at 10:49:47AM +, Pedro Alves wrote:
> On 2022-03-03 11:22, Stefan Hajnoczi wrote:
> > Hi,
> > The QEMU emulator uses coroutines with separate stacks. It can be
> > challenging to debug coroutines that have yielded because GDB is not
> > aware of them (no thread is currently
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Whether the cpu is in user-mode or not is something that we
> know at translation-time. We do not need to generate code
> after having raised an exception.
>
> Suggested-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> targe
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> From: Amir Gonnen
>
> Split NUM_CORE_REGS into components that can be used elsewhere.
>
> Signed-off-by: Amir Gonnen
> Message-Id: <20220303153906.2024748-3-amir.gon...@neuroblade.ai>
> [rth: Split out of a larger patch for shadow registe
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> From: Amir Gonnen
>
> The implementation of eret will become much more complex
> with the introduction of shadow registers.
>
> Signed-off-by: Amir Gonnen
> Message-Id: <20220303153906.2024748-3-amir.gon...@neuroblade.ai>
> [rth: Split ou
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> It is cleaner to have a separate name for this variable.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 10 +++-
> linux-user/elfload.c| 2 +-
> linux-user/nios2/cpu_loop.c | 17 ++---
> li
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> We don't need to reference them often, and when we do it
> is just as easy to load/store from cpu_env directly.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/translate.c | 21 -
> 1 file changed, 16 inserti
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> This function is unused. The real computation of this value
> is located in nios2_cpu_exec_interrupt.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/target/nio
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> The only thing this struct is used for is passing startup values
> from elfload.c to the cpu. We do not need all registers to be
> represented, we do not need the kernel internal stack slots.
>
> The userland argc, argv, and envp values ar
On Mon, Mar 07, 2022 at 10:14:38PM +0100, Eric Auger wrote:
> When run on ARM, basic and indirect tests currently fail with the
> following error:
>
> ERROR:../tests/qtest/libqos/virtio.c:224:qvirtio_wait_used_elem:
> assertion failed (got_desc_idx == desc_idx): (50331648 == 0)
> Bail out! ERROR:.
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Place the control registers into their own array, env->ctrl[].
>
> Use an anonymous union and struct to give the entries in the
> array distinct names, so that one may write env->foo instead
> of env->ctrl[CR_FOO].
>
> Signed-off-by: Richar
On Mon, Mar 07, 2022 at 02:42:49PM +, Jag Raman wrote:
>
>
> > On Mar 7, 2022, at 4:45 AM, Stefan Hajnoczi wrote:
> >
> > On Thu, Mar 03, 2022 at 02:49:53PM +, Jag Raman wrote:
> >>
> >>
> >>> On Mar 2, 2022, at 11:49 AM, Stefan Hajnoczi wrote:
> >>>
> >>> On Mon, Feb 28, 2022 at 07
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Do not print control registers for user-only mode.
> Rename reserved control registers to "resN", where
> N is the control register index.
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Add all fields; retain the helper macros for single bit fields.
> So far there are no uses of the multi-bit status fields.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 27 ++-
> 1 file changed,
Hi Stefan,
On 3/8/22 11:02 AM, Stefan Hajnoczi wrote:
> On Mon, Mar 07, 2022 at 10:14:38PM +0100, Eric Auger wrote:
>> When run on ARM, basic and indirect tests currently fail with the
>> following error:
>>
>> ERROR:../tests/qtest/libqos/virtio.c:224:qvirtio_wait_used_elem:
>> assertion failed (g
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Sink the set of env->exception to the end of nios2_cpu_do_interrupt.
This splits the two things the patch is doing between the subject line
and the commit message body; the subject is supposed to be a summary
and the body should be able to
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Mon, Mar 07, 2022 at 03:10:41PM +, Jag Raman wrote:
> > On Mar 7, 2022, at 5:24 AM, Stefan Hajnoczi wrote:
> > On Thu, Feb 17, 2022 at 02:49:02AM -0500, Jagannathan Raman wrote:
> >> @@ -332,6 +336,13 @@ void msi_notify(PCIDevice *dev, unsigned int vector)
> >> msi_send_message(dev, msg
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
Empty body.
You might also mention:
"Since we're rewriting the references to CR_TLBACC_IGN_* anyway,
we correct the name of this field to IG, which is its name in the
official CPU documentation."
> Signed-off-by: Richard Henderson
> ---
On Mon, Mar 07, 2022 at 03:37:51PM +, Jag Raman wrote:
>
>
> > On Mar 7, 2022, at 6:36 AM, Stefan Hajnoczi wrote:
> >
> > On Thu, Feb 17, 2022 at 02:49:05AM -0500, Jagannathan Raman wrote:
> >> Adds handler to reset a remote device
> >>
> >> Signed-off-by: Elena Ufimtseva
> >> Signed-off-
On Mon, Mar 07, 2022 at 12:09:59PM +, Alex Bennée wrote:
>
> Stefan Hajnoczi writes:
>
> > [[PGP Signed Part:Undecided]]
> > On Fri, Mar 04, 2022 at 04:49:30PM +, Alex Bennée wrote:
> >>
> >> Stefan Hajnoczi writes:
> >>
> >> > [[PGP Signed Part:Undecided]]
> >> > On Mon, Feb 28, 2022
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 28 ++--
> target/nios2/helper.c| 7 ++-
> target/nios2/mmu.c | 33 +++--
> target/nios2/translate.c |
On Tue, Mar 08, 2022 at 04:20:53PM +0800, Jason Wang wrote:
> Generally, yes.
So generally I support the idea of merging code gradually. And merging
with an unstable flag to enable it is a reasonable way to do it.
However we are half a day away from soft freeze, so this will just
result in the f
On Tue, Mar 08, 2022 at 04:20:53PM +0800, Jason Wang wrote:
> > Not by itself but I'm not sure we can guarantee guest will not
> > attempt to use the IOVA addresses we are reserving down
> > the road.
>
> The IOVA is allocated via the listeners and stored in the iova tree
> per GPA range as IOVA->
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> These symbols become available to the debugger.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Peter Maydell
thanks
-- PMM
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Copy the existing cpu_index into the space reserved for CR_CPUID.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
> index
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Without EIC, this bit is RES1. So set the bit at reset,
> and add it to the readonly fields of CR_STATUS.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 1 +
> target/nios2/cpu.c | 5 +++--
> 2 files changed, 4 inserti
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> This interrupt bit is never set, so testing it in
> nios2_cpu_has_work is pointless.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 2 --
> target/nios2/cpu.c | 2 +-
> 2 files changed, 1 insertion(+), 3 deletions(-)
R
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Create an array of masks which detail the writable and readonly
> bits for each control register. Apply them when writing to
> control registers.
>
> Signed-off-by: Richard Henderson
What's the justification for this extra machinery? Doe
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Replace current uses of tcg_const_tl, and remove the frees.
>
> Signed-off-by: Richard Henderson
> ---
> @@ -675,8 +663,8 @@ static void divu(DisasContext *dc, uint32_t code,
> uint32_t flags)
>
> TCGv t0 = tcg_temp_new();
> TC
On Tue, Mar 08, 2022 at 09:05:27AM +, Peter Maydell wrote:
> On Mon, 7 Mar 2022 at 22:52, Michael S. Tsirkin wrote:
> >
> > On Mon, Mar 07, 2022 at 05:13:16PM +, Peter Maydell wrote:
> > > Also fails on cross-win64-system:
> > >
> > > https://gitlab.com/qemu-project/qemu/-/jobs/2172339938
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Constrain all references to cpu_R[] to load_gpr and dest_gpr.
> This will be required for supporting shadow register sets.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/translate.c | 144 +++
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> There's nothing about EH that affects translation,
> so there's no need to include it in tb->flags.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/t
On Tue, Mar 08, 2022 at 11:09:13AM +0100, Eric Auger wrote:
> Hi Stefan,
>
> On 3/8/22 11:02 AM, Stefan Hajnoczi wrote:
> > On Mon, Mar 07, 2022 at 10:14:38PM +0100, Eric Auger wrote:
> >> When run on ARM, basic and indirect tests currently fail with the
> >> following error:
> >>
> >> ERROR:../te
On Tue, Feb 08, 2022 at 09:35:09AM -0500, Emanuele Giuseppe Esposito wrote:
> We are always using the given bs AioContext, so there is no need
> to take the job ones (which is identical anyways).
> This also reduces the point we need to check when protecting
> job.aio_context field.
>
> Signed-off
On Tue, 8 Mar 2022 at 11:01, Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 09:05:27AM +, Peter Maydell wrote:
> > On Mon, 7 Mar 2022 at 22:52, Michael S. Tsirkin wrote:
> > >
> > > On Mon, Mar 07, 2022 at 05:13:16PM +, Peter Maydell wrote:
> > > > Also fails on cross-win64-system:
Dominik Czarnota writes:
> Hey,
>
> I may work on this next week but I will probably not make it until the 8th :(.
>
> On Thu, 3 Mar 2022 at 13:34, Alex Bennée wrote:
>>
>>
>> Disconnect3d writes:
>>
>> > This commit adds support for `info proc mappings` and a few other commands
>> > into
>>
On Tue, Feb 08, 2022 at 09:35:10AM -0500, Emanuele Giuseppe Esposito wrote:
> From: Paolo Bonzini
>
> We want to make sure access of job->aio_context is always done
> under either BQL or job_mutex. The problem is that using
> aio_co_enter(job->aiocontext, job->co) in job_start and job_enter_cond
On Tue, Mar 08, 2022 at 11:18:38AM +, Peter Maydell wrote:
> On Tue, 8 Mar 2022 at 11:01, Michael S. Tsirkin wrote:
> >
> > On Tue, Mar 08, 2022 at 09:05:27AM +, Peter Maydell wrote:
> > > On Mon, 7 Mar 2022 at 22:52, Michael S. Tsirkin wrote:
> > > >
> > > > On Mon, Mar 07, 2022 at 05:13
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> Decode 'break 1' during translation, rather than doing
> it again during exception processing.
>
> Signed-off-by: Richard Henderson
> ---
> target/nios2/cpu.h | 1 +
> target/nios2/helper.c| 15 ++-
> target/nios2/t
On Tue, 8 Mar 2022 at 07:20, Richard Henderson
wrote:
>
> From: Amir Gonnen
>
> Implement nios2 Vectored Interrupt Controller (VIC).
> VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
> fields on Nios2CPU before raising an IRQ.
> For that purpose, VIC has a "cpu" property which
On 3/8/22 09:14, Thomas Huth wrote:
You now need to revert commit db4b2133b8d ('Quote "case not run" lines
in TAP mode'), too, which has just been merged yesterday.
But instead of reverting, couldn't we simply go ahead with my series
here instead to restore the output of failed iotests:
ht
From: Ivan Shcherbakov
Make sure that pausing the VM while in 64-bit mode will set the
HF_CS64_MASK flag in env->hflags (see x86_update_hflags() in
target/i386/cpu.c).
Without it, the code in gdbstub.c would only use the 32-bit register values
when debugging 64-bit targets, making debugging effe
Hi
On Mon, Mar 7, 2022 at 9:41 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 3/1/22 04:46, marcandre.lur...@redhat.com wrote:
> > Replace the global variables with inlined helper functions.
> getpagesize() is very
> > likely annotated with a "const" function attribute (at least
The following changes since commit 99c53410bc9d50e556f565b0960673cccb566452:
Merge remote-tracking branch
'remotes/thuth-gitlab/tags/pull-request-2022-02-28' into staging (2022-03-01
13:25:54 +)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstre
From: Marc-André Lureau
The headers are now all available in MinGW master branch.
(commit 13390dbbf885f and earlier) aiming for 10.0.
Signed-off-by: Marc-André Lureau
Message-Id: <20220222194008.610377-4-marcandre.lur...@redhat.com>
Signed-off-by: Paolo Bonzini
---
qga/meson.build | 2 +-
1 f
From: Marc-André Lureau
The VssCoordinator & VssAdmin interfaces have been moved to vsadmin.h in
the Windows SDK.
Signed-off-by: Marc-André Lureau
Message-Id: <20220222194008.610377-3-marcandre.lur...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build| 3 +++
qga/vss-win
From: Jing Liu
Add AMX primary feature bits XFD and AMX_TILE to
enumerate the CPU's AMX capability. Meanwhile, add
AMX TILE and TMUL CPUID leaf and subleaves which
exist when AMX TILE is present to provide the maximum
capability of TILE and TMUL.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhon
From: Ivan Shcherbakov
This fixes the following error triggered when stopping and resuming a 64-bit
Linux kernel via gdb:
qemu-system-x86_64.exe: WHPX: Failed to set virtual processor context,
hr=c0350005
The previous logic for synchronizing the values did not take into account
that the lower
Signed-off-by: Paolo Bonzini
---
scripts/meson-buildoptions.sh | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh
index 9ee684ef03..1e26f4571e 100644
--- a/scripts/meson-buildoptions.sh
+++ b/scripts/meson-buildoptions
From: "Longpeng(Mike)"
Paolo suggested adding the new API to support route changes [1]. We should
invoke
kvm_irqchip_begin_route_changes() before changing the routes, increasing the
KVMRouteChange.changes if the routes are changed, and commit the changes at
last.
[1] https://lists.gnu.org/arch
From: Vitaly Kuznetsov
5-level EPT is present in Icelake Server CPUs and is supported by QEMU
('vmx-page-walk-5').
Signed-off-by: Vitaly Kuznetsov
Message-Id: <20220221145316.576138-2-vkuzn...@redhat.com>
Signed-off-by: Paolo Bonzini
---
scripts/kvm/vmxcap | 1 +
1 file changed, 1 insertion(+
From: Jing Liu
When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave
area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE
under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB.
Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it.
Signed-off-by: Ji
From: "Longpeng(Mike)"
We invoke the kvm_irqchip_commit_routes() for each addition to MSI route
table, which is not efficient if we are adding lots of routes in some cases.
This patch lets callers invoke the kvm_irqchip_commit_routes(), so the
callers can decide how to optimize.
[1] https://lis
From: Marc-André Lureau
This is a left-over, despite requesting the change before the merge.
Fixes: commit 8821a389 ("configure, meson: replace VSS SDK checks and options
with --enable-vss-sdk")
Signed-off-by: Marc-André Lureau
Message-Id: <20220222194008.610377-2-marcandre.lur...@redhat.com>
LA57/PKE/PKS is only relevant in 64-bit mode, and NXE is only relevant if
PAE is in use. Since there is code that checks PG_MODE_LA57 to determine
the canonicality of addresses, make sure that the bit is not set by
mistake in 32-bit mode. While it would not be a problem because 32-bit
addresses b
From: Maxim Levitsky
Even when the feature is not supported in guest CPUID,
still set the msr to the default value which will
be the only value KVM will accept in this case
Signed-off-by: Maxim Levitsky
Message-Id: <20220223115824.319821-1-mlevi...@redhat.com>
Signed-off-by: Paolo Bonzini
---
From: Zeng Guang
XFD(eXtended Feature Disable) allows to enable a
feature on xsave state while preventing specific
user threads from using the feature.
Support save and restore XFD MSRs if CPUID.D.1.EAX[4]
enumerate to be valid. Likewise migrate the MSRs and
related xsave state necessarily.
Sig
Signed-off-by: Paolo Bonzini
---
linux-headers/asm-x86/kvm.h | 3 +++
linux-headers/linux/kvm.h | 4
2 files changed, 7 insertions(+)
diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h
index 2da3316bb5..bf6e96011d 100644
--- a/linux-headers/asm-x86/kvm.h
+++ b/linux-he
From: Jing Liu
The AMX TILECFG register and the TMMx tile data registers are
saved/restored via XSAVE, respectively in state component 17
(64 bytes) and state component 18 (8192 bytes).
Add AMX feature bits to x86_ext_save_areas array to set
up AMX components. Add structs that define the layout
From: Gareth Webb
Loading a non-canonical address into rsp when handling an interrupt or
performing a far call should raise a #SS not a #GP.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/870
Signed-off-by: Gareth Webb
Message-Id: <164529651121.25406.1533713706858424639...@git.sr.ht>
[
From: Jing Liu
The extended state subleaves (EAX=0Dh, ECX=n, n>1).ECX[1]
indicate whether the extended state component locates
on the next 64-byte boundary following the preceding state
component when the compacted format of an XSAVE area is
used.
Right now, they are all zero because no supporte
From: Jing Liu
Intel introduces XFD faulting mechanism for extended
XSAVE features to dynamically enable the features in
runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
as 1, it indicates support for XFD faulting of this
state component.
Signed-off-by: Jing Liu
Signed-off-by: Yang Zhong
This is flaky and sometimes fails or hangs unexplicably.
Signed-off-by: Paolo Bonzini
---
.gitlab-ci.d/buildtest.yml | 2 --
1 file changed, 2 deletions(-)
diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index 0aa70213fb..0aea7ab84c 100644
--- a/.gitlab-ci.d/buildtest.yml
+
From: Vitaly Kuznetsov
Windows 11 with WSL2 enabled (Hyper-V) fails to boot with Icelake-Server
{-v5} CPU model but boots well with '-cpu host'. Apparently, it expects
5-level paging and 5-level EPT support to come in pair but QEMU's
Icelake-Server CPU model lacks the later. Introduce 'Icelake-Se
On Tue, 8 Mar 2022 at 03:18, Richard Henderson
wrote:
>
> For both ldnt1 and stnt1, the meaning of the Rn and Rm are different
> from ld1 and st1: the vector and integer registers are reversed, and
> the integer register 31 refers to XZR instead of SP.
>
> Secondly, the 64-bit version of ldnt1 was
From: Yang Zhong
Kernel allocates 4K xstate buffer by default. For XSAVE features
which require large state component (e.g. AMX), Linux kernel
dynamically expands the xstate buffer only after the process has
acquired the necessary permissions. Those are called dynamically-
enabled XSAVE features
On Tue, Mar 08, 2022 at 09:42:25AM +, Longpeng (Mike, Cloud Infrastructure
Service Product Dept.) wrote:
-Original Message-
From: Stefano Garzarella [mailto:sgarz...@redhat.com]
Sent: Tuesday, March 8, 2022 4:41 PM
To: Longpeng (Mike, Cloud Infrastructure Service Product Dept.)
C
On Tue, Mar 8, 2022 at 11:48 AM Michael S. Tsirkin wrote:
>
> On Tue, Mar 08, 2022 at 04:20:53PM +0800, Jason Wang wrote:
> > > Not by itself but I'm not sure we can guarantee guest will not
> > > attempt to use the IOVA addresses we are reserving down
> > > the road.
> >
> > The IOVA is allocated
On 3/7/22 14:26, Chao Peng wrote:
In pseudo-Rust, this is the difference between:
fn convert_to_private(in: &mut Memfd)
and
fn convert_to_private(in: Memfd) -> PrivateMemoryFd
This doesn't map particularly nicely to the kernel, though.
I understand this Rust semantics and the difficulty to h
On Tue, Mar 08, 2022 at 12:37:33PM +0100, Eugenio Perez Martin wrote:
> On Tue, Mar 8, 2022 at 11:48 AM Michael S. Tsirkin wrote:
> >
> > On Tue, Mar 08, 2022 at 04:20:53PM +0800, Jason Wang wrote:
> > > > Not by itself but I'm not sure we can guarantee guest will not
> > > > attempt to use the IO
ull-aspeed-20220308
for you to fetch changes up to 46179776c292f83848df90de60da5ae1a965ce6a:
hw: aspeed_gpio: Cleanup stray semicolon after switch (2022-03-08 09:18:11
+0100)
aspeed queue:
* Fix for a potential memory leak
*
The Aspeed SMC model uses the 'num_cs' field to allocate resources
fitting the number of devices of the machine. This is a small
optimization without real need in the controller. Simplify modelling
and use the max_peripherals field instead.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistai
From: Patrick Williams
Add the 'bletchley-bmc' machine type based on the kernel DTS[1] and
hardware schematics available to me. The i2c model is as complete as
the current QEMU models support, but in some cases I substituted devices
that are close enough for present functionality. Strap registe
It is not used anymore.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-Id: <20220307071856.1410731-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 1 -
hw/arm/aspeed.c | 2 --
hw/arm/aspeed_ast2600.c | 2 --
hw/arm/as
From: Andrew Jeffery
Not sure how that got there.
Signed-off-by: Andrew Jeffery
Message-Id: <20220207150409.35-2-and...@aj.id.au>
Signed-off-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/a
From: Patrick Williams
Generally all BMCs will use the fmc_model to hold their own flash
and most will have a spi_model to hold the managed system's flash,
but not all systems do. Add a simple NULL check to allow a system
to set the spi_model as NULL to indicate it should not be instantiated.
S
The naming makes more sense in a SPI controller model.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Message-Id: <20220307071856.1410731-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/aspeed_smc.h | 2 +-
hw/ssi/aspeed_smc.c | 42 +++
Currently, the allocation of the flash devices uses the number of
slave selects configured in the SoC realize routine. It is simpler to
use directly the number of FMC devices defined in the machine class
and 1 for spi devices (which is what the SoC does in the back of the
machine).
Reviewed-by: Ph
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