On Tue, 8 Mar 2022 at 07:20, Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
> ---
> target/nios2/cpu.h | 28 ++++++++++++++++++----------
> target/nios2/helper.c | 7 ++-----
> target/nios2/mmu.c | 33 +++++++++++++++------------------
> target/nios2/translate.c | 2 +-
> 4 files changed, 36 insertions(+), 34 deletions(-)
>
> diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
> index 024ef3ccc0..3857848f7c 100644
> --- a/target/nios2/cpu.h
> +++ b/target/nios2/cpu.h
> @@ -131,16 +131,24 @@ FIELD(CR_TLBACC, IG, 25, 7)
> #define CR_TLBACC_G (1u << R_CR_TLBACC_G_SHIFT)
>
> #define CR_TLBMISC 10
> -#define CR_TLBMISC_WAY_SHIFT 20
> -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
> -#define CR_TLBMISC_RD (1 << 19)
> -#define CR_TLBMISC_WR (1 << 18)
> -#define CR_TLBMISC_PID_SHIFT 4
> -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
> -#define CR_TLBMISC_DBL (1 << 3)
> -#define CR_TLBMISC_BAD (1 << 2)
> -#define CR_TLBMISC_PERM (1 << 1)
> -#define CR_TLBMISC_D (1 << 0)
> +
> +FIELD(CR_TLBMISC, D, 0, 1)
> +FIELD(CR_TLBMISC, PERM, 1, 1)
> +FIELD(CR_TLBMISC, BAD, 2, 1)
> +FIELD(CR_TLBMISC, DBL, 3, 1)
> +FIELD(CR_TLBMISC, PID, 4, 14)
> +FIELD(CR_TLBMISC, WR, 18, 1)
> +FIELD(CR_TLBMISC, RD, 19, 1)
> +FIELD(CR_TLBMISC, WAY, 20, 4)
> +FIELD(CR_TLBMISC, EE, 24, 1)
> +
> +#define CR_TLBMISC_RD (1u << R_CR_TLBMISC_RD_SHIFT)
> +#define CR_TLBMISC_WR (1u << R_CR_TLBMISC_WR_SHIFT)
> +#define CR_TLBMISC_DBL (1u << R_CR_TLBMISC_DBL_SHIFT)
> +#define CR_TLBMISC_BAD (1u << R_CR_TLBMISC_BAD_SHIFT)
> +#define CR_TLBMISC_PERM (1u << R_CR_TLBMISC_PERM_SHIFT)
> +#define CR_TLBMISC_D (1u << R_CR_TLBMISC_D_SHIFT)
Same comment as previous patches.
> +
> #define CR_ENCINJ 11
> #define CR_BADADDR 12
> #define CR_CONFIG 13
> diff --git a/target/nios2/helper.c b/target/nios2/helper.c
> index 37fb53dadb..93338e86f0 100644
> --- a/target/nios2/helper.c
> +++ b/target/nios2/helper.c
> @@ -276,11 +276,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int
> size,
> return false;
> }
>
> - if (access_type == MMU_INST_FETCH) {
> - env->tlbmisc &= ~CR_TLBMISC_D;
> - } else {
> - env->tlbmisc |= CR_TLBMISC_D;
> - }
> + env->tlbmisc = FIELD_DP32(env->tlbmisc, CR_TLBMISC, D,
> + access_type == MMU_INST_FETCH);
This inverts the sense -- now we set the D bit for MMU_INST_FETCH,
which is wrong.
> env->pteaddr = FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN,
> address >> TARGET_PAGE_BITS);
> env->mmu.pteaddr_wr = env->pteaddr;
> @@ -130,24 +128,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env,
> uint32_t v)
> void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
> {
> Nios2CPU *cpu = env_archcpu(env);
> + uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID);
> + uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
> + uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY);
>
> - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
> + trace_nios2_mmu_write_tlbmisc(way,
> (v & CR_TLBMISC_RD) ? 'R' : '.',
> (v & CR_TLBMISC_WR) ? 'W' : '.',
> (v & CR_TLBMISC_DBL) ? '2' : '.',
> (v & CR_TLBMISC_BAD) ? 'B' : '.',
> (v & CR_TLBMISC_PERM) ? 'P' : '.',
> (v & CR_TLBMISC_D) ? 'D' : '.',
> - (v & CR_TLBMISC_PID_MASK) >> 4);
> + new_pid);
>
> - if ((v & CR_TLBMISC_PID_MASK) !=
> - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
> - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
> - CR_TLBMISC_PID_SHIFT);
> + if (new_pid != old_pid) {
> + mmu_flush_pid(env, old_pid);
> }
> +
> /* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
> if (v & CR_TLBMISC_RD) {
> - int way = (v >> CR_TLBMISC_WAY_SHIFT);
> int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
> Nios2TLBEntry *entry =
> &env->mmu.tlb[(way * cpu->tlb_num_ways) +
Any reason for hoisting the declaration of 'way' up to the top of the
function ?
-- PMM
