Hi Peter,
> Is a VIC a configurable option on the real hardware (well, FPGA image, I
> guess) that this board is modelling ?
> I couldn't find any docs on it with a quick google.
This specific example-board from Intel does not provide a VIC option, as far as
I know.
(https://fpgacloud.intel.c
On Fri, Feb 25, 2022 at 04:50:54PM +0100, Igor Mammedov wrote:
> On Fri, 25 Feb 2022 08:50:43 -0500
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Feb 25, 2022 at 02:18:23PM +0100, Igor Mammedov wrote:
> > > On Fri, 25 Feb 2022 04:58:46 -0500
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Th
On Fri, Feb 25, 2022 at 08:40:00PM +, Bernhard Beschow wrote:
> Am 17. Februar 2022 22:53:50 UTC schrieb Bernhard Beschow :
> >*opaque is an alias to *obj. Using the ladder makes the code consistent with
> >with other devices, e.g. accel/kvm/kvm-all and accel/tcg/tcg-all. It also
> >makes the c
Am 26. Februar 2022 06:30:18 UTC schrieb Liav Albani :
>This can allow the guest OS to determine more easily if i8042 controller
>is present in the system or not, so it doesn't need to do probing of the
>controller, but just initialize it immediately, before enumerating the
>ACPI AML namespace.
>
>
I notice that in the patch here:
https://gitlab.com/qemu-project/qemu/-/commit/5d6542bea780ad443c4f7f1496e64706101f525
The MAX_OPC_PARAM_IARGS was not updated as this path did:
https://gitlab.com/qemu-project/qemu/-/commit/1df3caa946e08b387511dfba3a37d78910e51796
And thus this patch fixes it ac
I notice that in the patch here:
https://gitlab.com/qemu-project/qemu/-/commit/5d6542bea780ad443c4f7f1496e64706101f525
The MAX_OPC_PARAM_IARGS was not updated as this path did:
https://gitlab.com/qemu-project/qemu/-/commit/1df3caa946e08b387511dfba3a37d78910e51796
And thus this patch fixes it ac
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.
Signed-off-by: Ziqiao Kong
---
include/tcg/tcg.h| 2 +-
tcg/tci/tcg-target.c.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tc
On Sun, 27 Feb 2022 at 00:56, Richard Henderson
wrote:
>
> On 2/26/22 08:07, Peter Maydell wrote:
> > Currently if qemu_try_memalign() is asked to allocate 0 bytes, we assert.
> > Instead return NULL; this is in line with the posix_memalign() API,
> > and is valid to pass to _aligned_free() (which
This series enable shadow virtqueue (SVQ) for vhost-vdpa devices. This
is intended as a new method of tracking the memory the devices touch
during a migration process: Instead of relay on vhost device's dirty
logging capability, SVQ intercepts the VQ dataplane forwarding the
descriptors between VM
Vhost shadow virtqueue (SVQ) is an intermediate jump for virtqueue
notifications and buffers, allowing qemu to track them. While qemu is
forwarding the buffers and virtqueue changes, it is able to commit the
memory it's being dirtied, the same way regular qemu's VirtIO devices
do.
This commit only
At this mode no buffer forwarding will be performed in SVQ mode: Qemu
will just forward the guest's kicks to the device.
Host memory notifiers regions are left out for simplicity, and they will
not be addressed in this series.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h
This will make qemu aware of the device used buffers, allowing it to
write the guest memory with its contents if needed.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-shadow-virtqueue.h | 4
hw/virtio/vhost-shadow-virtqueue.c | 34 ++
hw/virtio/vhost-vdpa.c
This allows SVQ to negotiate features with the guest and the device. For
the device, SVQ is a driver. While this function bypasses all
non-transport features, it needs to disable the features that SVQ does
not support when forwarding buffers. This includes packed vq layout,
indirect descriptors or
It reports the shadow virtqueue address from qemu virtual address space.
Since this will be different from the guest's vaddr, but the device can
access it, SVQ takes special care about its alignment & lack of garbage
data. It assumes that IOMMU will work in host_page_size ranges for that.
Signed-
First half of the buffers forwarding part, preparing vhost-vdpa
callbacks to SVQ to offer it. QEMU cannot enable it at this moment, so
this is effectively dead code at the moment, but it helps to reduce
patch size.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 84
Use translations added in VhostIOVATree in SVQ.
Only introduce usage here, not allocation and deallocation. As with
previous patches, we use the dead code paths of shadow_vqs_enabled to
avoid commiting too many changes at once. These are impossible to take
at the moment.
Signed-off-by: Eugenio Pé
Initial version of shadow virtqueue that actually forward buffers. There
is no iommu support at the moment, and that will be addressed in future
patches of this series. Since all vhost-vdpa devices use forced IOMMU,
this means that SVQ is not usable at this point of the series on any
device.
For s
This is needed to achieve migration, so the destination can restore its
index.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c
index 56f9f125cd..accc4024c2 100644
--- a/
This iova tree function allows it to look for a hole in allocated
regions and return a totally new translation for a given translated
address.
It's usage is mainly to allow devices to access qemu address space,
remapping guest's one into a new iova space where qemu can add chunks of
addresses.
Si
Finally offering the possibility to enable SVQ from the command line.
Signed-off-by: Eugenio Pérez
---
qapi/net.json| 5 -
net/vhost-vdpa.c | 48
2 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/qapi/net.json b/qapi/net.jso
This tree is able to look for a translated address from an IOVA address.
At first glance it is similar to util/iova-tree. However, SVQ working on
devices with limited IOVA space need more capabilities, like allocating
IOVA chunks or performing reverse translations (qemu addresses to iova).
The al
Setting the log address would make the device start reporting invalid
dirty memory because the SVQ vrings are located in qemu's memory.
Signed-off-by: Eugenio Pérez
---
hw/virtio/vhost-vdpa.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio
SVQ is able to log the dirty bits by itself, so let's use it to not
block migration.
Also, ignore set and clear of VHOST_F_LOG_ALL on set_features if SVQ is
enabled. Even if the device supports it, the reports would be nonsense
because SVQ memory is in the qemu region.
The log region is still all
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 4
target/riscv/insn_trans/tra
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 57
target/riscv/helper.h | 7 ++
This patchset implements RISC-V scalar crypto extension v1.0.0 version
instructions.
Partial instructions are reused from B-extension.
Specification:
https://github.com/riscv/riscv-crypto
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v6
To test rvk imple
- reuse partial instructions of zbc extension, update extension check for them
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 3 ++-
target/riscv/insn_trans/trans_rvb.c.inc | 4 ++--
2 files changed, 4 insertio
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 +
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 136
target/riscv/helper.h
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
crypto/meson.build | 1 +
crypto/sm4.c | 49 ++
include/cryp
- add aes32esmi, aes32esi, aes32dsmi and aes32dsi instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 139
target/riscv/helper.h | 6 +
target/riscv/insn32.decode
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/cpu.c | 23 +++
target/riscv/cpu.h | 13 +
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b0a40b83e7..d30534ead5 10064
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 49 +
target/riscv/helper.h | 6 +++
target/riscv/insn32.decode | 6 ++
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d30534ead5..64bc776072 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/c
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
disas/riscv.c | 170 ++
1 file changed, 170 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 03c8dc9961..44a2c16a0b 100644
- reuse partial instructions of zbb extension, update extension check for them
- add brev8, pack, packh, packw, unzip, zip instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Acked-by: Alistair Francis
---
target/riscv/bitmanip_helper.c | 53 +++
target/riscv
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 ++
target/riscv/helper.h | 5 +++
target/riscv/insn32.decode
- add SEED CSR
- add USEED, SSEED fields for MSECCFG CSR
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_bits.h | 9 ++
target/riscv/csr.c | 64 +
target/riscv/
On Fri, 25 Feb 2022 at 17:45, Hao Wu wrote:
>
> From: Shengtan Mao
>
> Reviewed-by: Hao Wu
> Reviewed-by: Chris Rauer
> Signed-off-by: Shengtan Mao
> Signed-off-by: Patrick Venture
Applied to target-arm.next, thanks.
-- PMM
On Sat, 26 Feb 2022 at 10:41, Akihiko Odaki wrote:
>
> This change brings two new features:
> - The window will be resizable if "Zoom To Fit" is eanbled
> - The window can be made full screen by clicking full screen button
> provided by the platform. (The left-top green button.)
>
> Signed-off-b
On 26/2/22 13:45, Akihiko Odaki wrote:
Signed-off-by: Akihiko Odaki
---
configure | 1 +
include/net/net.h | 2 +-
meson.build | 1 +
net/tap.c | 6 +-
qemu-options.hx | 4 ++--
5 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/net/tap.c b/net/t
Hi Richard,
Thank you for your review and comments!
> You're missing a gen_check_supervisor here and in wrprs.
There's something I don't understand about gen_check_supervisor - it looks like
it checks CR_STATUS_U when generating code instead of generating code that
checks CR_STATUS_U.
Is that
On Sun, 27 Feb 2022 at 16:16, Amir Gonnen wrote:
> There's something I don't understand about gen_check_supervisor -
> it looks like it checks CR_STATUS_U when generating code instead
> of generating code that checks CR_STATUS_U.
This is OK because it is checking the value of CR_STATUS_U in
the t
This fixes the problems that I pointed out with respect to the
existing Internal Interrupt Controller, and a few cleanups on the way.
It passes check-avocado, which is the only nios2 test I know of,
so more testing would be appreciated.
r~
Richard Henderson (7):
target/nios2: Remove mmu_read_
We can thus remove an ifdef covering the entire file.
Signed-off-by: Richard Henderson
---
target/nios2/mmu.c | 3 ---
target/nios2/meson.build | 3 +--
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 306370f675..437fad09b7 100644
This functionality can be had via plugins, if desired.
In the meantime, it is unused code.
Signed-off-by: Richard Henderson
---
target/nios2/helper.h| 1 -
target/nios2/mmu.h | 1 -
target/nios2/mmu.c | 20
target/nios2/op_helper.c | 5 -
target/nios2/
Signed-off-by: Richard Henderson
---
meson.build | 1 +
target/nios2/mmu.c| 96 ---
target/nios2/trace-events | 10
3 files changed, 39 insertions(+), 68 deletions(-)
create mode 100644 target/nios2/trace-events
diff --git a/meson.
Drop irq_pending boolean.
Drop helper_check_interrupts.
Move checks for irq disabled into nios2_cpu_exec_interrupt.
End the TB on writes to ienable, just like to status.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 1 -
target/nios2/helper.h| 1 -
target/nios2/cpu.c
This will avoid having to replicate the check to additional cases.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 194c8ebafd..fa355308a9 100644
---
It was never correct to be able to write to ipending.
Until the rest of the irq code is tidied, the read of ipending
will generate an "unnecessary" mask.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/nios2/t
Create three separate functions for the three separate registers.
Avoid extra dispatch through op_helper.c.
Dispatch to the correct function in translation.
Clean up the ifdefs in wrctl.
Signed-off-by: Richard Henderson
---
target/nios2/helper.h| 4 +-
target/nios2/mmu.c | 180 ++
On 2/27/22 02:54, Peter Maydell wrote:
+if (size) {
+ptr = _aligned_malloc(size, alignment);
+} else {
+ptr = NULL;
+}
Oh, should we set errno to something here?
Otherwise a random value will be used by qemu_memalign.
Yeah, I guess so, though the errno to use isn't
On 2/27/22 04:25, Weiwei Li wrote:
+static void gen_packh(TCGv ret, TCGv src1, TCGv src2)
+{
+TCGv t = tcg_temp_new();
+
+tcg_gen_ext8u_tl(t, src2);
+tcg_gen_deposit_tl(ret, src1, t, 8, TARGET_LONG_BITS - 8);
+tcg_temp_free(t);
+}
+
+static void gen_packw(TCGv ret, TCGv src1, TCGv
On 25/2/22 22:01, Cleber Rosa wrote:
Being explicit about the accelerator used on these tests is a good
thing in itself, but it will also be used in the filtering rules
applied on "make check-avocado".
Signed-off-by: Cleber Rosa
---
tests/avocado/linux_ssh_mips_malta.py | 3 +++
1 file chang
On 25/2/22 22:01, Cleber Rosa wrote:
Since Avocado 94.0[1], the "avocado.utils.network" dropped a lot of
previously deprecated API names, having the new names into a finer
grained structure.
This simply uses the new API names for the network port utility
module.
[1] -
https://avocado-framework
On 2/27/22 04:25, Weiwei Li wrote:
- add xperm4 and xperm8 instructions
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/bitmanip_helper.c | 27 +
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode
On 25/2/22 22:01, Cleber Rosa wrote:
Since Avocado 92.0[1], there's no universal preservation of logged
content via Python's "logging" APIs into the test log files. This
changes were motivated by the fact that doing so is intrusive as it
touches on Python's root logger.
Test writers are now exp
On 2/27/22 04:25, Weiwei Li wrote:
- share it between target/arm and target/riscv
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
---
crypto/meson.build | 1 +
crypto/sm4.c | 49
On 2/27/22 12:48, Bernhard Beschow wrote:
Am 26. Februar 2022 06:30:18 UTC schrieb Liav Albani :
This can allow the guest OS to determine more easily if i8042 controller
is present in the system or not, so it doesn't need to do probing of the
controller, but just initialize it immediately, bef
On 2/27/22 08:56, Ani Sinha wrote:
On Sat, 26 Feb 2022, Liav Albani wrote:
This can allow the guest OS to determine more easily if i8042 controller
is present in the system or not, so it doesn't need to do probing of the
controller, but just initialize it immediately, before enumerating the
On 2/27/22 09:27, Ani Sinha wrote:
On Sat, 26 Feb 2022, Liav Albani wrote:
This function enumerates all attached ISA devices in the machine, and
tries to compare a given device type name to the enumerated devices.
For example, this can help other code to determine if a i8042 controller
exist
On 2/27/22 04:25, Weiwei Li wrote:
+#define AES_SHIFROWS_LO(RS1, RS2) ( \
+(((RS1 >> 24) & 0xFF) << 56) | (((RS2 >> 48) & 0xFF) << 48) | \
+(((RS2 >> 8) & 0xFF) << 40) | (((RS1 >> 32) & 0xFF) << 32) | \
+(((RS2 >> 56) & 0xFF) << 24) | (((RS2 >> 16) & 0xFF) << 16) | \
+(((RS1 >> 40
On 2/27/22 04:25, Weiwei Li wrote:
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i
instructions
Co-authored-by: Ruibo Lu
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 136
On 2/27/22 04:25, Weiwei Li wrote:
- add sha256sig0, sha256sig1, sha256sum0 and sha256sum1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 +
target/riscv/helper.h |
On 2/27/22 04:25, Weiwei Li wrote:
- add sha512sum0r, sha512sig0l, sha512sum1r, sha512sig1l, sha512sig0h and
sha512sig1h instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 57
target/
On 2/27/22 04:25, Weiwei Li wrote:
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 31 ++
target/riscv/helper.h
On 2/27/22 04:25, Weiwei Li wrote:
- add sm3p0, sm3p1, sm4ed and sm4ks instructions
Co-authored-by: Ruibo Lu
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/crypto_helper.c| 49 +
target/riscv/helper.h | 6 +++
target
On some older software like Windows 7 installer, having both a PS/2
mouse and USB mouse results in only one device working property (which
might be a different device each boot). While the workaround to not use
a USB mouse with such software is valid, it creates an inconsistent
experience if the us
Am 27. Februar 2022 18:58:18 UTC schrieb Liav Albani :
>
>On 2/27/22 12:48, Bernhard Beschow wrote:
>> Am 26. Februar 2022 06:30:18 UTC schrieb Liav Albani :
>>> This can allow the guest OS to determine more easily if i8042 controller
>>> is present in the system or not, so it doesn't need to do pr
On 27/2/22 19:21, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
meson.build | 1 +
target/nios2/mmu.c| 96 ---
target/nios2/trace-events | 10
3 files changed, 39 insertions(+), 68 deletions(-)
create mode 100
On 27/2/22 19:21, Richard Henderson wrote:
We can thus remove an ifdef covering the entire file.
Signed-off-by: Richard Henderson
---
target/nios2/mmu.c | 3 ---
target/nios2/meson.build | 3 +--
2 files changed, 1 insertion(+), 5 deletions(-)
\o/
Reviewed-by: Philippe Mathieu-Daud
On 27/2/22 19:21, Richard Henderson wrote:
This will avoid having to replicate the check to additional cases.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 27/2/22 19:21, Richard Henderson wrote:
Drop irq_pending boolean.
Drop helper_check_interrupts.
Move checks for irq disabled into nios2_cpu_exec_interrupt.
End the TB on writes to ienable, just like to status.
Signed-off-by: Richard Henderson
---
target/nios2/cpu.h | 1 -
target/ni
On 27/2/22 19:21, Richard Henderson wrote:
It was never correct to be able to write to ipending.
Until the rest of the irq code is tidied, the read of ipending
will generate an "unnecessary" mask.
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 12
1 file changed
On 22/2/22 20:34, Bernhard Beschow wrote:
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/isa/piix4.c
On 22/2/22 20:34, Bernhard Beschow wrote:
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/rtc/m48t59-isa.c | 9 +++
On 22/2/22 20:34, Bernhard Beschow wrote:
Exposing the IRQ numbers as a QOM properties not only allows them to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow
---
hw/input/pckbd.c | 26
On 22/2/22 20:34, Bernhard Beschow wrote:
Determine the IRQ number in the same way as for isa-ipmi-bt. This resolves
the last usage of ISADevice::isairq[] which allows it to be removed.
Signed-off-by: Bernhard Beschow
---
hw/ppc/pnv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
On 22/2/22 20:34, Bernhard Beschow wrote:
Now that the last users of ISADevice::isairq[] have been resolved during the
previous commits, it can be removed for good.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 13 -
include/hw/isa/isa.h | 2 --
2 files changed, 15
On 22/2/22 20:34, Bernhard Beschow wrote:
isa_init_irq() had become a trivial one-line wrapper for isa_get_irq().
The previous commits resolved all usages in favor of isa_get_irq().
isa_init_irq() can therefore be removed.
Signed-off-by: Bernhard Beschow
---
hw/isa/isa-bus.c | 5 -
i
On 27/2/22 03:04, Richard Henderson wrote:
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.
This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally si
This is a followup to
https://lists.gnu.org/archive/html/qemu-devel/2022-02/msg04391.html,
adding 9p server support for Darwin.
Since v8, the following changes have been made:
Patch 4/11 (9p: darwin: Handle struct dirent differences)
- Declare qemu_dirent_off as static to prevent linker error
-
From: Keno Fischer
- Guard Linux only headers.
- Add qemu/statfs.h header to abstract over the which
headers are needed for struct statfs
- Define `ENOATTR` only if not only defined
(it's defined in system headers on Darwin).
Signed-off-by: Keno Fischer
[Michael Roitzsch: - Rebase for
From: Keno Fischer
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
[Will Cohen: - Note lack of f_namelen and f_frsize on Darwin
- Ensure that tv_sec and tv_nsec are both
initialized for Darwin and non-Darwin]
Signed-off-by: Will Cohen
---
hw/9pfs/9p-pro
From: Keno Fischer
On darwin `fgetxattr` takes two extra optional arguments,
and the l* variants are not defined (in favor of an extra
flag to the regular variants.
Signed-off-by: Keno Fischer
[Michael Roitzsch: - Rebase for NixOS]
Signed-off-by: Michael Roitzsch
Signed-off-by: Will Cohen
---
From: Keno Fischer
On darwin d_seekoff exists, but is optional and does not seem to
be commonly used by file systems. Use `telldir` instead to obtain
the seek offset and inject it into d_seekoff, and create a
qemu_dirent_off helper to call it appropriately when appropriate.
Signed-off-by: Keno F
From: Keno Fischer
Darwin doesn't have either of these flags. Darwin does have
F_NOCACHE, which is similar to O_DIRECT, but has different
enough semantics that other projects don't generally map
them automatically. In any case, we don't support O_DIRECT
on Linux at the moment either.
Signed-off-
From: Keno Fischer
The current file only has the Linux versions of these functions.
Rename the file accordingly and update the Makefile to only build
it on Linux. A Darwin version of these will follow later in the
series.
Signed-off-by: Keno Fischer
[Michael Roitzsch: - Rebase for NixOS]
Signed
From: Keno Fischer
Signed-off-by: Keno Fischer
Signed-off-by: Michael Roitzsch
Because XATTR_SIZE_MAX is not defined on Darwin,
create a cross-platform P9_XATTR_SIZE_MAX instead.
[Will Cohen: - Adjust coding style
- Lower XATTR_SIZE_MAX to 64k
- Add explanatory conte
From: Keno Fischer
To allow VirtFS on darwin, we need to check that pthread_fchdir_np is
available, which has only been available since macOS 10.12.
Additionally, virtfs_proxy_helper is disabled on Darwin. This patch
series does not currently provide an implementation of the proxy-helper,
but th
From: Keno Fischer
This implements the darwin equivalent of the functions that were
moved to 9p-util(-linux) earlier in this series in the new
9p-util-darwin file.
Signed-off-by: Keno Fischer
[Michael Roitzsch: - Rebase for NixOS]
Signed-off-by: Michael Roitzsch
Signed-off-by: Will Cohen
---
From: Keno Fischer
Darwin does not support mknodat. However, to avoid race conditions
with later setting the permissions, we must avoid using mknod on
the full path instead. We could try to fchdir, but that would cause
problems if multiple threads try to call mknodat at the same time.
However, lu
The previous test depended on the assumption that P9_DOTL_AT_REMOVEDIR
and AT_REMOVEDIR have the same value.
While this is true on Linux, it is not true everywhere, and leads to an
incorrect test failure on unlink_at, noticed when adding 9p to darwin:
Received response 7 (RLERROR) instead of 77 (
On 22/2/22 20:34, Bernhard Beschow wrote:
All isabus_dev_print() did was to print up to two IRQ numbers per
device. This is redundant if the IRQ numbers are present as QOM
properties (see e.g. the modified tests/qemu-iotests/172.out).
Now that the last devices relying on isabus_dev_print() had t
On 22/2/22 20:34, Bernhard Beschow wrote:
v2:
The newly QOM'ified devices now report an error to the user in their realize
functions if the configured IRQ number is greater than 15.
v1:
The IRQ attributes of ISADevice are hardcoded to support up to two IRQs per
device which creates an artificial
On 27/2/22 03:04, Richard Henderson wrote:
When using reserved_va, which is the default for a 64-bit host
and a 32-bit guest, set guest_base_signed_addr32 if requested
by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
On 27/2/22 03:04, Richard Henderson wrote:
All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Cc: Philippe Mathieu-Daudé
Cc: Aurelien Jarno
Cc: Huacai Chen
Cc: Jiaxun Yang
Cc: Aleksandar Rikalo
Signed-off-by:
On 27/2/22 03:04, Richard Henderson wrote:
All 32-bit LoongArch operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Cc: WANG Xuerui
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-sa32.h | 2 +-
tcg/loongarch
On 26/2/22 02:55, Richard Henderson wrote:
The tcg_out_ldst helper will handle out-of-range offsets.
We haven't actually encountered any, since we haven't run
across the assert within tcg_out_op_rrs, but an out-of-range
offset would not be impossible in future.
Fixes: 65089889183 ("tcg/tci: Chan
On 25/2/22 09:45, Markus Armbruster wrote:
Commit 57df0dff1a "qapi: Extend -compat to set policy for unstable
interfaces" (v6.2.0) took care of covering experimental features, but
neglected to adjust a comment suggesting to cover it. Adjust it now.
Fixes: 57df0dff1a1f4c846aa74a082bfd595a8a99001
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