Re: [PATCH v6 10/14] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension

[Richard Henderson]

On 2/27/22 04:25, Weiwei Li wrote:

  - add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions

Co-authored-by: Zewen Ye <lust...@foxmail.com>
Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
---
  target/riscv/crypto_helper.c            | 31 ++++++++++++++
  target/riscv/helper.h                   |  5 +++
  target/riscv/insn32.decode              |  5 +++
  target/riscv/insn_trans/trans_rvk.c.inc | 56 +++++++++++++++++++++++++
  4 files changed, 97 insertions(+)

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index 6cd2a92b86..fd50a034a3 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -360,4 +360,35 @@ target_ulong HELPER(sha512sig1h)(target_ulong rs1, 
target_ulong rs2)
      return sext_xlen(result);
  }
  #undef zext32
+
+#define ROR64(a, amt) ((a << (-amt & 63)) | (a >> (amt & 63)))

Same comments for patch 8.


r~