On 1/28/22 02:46, Peter Maydell wrote:
Now that we have dealt with the one special case (highbank) that needed
to set both psci_conduit and secure_board_setup, we don't need to
allow that combination any more. It doesn't make sense in general,
so use an assertion to ensure we don't add new boards
On 220131 0806, Thomas Huth wrote:
> > On 29/1/22 14:34, Peter Maydell wrote:
> > > Hi; the build-oss-fuzz gitlab CI job seems to intermittently
> > > but quite commonly hit the 1 hour timeout mark and get killed.
> > > Examples from the last couple of days:
> > >
> > > https://gitlab.com/qemu-pro
On 1/28/22 02:46, Peter Maydell wrote:
Guest code on highbank may make non-PSCI SMC calls in order to
enable/disable the L2x0 cache controller (see the Linux kernel's
arch/arm/mach-highbank/highbank.c highbank_l2c310_write_sec()
function). The ABI for this is documented in kernel commit
8e56130d
On 1/28/22 02:46, Peter Maydell wrote:
If we're using PSCI emulation to start secondary CPUs, there is no
point in writing the "secondary boot" stub code, because it will
never be used -- secondary CPUs start powered-off, and when powered
on are set to begin execution at the address specified by
On 1/28/22 02:46, Peter Maydell wrote:
The highbank and midway board code includes boot-stub code for
handling secondary CPU boot which keeps the secondaries in a pen
until the primary writes to a known location with the address they
should jump to.
This code is never used, because the boards en
On 1/28/22 02:46, Peter Maydell wrote:
If we're using PSCI emulation, we add a /psci node to the device tree
we pass to the guest. At the moment, if the dtb already has a /psci
node in it, we retain it, rather than replacing it. (This behaviour
was added in commit c39770cd637765 in 2018.)
This
On 1/28/22 02:46, Peter Maydell wrote:
We use the arm_boot_info::nb_cpus field in only one place, and that
place can easily get the number of CPUs locally rather than relying
on the board code to have set the field correctly. (At least one
board, xlnx-versal-virt, does not set the field despite
On 1/31/22 10:57, Philipp Tomsich wrote:
Signed-off-by: Philipp Tomsich
Suggested-by: Richard Henderson
---
Changes in v4:
- use a typedef into 'RISCVCPUConfig' (instead of the explicit
'struct RISCVCPUConfig') to comply with the coding standard
(as suggested in Richard's review of v3)
C
On 30.01.22 23:50, Niek Linnenbank wrote:
> Hi David,
Hi Niek,
thanks for the report.
>
> While I realize my response is quite late, I wanted to report this error
> I found when running the acceptance
> tests for the orangepi-pc machine using avocado:
>
> ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_A
On 1/31/22 10:57, Philipp Tomsich wrote:
In adding our first X-extension (i.e., vendor-defined) on RISC-V with
XVentanaCondOps, we need to add a few instructure improvements to make
it easier to add similar vendor-defined extensions in the future:
- refactor access to the cfg->ext_* fields by ma
On Mon, 31 Jan 2022 at 09:25, Richard Henderson
wrote:
>
> On 1/31/22 10:57, Philipp Tomsich wrote:
> >
> > In adding our first X-extension (i.e., vendor-defined) on RISC-V with
> > XVentanaCondOps, we need to add a few instructure improvements to make
> > it easier to add similar vendor-defined e
On 1/31/22 10:57, Philipp Tomsich wrote:
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the av
On 28.01.22 16:19, Emanuele Giuseppe Esposito wrote:
On 26/01/2022 15:13, Hanna Reitz wrote:
On 21.01.22 18:05, Emanuele Giuseppe Esposito wrote:
Signed-off-by: Emanuele Giuseppe Esposito
---
job.c | 9 +
1 file changed, 9 insertions(+)
Just curious, why did you remove the asser
Peter Maydell wrote:
> On Thu, 27 Jan 2022 at 15:06, Juan Quintela wrote:
>>
>> The following changes since commit 48302d4eb628ff0bea4d7e92cbf6b726410eb4c3:
>>
>> Merge remote-tracking branch
>> 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20220126' into staging
>> (2022-01-26 10:59:50 +)
>>
"Dr. David Alan Gilbert" wrote:
> * Juan Quintela (quint...@redhat.com) wrote:
>> "Dr. David Alan Gilbert (git)" wrote:
>> > From: "Dr. David Alan Gilbert"
>> >
>> > Perform a check on vmsd structures during test runs in the hope
>> > of catching any missing terminators and other simple screwups
CC'ing Babu Moger who aded the Milan CPU model.
On Sat, Jan 29, 2022 at 07:23:37AM -0300, Leonardo Bras wrote:
> While trying to bring a VM with EPYC-Milan cpu on a host with
> EPYC-Milan cpu (EPYC 7313), the following warning can be seen:
>
> qemu-system-x86_64: warning: host doesn't support re
On Fri, Jan 28, 2022 at 4:42 PM Daniel P. Berrangé wrote:
>
> Hi Eduardo,
>
> You acked this series, but going through my old git branches I
> just discovered that this never got merged. I guess I was assuming
> you had queued it for a future PULL when you acked it.
>
> I don't mind sending a pull
On Mon, Jan 31, 2022 at 10:07:43AM +0100, Eduardo Otubo wrote:
> On Fri, Jan 28, 2022 at 4:42 PM Daniel P. Berrangé
> wrote:
> >
> > Hi Eduardo,
> >
> > You acked this series, but going through my old git branches I
> > just discovered that this never got merged. I guess I was assuming
> > you ha
On 1/27/22 3:29 PM, Jean-Philippe Brucker wrote:
> Currently the virtio-iommu device must be programmed before it allows
> DMA from any PCI device. This can make the VM entirely unusable when a
> virtio-iommu driver isn't present, for example in a bootloader that
> loads the OS from storage.
>
>
On 1/27/22 3:29 PM, Jean-Philippe Brucker wrote:
> The bypass config field should be initialized to 1 by default.
>
> Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Eric
> ---
> tests/qtest/virtio-iommu-test.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/qte
GCC options pairs -mlittle/-mlittle-endian and -mbig/-mbig-endian are
equivalent on ppc64 architecture. However, Clang supports only long
version of the options.
Use longer form in configure to properly support both GCC and Clang
compiler. In addition, fix this issue in tcg test configure.
Signed
Hi Jean,
On 1/27/22 3:29 PM, Jean-Philippe Brucker wrote:
> Update Linux headers to v5.17-rc1
>
> Signed-off-by: Jean-Philippe Brucker
Reviewed-by: Eric Auger
Eric
> ---
> include/standard-headers/asm-x86/kvm_para.h | 1 +
> include/standard-headers/drm/drm_fourcc.h | 11 ++
> include
On Fri, Jan 28, 2022 at 7:02 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > This series enables shadow virtqueue (SVQ) for vhost-vdpa devices. This
> > is intended as a new method of tracking the memory the devices touch
> > during a migration process: Instead of relay on vho
Hi Jean,
On 1/27/22 3:29 PM, Jean-Philippe Brucker wrote:
> The driver can create a bypass domain by passing the
> VIRTIO_IOMMU_ATTACH_F_BYPASS flag on the ATTACH request. Bypass domains
> perform slightly better than domains with identity mappings since they
> skip translation.
>
> Signed-off-by:
Le 29/01/2022 à 20:48, Serge Belyshev a écrit :
Signed-off-by: Serge Belyshev
---
linux-user/generic/target_resource.h | 1 +
linux-user/syscall.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/linux-user/generic/target_resource.h
b/linux-user/generic/target_resourc
On Fri, Jan 28, 2022 at 7:03 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > Is needed so vhost-vdpa knows the device's kick event fd.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > hw/virtio/vhost-shadow-virtqueue.h | 4
> > hw/virtio/vhost-shadow-virtqueue.c | 10
On 1/14/22 21:38, Matthew Rosato wrote:
Use the associated vfio feature ioctl to enable interpretation for devices
when requested. As part of this process, we must use the host function
handle rather than a QEMU-generated one -- this is provided as part of the
ioctl payload.
Signed-off-by: M
Le 29/01/2022 à 20:48, Serge Belyshev a écrit :
Signed-off-by: Serge Belyshev
---
linux-user/generic/target_resource.h | 1 +
linux-user/syscall.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/linux-user/generic/target_resource.h
b/linux-user/generic/target_resourc
Linux kernel required alined address of DTB.
But missing align in dtb load function.
Fixed to load to the correct address.
Signed-off-by: Yoshinori Sato
---
hw/rx/rx-gdbsim.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c
index 75d1fec6ca..f70472aeaf 10
Since SCI supports continuous data receive, Added that test.
Signed-off-by: Yoshinori Sato
---
tests/avocado/machine_rx_gdbsim.py | 29 +
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/tests/avocado/machine_rx_gdbsim.py
b/tests/avocado/machine_rx_gdb
SCI does not have a fifo, it is necessary to send and receive
at a bit rate speed.
But, qemu's chardev backend does not have a buffer,
so it sends received data continuously.
By buffering the received data with the FIFO, continuous
received data can be received.
Signed-off-by: Yoshinori Sato
-
Am 25.01.22 um 16:06 schrieb Daniel P. Berrangé:
> On Mon, Jan 24, 2022 at 02:50:39PM +0100, Markus Armbruster wrote:
>> Stefan Reiter writes:
>>
>>> Since the removal of the generic 'qmp_change' command, one can no longer
>>> replace
>>> the 'default' VNC display listen address at runtime (AFAIK
> As a small improvement, we don't need aio_co_enter() in job_start(),
> we can simplify it with qemu_coroutine_enter(). If the aio_context
> where it is running is wrong, job_do_yield_locked() will automatically
> reschedule the coroutine where it belongs, once the first
> job_pause_point is trigg
On Fri, Jan 28, 2022 at 7:29 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > This function allows the vhost-vdpa backend to override kick_fd.
> >
> > Signed-off-by: Eugenio Pérez
> > ---
> > hw/virtio/vhost-shadow-virtqueue.h | 1 +
> > hw/virtio/vhost-shadow-virtqueue.c
We did not add documentation to the storage daemon's man page for fuse's
allow-other option when it was introduced, so do that now.
Fixes: 8fc54f9428b9763f800 ("export/fuse: Add allow-other option")
Signed-off-by: Hanna Reitz
---
v2:
- Replaced instances of "QSD" by more generic descriptions, as
On 25.01.22 14:57, David Hildenbrand wrote:
> During precopy we usually write all plugged ares and essentially
> allocate them. However, there are two corner cases:
>
> 1) Migrating the zeropage
>
> When the zeropage gets migrated, we first check if the destination range is
> already zero and avo
On Fri, Jan 28, 2022 at 7:33 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > At this mode no buffer forwarding will be performed in SVQ mode: Qemu
> > will just forward the guest's kicks to the device.
> >
> > Also, host notifiers must be disabled at SVQ start, and they will n
On Sun, 30 Jan 2022 23:35:37 +0100
Niek Linnenbank wrote:
Hi,
(CC:ing Samuel for his intimate Allwinner BootROM knowledge)
> Hi Peter,
>
>
>
> On Thu, Jan 27, 2022 at 4:46 PM Peter Maydell
> wrote:
>
> > Change the allwinner-h3 based board to use the new boot.c
> > functionality to allow u
As the number of extensions is growing, copying them individiually
into the DisasContext will scale less and less... instead we populate
a pointer to the RISCVCPUConfig structure in the DisasContext.
This adds an extra indirection when checking for the availability of
an extension (compared to cop
The Zb[abcs] support code still uses the RISCV_CPU macros to access
the configuration information (i.e., check whether an extension is
available/enabled). Now that we provide this information directly
from DisasContext, we can access this directly via the cfg_ptr field.
Signed-off-by: Philipp Tom
Signed-off-by: Philipp Tomsich
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
---
(no changes since v4)
Changes in v4:
- use a typedef into 'RISCVCPUConfig' (instead of the explicit
'struct RISCVCPUConfig') to comply with the coding standard
(as suggested in Richard's revi
From: Daniel Henrique Barboza
pnv_phb4_translate_tve() is quite similar to pnv_phb3_translate_tve(),
and that includes the fact that 'taddr' can be considered uninitialized
when throwing the "TCE access fault" error because, in theory, the loop
that sets 'taddr' can be skippable due to 'lev' bein
From: Fabiano Rosas
Remove setting of BookE registers.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220124184605.999353-6-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 4
1 file changed, 4 deletions(-)
diff --git a/ta
In adding our first X-extension (i.e., vendor-defined) on RISC-V with
XVentanaCondOps, we need to add a few instructure improvements to make
it easier to add similar vendor-defined extensions in the future:
- refactor access to the cfg->ext_* fields by making a pointer to the
cfg structure (as
The implementation in trans_{rvi,rvv,rvzfh}.c.inc accesses the shallow
copies (in DisasContext) of some of the elements available in the
RISCVCPUConfig structure. This commit redirects accesses to use the
cfg_ptr copied into DisasContext and removes the shallow copies.
Signed-off-by: Philipp Toms
This adds the decoder and translation for the XVentanaCondOps custom
extension (vendor-defined by Ventana Micro Systems), which is
documented at
https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf
This commit then also adds a gua
From: Fabiano Rosas
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220118184448
From: Daniel Henrique Barboza
The 'taddr' variable is left unintialized, being set only inside the
"while ((lev--) >= 0)" loop where we get the TCE address. The 'lev' var
is an int32_t that is being initiliazed by the GETFIELD() macro, which
returns an uint64_t.
For a human reader this means tha
From: Fabiano Rosas
powerpc_excp_40x applies only to the 405, so remove HV code and
references to BookE.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220118184448.852996-7-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 26 ++
From: Fabiano Rosas
powerpc_excp_books is BookS only, so remove 40x and BookE code.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220124184605.999353-4-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 17 -
1 fi
From: Alexey Kardashevskiy
"PowerPC Processor binding to IEEE 1275" says in
"8.2.1. Initial Register Values" that the initial state is defined as
32bit so do it for both SLOF and VOF.
This should not cause behavioral change as SLOF switches to 64bit very
early anyway. As nothing enforces LE anyw
The XVentanaCondOps extension is supported by VRULL on behalf of the
Ventana Micro. Add myself as a point-of-contact.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- add a MAINTAINERS entry for XVentanaCondOps
MAINTAINERS | 7 +++
From: Fabiano Rosas
Remove the BookE code and add a comment explaining why we need to keep
hypercall support even though this CPU does not have a hypervisor
mode.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-7-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
targ
To split up the decoder into multiple functions (both to support
vendor-specific opcodes in separate files and to simplify maintenance
of orthogonal extensions), this changes decode_op to iterate over a
table of decoders predicated on guard functions.
This commit only adds the new structure and th
From: Fabiano Rosas
The 74xx don't have an MSR_HV.
Also remove 40x and BookE code.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-4-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 24
1 file changed, 24 deletion
From: Fabiano Rosas
There's no sc 1.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Message-Id: <20220118184448.852996-9-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 21 ++---
1 file changed,
From: Fabiano Rosas
The --disable-tcg build broke when do_rfi stopped being inlined.
Fixes: 62e79ef914 ("target/ppc: Remove static inline")
Signed-off-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220124191547.1008391-1-faro...@linux
From: Fabiano Rosas
Since this is now BookS only, we can simplify the code a bit and check
has_hv_mode instead of enumerating the exception models. LPES0 does
not make sense if there is no MSR_HV.
Note that QEMU does not support HV mode on 970 and POWER5+ so we don't
set MSR_HV in msr_mask.
Sig
From: Fabiano Rosas
The 405 Program Interrupt does not set SRR1 with any diagnostic bits,
just a clean copy of the MSR.
We're using the BookE Exception Syndrome Register which is different
from the 405.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
[ clg: restored SPR_40x_ESR set
From: Frederic Barrat
If an iommu page has wrong permissions, an error message is displayed,
but the access is allowed, which is odd. This patch fixes it.
Signed-off-by: Frederic Barrat
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220121152350.381685-1-fbar...@linux.ibm.com>
Signed-off-
From: Fabiano Rosas
The 405 ISI does not set SRR1 with any exception syndrome bits, only a
clean copy of the MSR.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
[ clg : Fixed removal which was done in the wrong routine ]
Message-Id: <20220118184448.852996-13-faro...@linux.ibm.com>
From: Fabiano Rosas
There is no DSISR in the 405. It uses DEAR which we already set
earlier at ppc_cpu_do_unaligned_access.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 7 ---
1 file changed, 7 deletions(-)
diff --
From: Fabiano Rosas
Introduce a new powerpc_excp function specific for 40x CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Message-Id: <20220118184448.852996-4-far
From: Fabiano Rosas
Introduce a new powerpc_excp function specific for PowerPC 74xx
CPUs. This commit copies powerpc_excp_legacy verbatim so the next one
has a clean diff.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-2-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
From: Fabiano Rosas
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- Always uses HV_EMU if the CPU has MSR_HV;
- Exceptions always delivered in 64 bit.
Exceptions used:
POWERPC_EXCP_ALIGN
POWERPC_EXCP_DECR
POWERPC_EXCP_DSEG
POWE
From: Fabiano Rosas
The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-9-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 13 ++-
On Saturday, 2022-01-29 at 07:23:37 -03, Leonardo Bras wrote:
> While trying to bring a VM with EPYC-Milan cpu on a host with
> EPYC-Milan cpu (EPYC 7313), the following warning can be seen:
>
> qemu-system-x86_64: warning: host doesn't support requested feature:
> CPUID.07H:EBX.erms [bit 9]
> qe
From: Fabiano Rosas
The current Debug exception dispatch is the BookE one, so it is
different from the 405. We effectively don't support the 405 Debug
exception.
This patch removes the BookE code and moves the DEBUG into the "not
implemented" block.
Note that there is in theory a functional cha
From: Philippe Mathieu-Daudé
vof.h requires "qom/object.h" for DECLARE_CLASS_CHECKERS(),
"exec/memory.h" for address_space_read/write(),
"exec/address-spaces.h" for address_space_memory
and more importantly "cpu.h" for target_ulong.
vof.c doesn't need "exec/ram_addr.h".
Signed-off-by: Philippe
Commit cd0c6f473532 did not take into account 405 CPUs when adding
support to batching of TCG tlb flushes. Set the TLB_NEED_LOCAL_FLUSH
flag when the SPR_40x_PID is set or a TLB updated.
Cc: Thomas Huth
Cc: Christophe Leroy
Cc: Fabiano Rosas
Reviewed-by: Fabiano Rosas
Fixes: cd0c6f473532 ("ppc
POWERPC_MMU_BOOKE is not a mask and should not be tested with a
bitwise AND operator.
It went unnoticed because it only impacts the 601 CPU implementation
for which we don't have a known firmware image.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20220124081609.367234
From: Daniel Henrique Barboza
spapr_get_fw_dev_path() is an impl of
FWPathProviderClass::get_dev_path(). This interface is used by
hw/core/qdev-fw.c via fw_path_provider_try_get_dev_path() in two
functions:
- static char *qdev_get_fw_dev_path_from_handler(), which is used only in
qdev_get_fw_dev
From: Fabiano Rosas
The 74xx don't have MSR_HV so all the LPES0 logic can be removed.
Also remove the BookE IRQ code.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-5-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 38 --
From: Fabiano Rosas
405 has no MSR_HV and EPR is BookE only so we can remove it all.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220118184448.852996-8-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 37 --
From: Fabiano Rosas
In powerpc_excp_40x the Critical exception is now for 405 only, so we
can remove the BookE and G2 blocks.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20220118184448.852996-6-faro...@linux.ibm.com>
Signed-off-by: Cédric
From: Fabiano Rosas
The whole power saving states logic seems to be dependent on HV mode,
which don't exist for 74xx so I'm removing it all and leaving the
abort message.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-8-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
-
From: Fabiano Rosas
Remove references to BookE.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220118184448.852996-15-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/tar
From: Fabiano Rosas
The 405 MSR has the Machine Check Enable bit. We're making use of it
when dispatching Machine Check, so add the bit to the msr_mask.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220118184448.852996-3-faro...@linux.ibm.com>
Signed-off-by: Cédric
Commit aff0e204cb1f1c036a496c94c15f5dfafcd9b4b4 introduced CF_NOIRQ usage,
but one case was forgotten. Record/replay uses one special TB which is not
really executed, but used to cause a correct exception in replay mode.
This patch adds CF_NOIRQ flag for such block.
Signed-off-by: Pavel Dovgalyuk
The 602 was derived from the PowerPC 603, for the gaming market it
seems. It was hardly used and no firmware supporting the CPU could be
found. Drop support.
Signed-off-by: Cédric Le Goater
---
target/ppc/cpu-models.h | 1 -
target/ppc/cpu.h | 8 +-
target/ppc/helper.h
From: Fabiano Rosas
Remove the BookE ESR setting.
Signed-off-by: Fabiano Rosas
Message-Id: <20220127201116.1154733-6-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc
From: Fabiano Rosas
The 405 has no DSISR or DAR, so convert the trace entry to
use ESR and DEAR instead.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
[ clg : - changed registers to ESR and DEAR.
- updated commit log ]
Message-Id: <20220118184448.852996-12-faro...@linux.ib
From: Daniel Henrique Barboza
cpu_interrupt_exittb() was introduced by commit 044897ef4a22
("target/ppc: Fix system lockups caused by interrupt_request state
corruption") as a way to wrap cpu_interrupt() helper in BQL.
After that, commit 6d38666a8931 ("ppc: Ignore the CPU_INTERRUPT_EXITTB
interr
The ldq_be_dma() routine was recently changed to return a result of
the transaction. Use it when loading the virtual structure descriptors
in the XIVE PowerNV model.
Cc: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
Message-Id: <20220124081635.3672439-1-...@kaod.org>
Signed-off-by: Cédr
Added myself as a reviewer of vmgenid, unimplemented device and empty slot.
Signed-off-by: Ani Sinha
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b43344fa98..fed31a5eb5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2182,6 +2182,7 @@ F: t
From: Fabiano Rosas
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Alternate Interrupt Location.
Exceptio
From: Christophe Leroy
After a TLB miss exception, GPRs 0-3 must be restored on rfi.
This is managed by hreg_store_msr() which is called by do_rfi()
However, hreg_store_msr() does it if MSR[TGPR] is unset in the
passed MSR value.
The problem is that do_rfi() is given the content of SRR1 as
the
Currently the responses of QMP commands query-sev-launch-measure and
query-sev-attestation-report return just the signed measurement. In
order to validate it, the Guest Owner must know the exact guest launch
digest, besides other host and guest properties which are included in
the measurement.
The
On 1/24/2022 3:26 PM, Alex Bennée wrote:
> Oleg Vasilev writes:
>
>> From: Oleg Vasilev
>>
>> Plugin can be used to track statistics based on virtual address mask
>> matching.
>> Useful for tracking kernel vs user translation blocks.
> Could we have a bit more detail please, maybe some words fo
From: Fabiano Rosas
Introduce a new powerpc_excp function specific for BookS CPUs. This
commit copies powerpc_excp_legacy verbatim so the next one has a clean
diff.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Message-Id: <20220124184605.999353-2-faro...@linux.ibm.com>
Signed-off
The following changes since commit cfe63e46be0a1f8a7fd2fd5547222f8344a43279:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2022-01-27-v2'
into staging (2022-01-27 15:45:13 +)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-ppc-20220130
On 27/01/2022 11:56, Kevin Wolf wrote:
> Am 21.01.2022 um 18:05 hat Emanuele Giuseppe Esposito geschrieben:
>> When invoked from the main loop, this function is the same
>> as qemu_mutex_iothread_locked, and returns true if the BQL is held.
>
> So its name is misleading because it doesn't answe
On Montag, 31. Januar 2022 08:35:24 CET Greg Kurz wrote:
> > > > diff --git a/tests/qtest/libqos/virtio-9p.c
> > > > b/tests/qtest/libqos/virtio-9p.c index ef96ef006adc..0a0d0d16709b
> > > > 100644
> > > > --- a/tests/qtest/libqos/virtio-9p.c
> > > > +++ b/tests/qtest/libqos/virtio-9p.c
> > > > @@
On Saturday, 2022-01-29 at 06:46:45 -03, Leonardo Bras wrote:
> The following steps describe a migration bug:
> 1 - Bring up a VM with -cpu EPYC on a host with EPYC-Milan cpu
> 2 - Migrate to a host with EPYC-Naples cpu
>
> The guest kernel crashes shortly after the migration.
>
> The crash happen
From: Fabiano Rosas
Differences from the generic powerpc_excp code:
- Not BookE, so some MSR bits are cleared at interrupt dispatch;
- No MSR_HV or MSR_LE;
- No power saving states;
- No Hypervisor Emulation Assistance;
- Not 64 bits;
- No System call vectored;
- No Interrupts Little Endian;
- N
On Mon, Jan 31, 2022 at 11:15:39AM +, Dov Murik wrote:
> Currently the responses of QMP commands query-sev-launch-measure and
> query-sev-attestation-report return just the signed measurement. In
> order to validate it, the Guest Owner must know the exact guest launch
> digest, besides other ho
From: Vitaly Cheptsov
Book-E architecture does not set the error code in 31:27 bits
of SRR1, but instead uses these bits for custom fields such
as GS (Guest Supervisor).
Wrongly setting these fields will result in QEMU crashes
when attempting to execute not executable code due to the attempts
to
Cédric Le Goater writes:
> The 602 was derived from the PowerPC 603, for the gaming market it
> seems. It was hardly used and no firmware supporting the CPU could be
> found. Drop support.
>
> Cc: Fabiano Rosas
> Cc: Víctor Colombo
> Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
On Fri, Jan 28, 2022 at 7:57 AM Jason Wang wrote:
>
>
> 在 2022/1/22 上午4:27, Eugenio Pérez 写道:
> > At this moment no buffer forwarding will be performed in SVQ mode: Qemu
> > just forward the guest's kicks to the device. This commit also set up
> > SVQs in the vhost device.
> >
> > Host memory noti
On Mon, 31 Jan 2022 11:47:00 +0530
Ani Sinha wrote:
> On Wed, Jan 12, 2022 at 6:33 PM Igor Mammedov wrote:
> >
> > Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
> > fields in headers of ACPI tables. While it doesn't have impact on
> > default values since QEMU uses 6 and 8 ch
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