From: Daniel P. Berrangé
Cleanup the package lists by removing some entries that we don't need to
directly reference
binutils: implied by the compiler toolchain
coreutils: not required by QEMU build
mesa-egl mesa-gbm: implied by mesa-dev
ninja: alias for samurai package
shadow: not req
The pgb_find_hole function goes to the trouble of taking account of
both mmap_min_addr and any offset we've applied to decide the starting
address of a potential hole. This is especially important for
emulating 32bit ARM in a 32bit build as we have applied the offset to
ensure there will be space t
On 1/10/22 06:04, Alexey Kardashevskiy wrote:
The following changes since commit 0625c7760d5451d7436ef0738f763c6bb5141919:
target/ppc: do not call hreg_compute_hflags() in helper_store_mmcr0()
(2022-01-04 07:55:35 +0100)
are available in the Git repository at:
g...@github.com:aik/qemu.g
From: Thomas Huth
It's likely broken, and nobody cared for picking it up again
during the deprecation phase, so let's remove this now.
Since this is the last entry in deprecated_targets_list, remove
the related code in the configure script, too.
Signed-off-by: Thomas Huth
Reviewed-by: Richard
From: Daniel P. Berrangé
This commit is best examined using the "-b" option to diff.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Daniel P. Berrangé
Signed-off-by: Alex Bennée
Message-Id: <20211215141949.3512719-19-berra...@redhat.com>
Message-Id: <20220105135009.1584676-19-alex.ben...@
On 1/11/22 21:01, Daniel Henrique Barboza wrote:
Hi,
This is something that caught my eye when I was looking into the
instances where we need stack properties versus phb4 properties.
I tested this fix and it doesn't seem to impact the boot process
whatsoever. Tracing pnv_pec_stk_pci_xscom_write
From: Brad Smith
Note, since libtasn1 was fixed in 12.3 [*], this commit re-enables GnuTLS.
[*] https://gitlab.com/gnutls/libtasn1/-/merge_requests/71
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
Reviewed-by: Warner Losh
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Review
On 1/5/22 11:32, Thomas Huth wrote:
The Protected Execution Facility is only available with the pseries
machine, so let's merge the old ASCII text into the new RST file now.
Signed-off-by: Thomas Huth
Applied to ppc7.0.
Thanks,
C.
From: Paolo Bonzini
The two more or less overlap, because CONFIG_LINUX is a requirement for Linux
user-mode emulation. However, CONFIG_LINUX is technically a host symbol
that applies even to system emulation. Defining CONFIG_LINUX_USER, and
CONFIG_BSD_USER for eventual future use, is cleaner.
On 1/11/22 14:10, Daniel Henrique Barboza wrote:
Hi,
This version implements Cedric's review suggestions from v4. No
drastic design changes were made.
Changes from v4:
- patches 1,3,5: unchanged
- patch 2:
* renamed function to pnv_phb4_xscom_realize()
* pnv4_phb4_xscom_realize() is now c
On 1/5/22 10:51, Cédric Le Goater wrote:
Hello,
Grab the images under :
https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64_pseries_p5p-2021.11-730-g4f325ce788-20220104
and run with :
qemu-system-ppc64 -M pseries -cpu POWER5+ -m 1G -smp 2 -kernel ./vmlinux -append
This cleanups the PHB3 model a bit more since the root port is an
independent device and it will ease our task when adding user created
PHB3s.
pnv_phb_attach_root_port() is made public in pnv.c so it can be reused
with the pnv_phb4 root port later.
Signed-off-by: Cédric Le Goater
Signed-off-by:
On 1/5/22 11:48, Thomas Huth wrote:
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Signed-off-by: Thomas Huth
---
MAINTAINERS | 12
1 file cha
Using _qemu is a little confusing. Let's use _compat for these sorts
of things. We should also mention _impl which is another common suffix
in the code base.
Signed-off-by: Alex Bennée
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20220105135009.1584676-25-ale
Hello,
This patchset adds vhost-user-gpio device's support in Qemu. The support for the
same has already been added to virtio specification and Linux Kernel.
A Rust based backend is also in progress and is tested against this patchset:
https://github.com/rust-vmm/vhost-device/pull/76
--
Viresh
From: Fabiano Rosas
Remove the compile time definition and make the logging be controlled
by the `-d mmu` option in the cmdline.
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
Message-Id: <20220107222601.4101511-3-faro...@linux.ibm.com>
Signed-off-by: Céd
From: Thomas Huth
The Protected Execution Facility is only available with the pseries
machine, so let's merge the old ASCII text into the new RST file now.
Signed-off-by: Thomas Huth
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20220105103232.405204-1-th...@redhat.com>
Signed-off-by: Cédr
On Tue, 11 Jan 2022 at 09:00, Laurent Vivier wrote:
>
> Le 11/01/2022 à 09:29, Peter Maydell a écrit :
> > The clang in Ubuntu 18.04 (10.0.0-4ubuntu1) produces a warning
> > on the code added in commit f5ef0e518d03 where we use a
> > shifted expression in a boolean context:
> >
> > ../../linux-use
From: Fabiano Rosas
Next patches will split powerpc_excp in multiple family specific
handlers. This patch adds a wrapper to make the transition clearer.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220107222601.4101511-8-faro...@linux.ibm.com>
Signed-off-by: Cédric Le
From: Richard Henderson
We need to read the floating-point flags before printf may do
other floating-point operations which may affect the flags.
Hexagon reference files regenerated by Taylor Simpson.
Signed-off-by: Taylor Simpson
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu
Am 12.01.22 um 10:59 schrieb Ilya Dryomov:
> On Mon, Jan 10, 2022 at 12:43 PM Peter Lieven wrote:
>> librbd had a bug until early 2022 that affected all versions of ceph that
>> supported fast-diff. This bug results in reporting of incorrect offsets
>> if the offset parameter to rbd_diff_iterate2
POWER5+ (ISA v2.03) processors are supported by the pseries machine
but they do not have Altivec instructions. Do not advertise support
for it in the DT.
To be noted that this test is in contradiction with the assert in
cap_vsx_apply().
Signed-off-by: Cédric Le Goater
Tested-by: Fabiano Rosas
M
s/pull-ppc-20220112
for you to fetch changes up to f83460bb203a49dd1693bf8b664d2a935a5be621:
ppc/pnv: use stack->pci_regs[] in pnv_pec_stk_pci_xscom_write() (2022-01-12
11:28:27 +0100)
ppc 7.0 queue:
* New SLOF for PPC970 and PO
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: Cédric Le Goater
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20220107222601.4101511-4-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 77 +---
From: Daniel Henrique Barboza
pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.
Instead of asserting, check if the root port exists
From: Daniel Henrique Barboza
When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:
qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3:
Can't add chassis slot, error -16
This er
From: Daniel Henrique Barboza
A similar situation as described previously with pnv_phb3_root_port
devices also happens with pnv_phb4_root_ports.
The solution is the same: assign an unique chassis/slot combo for them.
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20220105212338.49899-3-da
From: Fabiano Rosas
We use the endianness of interrupts to determine which endianness to
use for the guest kernel memory dump. For machines that support HILE
(powernv8 and up) we have been always generating big endian dump
files.
This patch uses the HILE support recently added to
ppc_interrupts_
From: Daniel Henrique Barboza
Moving all phb4 properties setup to stk_realize() keeps this logic in
a single place instead of having it scattered between stk_realize() and
pec_realize().
'phb->index' can be retrieved using stack->stack_no and
pnv_phb4_pec_get_phb_id(), deprecating the use of 'ph
popcntb instruction was added in ISA v2.02. Add support for POWER5+
processors since they implement ISA v2.03.
PPC970 CPUs implement v2.01 and do not support popcntb.
Signed-off-by: Cédric Le Goater
Reviewed-by: Fabiano Rosas
Message-Id: <20220105095142.3990430-2-...@kaod.org>
Signed-off-by: Cé
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Cédric Le Goater
Message-Id:
<3b228af4785241c7fb4a2c70f0c495d2a9adea83.1641405872.git.lagar...@br.ibm.com>
Signed-off-by: Cédric Le Goater
---
docs/specs/ppc-spapr-hcalls.rst | 21 -
docs/system/ppc/pseries.rst
It is not used elsewhere so that's where it belongs.
Signed-off-by: Cédric Le Goater
Message-Id: <20220105212338.49899-10-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 4 ++--
hw/ppc/pnv.c | 7 +++
2 files changed, 5 insertions(+), 6 deletions(-)
ISA v2.03 introduced Floating Round to Integer instructions : frin,
friz, frip, and frim. Add them to POWER5+.
The PPC_FLOAT_EXT flag also includes the fre (Floating Reciprocal
Estimate) instruction which was introduced in ISA v2.0x. The
architecture document says its optional and that might be th
From: Daniel Henrique Barboza
The logic inside pnv_pec_phb_offset() will be useful in the next patch
to determine the stack that should contain a PHB4 device.
Move the function to pnv_phb4.c and make it public since there's no
pnv_phb4_pec.h header. While we're at it, add 'stack_index' as a
para
From: Daniel Henrique Barboza
Similar to what was happening with pnv-phb3 buses,
TYPE_PNV_PHB4_ROOT_BUS set to "pnv-phb4-root-bus" is a bit too long for
a default root bus name. The usual default name for theses buses in QEMU
are 'pcie', but we want to make a distinction between pnv-phb4 buses an
From: Fabiano Rosas
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The p
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Cédric Le Goater
Message-Id: <20220105212338.49899-9-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 9 +
hw/ppc/pnv.c
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB3 device is parented to its chip by reparenting th
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices, a lookup on 'chip-id' is required to assign the
own
From: Daniel Henrique Barboza
We want to create only the absolutely minimal amount of devices when
running with -nodefaults. The root port is something that the machine
can boot up without. But, to do that, we need to provide a way for the
user to add them by hand.
This patch makes pnv-phb4-root
From: Daniel Henrique Barboza
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pSeries spapr-pci-host
From: Daniel Henrique Barboza
Its only callers are inside pnv_phb4.c.
Reviewed-by: Cédric Le Goater
Signed-off-by: Daniel Henrique Barboza
Message-Id: <2022031027.599784-6-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 1 -
hw/pci-host/pnv_ph
From: Fabiano Rosas
The ppc_interrupts_little_endian function is now suitable for
determining the endianness of interrupts for all CPUs.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Message-Id: <20220107222601.4101511-7-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
tar
From: Daniel Henrique Barboza
pnv_pec_stk_pci_xscom_write() is pnv_pec_stk_pci_xscom_ops write
callback. It writes values into regs in the stack->nest_regs[] array.
The pnv_pec_stk_pci_xscom_read read callback, on the other hand, returns
values of the stack->pci_regs[]. In fact, at this moment, t
Anup Patel 於 2021年12月30日 週四 下午8:47寫道：
> From: Anup Patel
>
> The AIA specification introduces new [m|s|vs]topi CSRs for
> reporting pending local IRQ number and associated IRQ priority.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> ---
> target/riscv/csr.c | 156
From: Fabiano Rosas
Some CPUs set ILE via an MSR bit. We can make
ppc_interrupts_little_endian handle that case as well. Now we have a
centralized way of determining the endianness of interrupts.
This change has no functional impact.
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Mess
From: Fabiano Rosas
Signed-off-by: Fabiano Rosas
Reviewed-by: David Gibson
Reviewed-by: Richard Henderson
Message-Id: <20220107222601.4101511-2-faro...@linux.ibm.com>
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 65 +++-
1 file changed, 3
Interaction with vmnet.framework in different modes
differs only on configuration stage, so we can create
common `send`, `receive`, etc. procedures and reuse them.
vmnet.framework supports iov, but writing more than
one iov into vmnet interface fails with
'VMNET_INVALID_ARGUMENT'. Collecting provi
On Wed, Jan 12, 2022 at 12:55 PM Peter Lieven wrote:
>
> Am 12.01.22 um 10:59 schrieb Ilya Dryomov:
> > On Mon, Jan 10, 2022 at 12:43 PM Peter Lieven wrote:
> >> librbd had a bug until early 2022 that affected all versions of ceph that
> >> supported fast-diff. This bug results in reporting of in
From: Daniel Henrique Barboza
This patch introduces pnv-phb4 user creatable devices that are created
in a similar manner as pnv-phb3 devices, allowing the user to interact
with the PHBs directly instead of creating PCI Express Controllers that
will create a certain amount of PHBs per controller i
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-bridged.m | 100 +---
1 file changed, 94 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-bridged.m b/net/vmnet-bridged.m
index 4e42a90391..19a68a6a1c 100644
--- a/net/vmnet-bridged.m
+++ b/net/vmnet-br
macOS provides networking API for VMs called 'vmnet.framework':
https://developer.apple.com/documentation/vmnet
We can provide its support as the new QEMU network backends which
represent three different vmnet.framework interface usage modes:
* `vmnet-shared`:
allows the guest to communicat
Signed-off-by: Vladislav Yaroshchuk
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c98a61caee..638d129305 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2641,6 +2641,11 @@ W: http://info.iet.unipi.it/~luigi/netmap/
S: Maintained
F: net/n
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-host.c | 96 +---
1 file changed, 90 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-host.c b/net/vmnet-host.c
index 4a5ef99dc7..eee4daf74b 100644
--- a/net/vmnet-host.c
+++ b/net/vmnet-host.c
@@ -
Create separate netdevs for each vmnet operating mode:
- vmnet-host
- vmnet-shared
- vmnet-bridged
Signed-off-by: Vladislav Yaroshchuk
---
net/clients.h | 11
net/meson.build | 7 +++
net/net.c | 10
net/vmnet-bridged.m | 25
net/vmnet-common.m | 20
Anup Patel 於 2021年12月30日 週四 下午8:37寫道：
> From: Anup Patel
>
> We should be returning illegal instruction trap when RV64 HS-mode tries
> to access RV32 HS-mode CSR.
>
> Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Pa
From: Daniel Henrique Barboza
Relying on stack->phb to write the xscom DT of the PEC is something that
we won't be able to do with user creatable pnv-phb4 devices.
Hopefully, this can be done by using pnv_phb4_pec_get_phb_id(), which is
already used by pnv_pec_realize() to set the phb-id of the
Am 17.12.2021 um 17:46 hat Vladimir Sementsov-Ogievskiy geschrieben:
> Hi all!
>
> 01: only update test output rebasing on master
> 02: replaced with my proposed solution.
Thanks, applied to the block branch.
Kevin
From: Daniel Henrique Barboza
At this moment, stack->phb is the plain PnvPHB4 device itself instead of
a pointer to the device. This will present a problem when adding user
creatable devices because we can't deal with this struct and the
realize() callback from the user creatable device.
We can'
> On 11 Jan 2022, at 00:55, Alistair Francis wrote:
>
> I would expect them to just be referred to by QEMU internally.
I checked and there are indeed several files referred internally.
> My guess would be keep *arm*/*aarch64*, keymaps, npcm7xx_bootrom.bin,
> efi-* and linuxboot*/multiboot*.
From: Daniel Henrique Barboza
The 'stack->phb_regs_mr' PHB4 passthrough XSCOM initialization relies on
'stack->phb' being not NULL. Moving 'stack->phb_regs_mr' region_init()
and add_subregion() to phb4_realize() time is a natural thing to do
since it's strictly PHB related.
The remaining XSCOM i
Anup Patel 於 2021年12月30日 週四 下午8:36寫道：
> From: Anup Patel
>
> We define a CPU feature for AIA CSR support in RISC-V CPUs which
> can be set by machine/device emulation. The RISC-V CSR emulation
> will also check this feature for emulating AIA CSRs.
>
> Signed-off-by: Anup Patel
> Signed-off-by:
Anup Patel 於 2021年12月30日 週四 下午8:52寫道：
> From: Anup Patel
>
> The RISC-V AIA specification extends RISC-V local interrupts and
> introduces new CSRs. This patch adds defines for the new AIA CSRs.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-by: Alistair Francis
> ---
>
Anup Patel 於 2021年12月30日 週四 下午8:36寫道：
> From: Anup Patel
>
> The machine or device emulation should be able to force set certain
> CPU features because:
> 1) We can have certain CPU features which are in-general optional
>but implemented by RISC-V CPUs on the machine.
> 2) We can have device
On Wed, 2022-01-12 at 09:59 +0100, David Hildenbrand wrote:
> On 12.01.22 05:39, Ilya Leoshkevich wrote:
> > An overflow occurs for SLAG when at least one shifted bit is not
> > equal
> > to sign bit. Therefore, we need to check that `shift + 1` bits are
> > neither all 0s nor all 1s. The current c
From: Thomas Huth
Add some documentation files to the corresponding machine sections
and mention the machine names in the section titles where it is
not so obvious (e.g. that "taihu" is a 405 machine).
Signed-off-by: Thomas Huth
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Mark Cave-Aylan
ср, 12 янв. 2022 г. в 10:51, Jason Wang :
> On Wed, Jan 12, 2022 at 3:10 PM Roman Bolshakov wrote:
> >
> > On Wed, Jan 12, 2022 at 01:39:28PM +0800, Jason Wang wrote:
> > >
> > > 在 2022/1/12 上午6:02, Vladislav Yaroshchuk 写道:
> > > >
> > > >
> > > > вт, 11 янв. 2022 г., 5:10 AM Jason Wang :
> > > >
v2: https://lists.nongnu.org/archive/html/qemu-devel/2022-01/msg02488.html
v2 -> v3: Unify CC_OP_SLA_32 and CC_OP_SLA_64.
Add underscores to test macro parameters.
Shift CC in test asm.
Add a second SLAG test.
Add tags to commit messages.
v1: https://lists.n
vmnet.framework dependency is added with 'vmnet' option
to enable or disable it. Default value is 'auto'.
vmnet features to be used are available since macOS 11.0,
corresponding probe is created into meson.build.
Signed-off-by: Vladislav Yaroshchuk
---
meson.build | 23 +++
Anup Patel 於 2021年12月30日 週四 下午8:36寫道：
> From: Anup Patel
>
> The AIA device emulation (such as AIA IMSIC) should be able to set
> (or provide) AIA ireg read-modify-write callback for each privilege
> level of a RISC-V HART.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-b
The next commit will revert OEM fields padding with whitespace to
padding with '\0' as it was before [1]. As result test_oem_fields() will
fail due to unexpectedly smaller ID sizes read from QEMU ACPI tables.
Pad OEM_ID/OEM_TABLE_ID manually with spaces so that values the test
puts on QEMU CLI and
Signed-off-by: Vladislav Yaroshchuk
---
qemu-options.hx | 25 +
1 file changed, 25 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index ec90505d84..81dd34f550 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2732,6 +2732,25 @@ DEF("netdev", HAS_ARG, QE
Hello Gregory,
On 1/12/22 11:57, Graeme Gregory wrote:
On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
This series of patch introduce a dummy implemenation of aspeed i3c
model, and it provide just enough information for guest machine.
However, the driver probing is still failed, but i
Anup Patel 於 2021年12月30日 週四 下午9:06寫道：
> From: Anup Patel
>
> To facilitate software development of RISC-V systems with large number
> of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
>
> We also add a detailed source level comments about limit defines which
> impact the phy
SRDA uses r1_D32 for binding the first operand and s64 for setting CC.
cout_s64() relies on o->out being the shift result, however,
wout_r1_D32() clobbers it.
Fix by using a temporary.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Signed-off-by: Ilya Leoshkevich
Reviewed-by: David Hi
Anup Patel 於 2021年12月30日 週四 下午8:41寫道：
> From: Anup Patel
>
> The AIA hvictl and hviprioX CSRs allow hypervisor to control
> interrupts visible at VS-level. This patch implements AIA hvictl
> and hviprioX CSRs.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-by: Alistair Fr
Commit [2] broke original '\0' padding of OEM ID and OEM Table ID
fields in headers of ACPI tables. While it doesn't have impact on
default values since QEMU uses 6 and 8 characters long values
respectively, it broke usecase where IDs are provided on QEMU CLI.
It shouldn't affect guest (but may cau
On Mon, Jan 10, 2022 at 06:28:44PM -0500, John Snow wrote:
> Reported-by: Vladimir Sementsov-Ogievskiy
> Signed-off-by: John Snow
> ---
> python/qemu/aqmp/__init__.py | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/python/qemu/aqmp/__init__.py b/python/qemu/aqmp/__init_
Add a test for each shift instruction in order to to prevent
regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/shift.c | 270
2 files changed, 271 insertions(+)
create mode 100644 tests/tcg/s390x/sh
An overflow occurs for SLAG when at least one shifted bit is not equal
to sign bit. Therefore, we need to check that `shift + 1` bits are
neither all 0s nor all 1s. The current code checks only `shift` bits,
missing some overflows.
Fixes: cbe24bfa91d2 ("target-s390: Convert SHIFT, ROTATE SINGLE")
Since 6.0 the commit:
602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed")
regressed values of OEM [Table] ID fields in ACPI tables
by padding them with whitespace is a value is shorter then
max possible. That depending on vendor broke OEM [Table] ID patching
with SLIC table v
+Paolo who I forgot to Cc.
On 1/11/22 18:16, Roman Bolshakov wrote:
> On Mon, Jan 10, 2022 at 02:09:55PM +0100, Philippe Mathieu-Daudé wrote:
>> We can pass C/CPP/LD flags via CFLAGS/CXXFLAGS/LDFLAGS environment
>> variables, or via configure --extra-cflags / --extra-cxxflags /
>> --extra-ldflags
ср, 12 янв. 2022 г. в 11:22, Roman Bolshakov :
> On Wed, Jan 12, 2022 at 10:50:04AM +0300, Roman Bolshakov wrote:
> > On Wed, Jan 12, 2022 at 12:14:15AM +0300, Vladislav Yaroshchuk wrote:
> > > macOS provides networking API for VMs called 'vmnet.framework':
> > > https://developer.apple.com/docume
SLDA operates on 64-bit values, so its sign bit index should be 63,
not 31.
Fixes: a79ba3398a0a ("target-s390: Convert SHIFT DOUBLE")
Reported-by: David Hildenbrand
Signed-off-by: Ilya Leoshkevich
Reviewed-by: David Hildenbrand
---
target/s390x/tcg/insn-data.def | 2 +-
1 file changed, 1 inser
The next commit will revert OEM fields whitespace padding to
padding with '\0' as it was before [1]. That will change OEM
Table ID for:
* SSDT.*: where it was padded from 6 characters to 8
* FACP.slic: where it was padded from 2 characters to 8
after reverting whitespace padding, it will be rep
Expected changes caused by previous commit:
nvdimm ssdt (q35/pc/virt):
- * OEM Table ID "NVDIMM "
+ * OEM Table ID "NVDIMM"
SLIC test FADT (tests/data/acpi/q35/FACP.slic):
-[010h 0016 8] Oem Table ID : "ME "
+[010h 0016 8] Oem Tabl
From: Leonardo Garcia
This patch series depend on previously sent patch "docs: Clarification
and formatting changes in ppc docs." which is already included in latest
pull request from Cédric.
It is important to notice that I focused mainly in the layout of the
document, and not so much on the co
According to PoP, both 32- and 64-bit shifts use lowest 6 address
bits. The current code special-cases 32-bit shifts to use only 5 bits,
which is not correct. For example, shifting by 32 bits currently
preserves the initial value, however, it's supposed zero it out
instead.
Fix by merging sh32 and
On Mon, Jan 10, 2022 at 06:28:47PM -0500, John Snow wrote:
> Copy the remaining type definitions from QMP into the qemu.aqmp.legacy
> module. Now, users that require the legacy interface don't need to
> import anything else but qemu.aqmp.legacy wrapper.
>
> Signed-off-by: John Snow
> Reviewed-by:
Anup Patel 於 2021年12月30日 週四 下午8:57寫道：
> From: Anup Patel
>
> We add "x-aia" command-line option for RISC-V HART using which
> allows users to force enable CPU AIA CSRs without changing the
> interrupt controller available in RISC-V machine.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Pa
On Wed, Jan 12, 2022 at 08:03:29AM -0500, Igor Mammedov wrote:
> The next commit will revert OEM fields padding with whitespace to
> padding with '\0' as it was before [1]. As result test_oem_fields() will
> fail due to unexpectedly smaller ID sizes read from QEMU ACPI tables.
>
> Pad OEM_ID/OEM_T
On Mon, Jan 10, 2022 at 06:29:10PM -0500, John Snow wrote:
> This is the last vestige of the "aqmp" moniker surviving in the tree; remove
> it.
>
> Signed-off-by: John Snow
> ---
> python/qemu/qmp/{aqmp_tui.py => qmp_tui.py} | 12 ++--
> python/setup.cfg| 6
On Mon, Jan 10, 2022 at 06:28:55PM -0500, John Snow wrote:
> Signed-off-by: John Snow
> Reviewed-by: Vladimir Sementsov-Ogievskiy
> Reviewed-by: Beraldo Leal
> ---
> python/README.rst | 2 +-
> python/qemu/{qmp => aqmp}/qmp_shell.py | 0
> python/setup.cfg
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
docs/system/ppc/pseries.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/system/ppc/pseries.rst b/docs/system/ppc/pseries.rst
index ead33e6764..1120b21d95 100644
--- a/docs/system/ppc/pseries.rst
+++ b/docs/sys
Anup Patel 於 2021年12月30日 週四 下午9:03寫道：
> From: Anup Patel
>
> We have two new machine options "aia" and "aia-guests" available
> for the RISC-V virt machine so let's document these options.
>
> Signed-off-by: Anup Patel
> Signed-off-by: Anup Patel
> Reviewed-by: Alistair Francis
> ---
> docs/
On Mon, Jan 10, 2022 at 06:28:54PM -0500, John Snow wrote:
> In order to upload a QMP package to PyPI, I want to remove any scripts
> that I am not 100% confident I want to support upstream, beyond our
> castle walls.
>
> Move most of our QMP utilities into the utils package so we can split
> them
On Wed, Jan 12, 2022 at 6:57 PM Graeme Gregory
wrote:
>
> On Tue, Jan 11, 2022 at 04:45:44PM +0800, Troy Lee wrote:
> > This series of patch introduce a dummy implemenation of aspeed i3c
> > model, and it provide just enough information for guest machine.
> > However, the driver probing is still f
On Mon, Jan 10, 2022 at 06:28:49PM -0500, John Snow wrote:
> This is in preparation for renaming qemu.aqmp to qemu.qmp. I should have
> done this from this from the very beginning, but it's a convenient time
> to make sure this churn is taken care of.
s/this from this from/this from/
--
Beraldo
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
---
docs/specs/{ppc-spapr-hotplug.txt => ppc-spapr-hotplug.rst} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename docs/specs/{ppc-spapr-hotplug.txt => ppc-spapr-hotplug.rst} (100%)
diff --git a/docs/specs/ppc-spapr-hotplug.txt b/d
On Wed, 12 Jan 2022 at 13:53, Liviu Ionescu wrote:
> >> -rw-r--r-- 1 ilg staff 67108864 Jan 7 14:52 edk2-aarch64-code.fd
> >> -rw-r--r-- 1 ilg staff 67108864 Jan 7 14:52 edk2-arm-code.fd
> >> -rw-r--r-- 1 ilg staff 67108864 Jan 7 14:52 edk2-arm-vars.fd
>
> These are the top 3 larges
101 - 200 of 329 matches
Mail list logo
