Hi
On Wed, Dec 29, 2021 at 6:18 AM Rao Lei wrote:
> The GDB statck is as follows:
> (gdb) bt
> 0 __lll_lock_wait (futex=futex@entry=0x56211df20360, private=0) at
> lowlevellock.c:52
> 1 0x7f263caf20a3 in __GI___pthread_mutex_lock (mutex=0x56211df20360)
> at ../nptl/pthread_mutex_lock.c:80
Hi,
> +#ifdef DEBUG_CANOKEY
> +#define DPRINTF(fmt, ...) \
> +do { printf("canokey: " fmt "\n", ## __VA_ARGS__); } while (0)
Better use tracepoints instead (see docs/devel/tracing.rst).
> +int canokey_emu_transmit(
> +void *base, uint8_t ep, const uint8_t *pbuf, uint16_t size)
> +{
> +
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a couple of pnv-phb3 and pnv-phb3-root-port fixes that
were also applied for the pnv4 equivalents.
During the enablement I had to rollback
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
When creating a pnv_phb3_root_port using the command line, the first
root port is created successfully, but the second fails with the
following error:
qemu-system-ppc64: -device pnv-phb3-root-port,bus=phb3-root.0,id=pcie.3:
Can't add chassis slot
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
All pnv-phb3-root-bus buses are being created as 'root-bus'. This
makes it impossible to, for example, add a pnv-phb3-root-port in
a specific root bus, since they all have the same name. By default
the device will be parented by the pnv-phb3 devic
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
All pnv-phb3-root-bus buses are being created as 'root-bus'. This
makes it impossible to, for example, add a pnv-phb3-root-port in
a specific root bus, since they all have the same name. By default
the device will be parented by the pnv-phb3 devic
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controllers are named based on their bus
type (e.g. pS
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
The root port 'chassis' and 'slot' attributes are being set in the
realize() callback of phb3_root_port and phb4_root_port.
Remove the unneeded 'chassis' and 'slot' setting from
pnv_phb_attach_root_port().
You should simply resend a modified ve
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
We're adding the default pnv_phb4_root_port in
pnv_chip_power9_pec_realize() by going into each stack, from eack pec,
each
accessing the stack PHB and adding the port.
This will be an annoyance when trying to implement user creatable PHB4
dev
On 12/28/21 20:38, Daniel Henrique Barboza wrote:
This change has the same motivation as the one done for pnv-phb3-root-bus
buses previously. Defaulting every bus to 'root-bus' makes it impossible to
attach
root ports to specific buses and it doesn't allow for custom bus
naming because we're ign
ARM64 machines like Kunpeng Family Server Chips have a level
of hardware topology in which a group of CPU cores share L3
cache tag or L2 cache. For example, Kunpeng 920 typically
has 6 or 8 clusters in each NUMA node (also represent range
of CPU die), and each cluster has 4 CPU cores. All clusters
This v6 series enables the support for CPU cluster topology on
ARM virt machines. The generic infrastructure for CPU cluster
parameter now is in upstream.
Background and descriptions:
The new Cluster-Aware Scheduling support has landed in Linux 5.16,
which has been proved to benefit the scheduling
We have a generic build_pptt() in hw/acpi/aml-build.c but it's
currently only used in ARM acpi initialization. Now we are going
to support the new CPU cluster parameter which is currently only
supported by ARM, it won't be a very good idea to add it to the
generic build_pptt() as it will make the c
Currently we generate a PPTT table of n-level processor hierarchy
with n-level loops in build_pptt(). It works fine as now there are
only three CPU topology parameters. But the code may become less
scalable with the processor hierarchy levels increasing.
This patch only improves the scalability of
Support one cluster level between core and physical package in the
cpu-map of Arm/virt devicetree. This is also consistent with Linux
Doc "Documentation/devicetree/bindings/cpu/cpu-topology.txt".
Signed-off-by: Yanan Wang
---
hw/arm/virt.c | 15 ---
1 file changed, 8 insertions(+), 7
Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180810 (64-bit version
List test/data/acpi/virt/PPTT as the expected files allowed to
be changed in tests/qtest/bios-tables-test-allowed-diff.h
Signed-off-by: Yanan Wang
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/te
Support cluster level in generation of ACPI Processor Properties
Topology Table (PPTT) for ARM virt machines.
Signed-off-by: Yanan Wang
---
hw/arm/virt-acpi-build.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 3ce7
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
pnv_phb4_rc_config_read() and pnv_phb4_rc_config_write() are asserting
the existence of the root port. The root port is now optional, and there
will be cases where a pnv-phb4 device won't have a root port attached.
May be we should enforce a str
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
The logic inside pnv_pec_phb_offset() wiil be useful in the next patch
will
to determine the stack that should contain a PHB4 device.
Move the function to pnv_phb4.c and make it public since there's no
pnv_phb4_pec.h header. While we're at it
Ubuntu GCC enables -fcf-protection globally, which is not supported
for x86 16-bit (realmode). This causes the build to fail.
This commit turns off that option.
Signed-off-by: Björn Töpel
---
pc-bios/optionrom/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/pc-bios/optionrom/Makefi
On 12/28/21 20:38, Daniel Henrique Barboza wrote:
Relying on stack->phb to write the xscom DT of the PEC is something that
we won't be able to do with user creatable pnv-phb4 devices.
Hopefully, this can be done by using pnv_pec_get_phb_id(), which is
already used by pnv_pec_realize() to set the
The rest ARM & ACPI part (patches 8-14) have been packed into v6:
v6: https://patchew.org/QEMU/20220103084636.2496-1-wangyana...@huawei.com/
Thanks,
Yanan
On 2021/12/28 17:22, Yanan Wang wrote:
Hi,
This series introduces the new CPU clusters topology parameter
and enable the support for it on
Add docs/specs/sev-guest-firmware.rst which describes the GUIDed table
in the end of OVMF's image which is parsed by QEMU, and currently used
to describe some values for SEV and SEV-ES guests.
Signed-off-by: Dov Murik
---
docs/specs/index.rst | 1 +
docs/specs/sev-guest-firmware.r
On 2021/12/31 20:11, Philippe Mathieu-Daudé wrote:
On 12/31/21 08:30, wangyanan (Y) wrote:
Hi,
On 2021/12/30 6:52, Philippe Mathieu-Daudé wrote:
qdev_get_gpio_out_connector() is called by sysbus_get_connected_irq()
which is only used by platform-bus.c; restrict it to hw/core/ by
adding a loc
Hi Raphael,
Thanks for your reply.
I will fix the grammar mistake in V2.
-Original Message-
From: Raphael Norwitz
Sent: Tuesday, November 30, 2021 5:58 AM
To: Pei, Andy
Cc: qemu-devel@nongnu.org; qemu-bl...@nongnu.org; Liu, Changpeng
; Raphael Norwitz ;
m...@redhat.com; kw...@redhat.
Turn on pre-defined feature VIRTIO_BLK_F_SIZE_MAX for virtio blk device to
avoid guest DMA request sizes which are too large for hardware spec.
Signed-off-by: Andy Pei
---
hw/block/vhost-user-blk.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-use
On 24.12.21 16:04, Vladimir Sementsov-Ogievskiy wrote:
09.07.2021 15:50, Kevin Wolf wrote:
From: Max Reitz
We do not do any permission checks in fuse_open(), so let the kernel do
them. We already let fuse_getattr() report the proper UNIX permissions,
so this should work the way we want.
This
On 31/12/2021 08:31, Cédric Le Goater wrote:
For Radix translation, the EA range is 64-bits. when EA(2:11) are
nonzero, a segment interrupt should occur.
Signed-off-by: Cédric Le Goater
---
Looks ok to me.
Reviewed-by: Frederic Barrat
Fred
target/ppc/mmu-radix64.h | 1 +
target/
On 27/12/2021 11.01, Igor Mammedov wrote:
On Wed, 22 Dec 2021 16:39:23 +0100
Thomas Huth wrote:
The user might have disabled the pc-i440fx machine type (or it's older
versions, like done in downstream RHEL) in the QEMU binary, so let's
better check whether the machine types are available befor
> /*
> * When an IOMMU is present, bus addresses become distinct from
> * CPU/memory physical addresses and may be a different size. Because
> @@ -39,9 +28,22 @@ struct QEMUSGList {
> * least most) cases.
> */
> typedef uint64_t dma_addr_t;
> +typedef uint64_t dma_size_t;
This is a bi
On Mon, Jan 03, 2022 at 05:28:12PM +0800, Andy Pei wrote:
> Turn on pre-defined feature VIRTIO_BLK_F_SIZE_MAX for virtio blk device to
> avoid guest DMA request sizes which are too large for hardware spec.
>
> Signed-off-by: Andy Pei
> ---
Thanks!
Notes for future submissions:
- pls include ac
On 1/3/22 03:48, Cédric Le Goater wrote:
On 12/30/21 23:12, Daniel Henrique Barboza wrote:
On 12/23/21 18:19, Richard Henderson wrote:
On 12/23/21 12:36 PM, Daniel Henrique Barboza wrote:
This reorg is breaking PMU-EBB tests, unfortunately. These tests are run from
the kernel
tree [1] an
On Mon, Jan 03, 2022 at 04:46:32PM +0800, Yanan Wang wrote:
> Currently we generate a PPTT table of n-level processor hierarchy
> with n-level loops in build_pptt(). It works fine as now there are
> only three CPU topology parameters. But the code may become less
> scalable with the processor hiera
On Mon, Jan 03, 2022 at 04:46:30PM +0800, Yanan Wang wrote:
> ARM64 machines like Kunpeng Family Server Chips have a level
> of hardware topology in which a group of CPU cores share L3
> cache tag or L2 cache. For example, Kunpeng 920 typically
> has 6 or 8 clusters in each NUMA node (also represen
On Mon, Jan 03, 2022 at 04:46:31PM +0800, Yanan Wang wrote:
> Support one cluster level between core and physical package in the
> cpu-map of Arm/virt devicetree. This is also consistent with Linux
> Doc "Documentation/devicetree/bindings/cpu/cpu-topology.txt".
>
> Signed-off-by: Yanan Wang
> ---
On Mon, Jan 03, 2022 at 04:46:33PM +0800, Yanan Wang wrote:
> We have a generic build_pptt() in hw/acpi/aml-build.c but it's
> currently only used in ARM acpi initialization. Now we are going
> to support the new CPU cluster parameter which is currently only
> supported by ARM, it won't be a very g
On Mon, Jan 03, 2022 at 04:46:35PM +0800, Yanan Wang wrote:
> Support cluster level in generation of ACPI Processor Properties
> Topology Table (PPTT) for ARM virt machines.
>
> Signed-off-by: Yanan Wang
> ---
> hw/arm/virt-acpi-build.c | 15 +++
> 1 file changed, 15 insertions(+)
>
Minor change to make fullscreen mode in the Cocoa UI a little more
convenient.
The menu bar is now made visible when the mouse is released (ungrabbed)
making it accessible without having to leave fullscreen mode. Grabbing
the mouse hides the menu.
Carwyn Ellis (1):
ui/cocoa: show/hide menu in f
The menu bar is only accessible when the Cocoa UI is windowed. In order
to allow the menu bar to be accessible in fullscreen mode, this change
makes the menu visible when the mouse is ungrabbed.
When the mouse is grabbed the menu is hidden again.
Signed-off-by: Carwyn Ellis
---
ui/cocoa.m | 8 +
On Mon, 3 Jan 2022, Yanan Wang wrote:
> List test/data/acpi/virt/PPTT as the expected files allowed to
> be changed in tests/qtest/bios-tables-test-allowed-diff.h
>
> Signed-off-by: Yanan Wang
Acked-by: Ani Sinha
> ---
> tests/qtest/bios-tables-test-allowed-diff.h | 1 +
> 1 file changed,
Thank you Frank for that extra confirmation,
by now also all the blockers on the other bug fixed are good. I expect this to
be released as soon as the SRU Team is back from the Christmas shutdown.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscrib
With CAP_DAC_OVERRIDE (which e.g. root generally has), permission checks
will be bypassed when opening files.
308 in one instance tries to open a read-only file (FUSE export) with
qemu-io as read/write, and expects this to fail. However, when running
it as root, opening will succeed (thanks to CA
On Mon, 3 Jan 2022, Yanan Wang wrote:
> Run ./tests/data/acpi/rebuild-expected-aml.sh from build directory
> to update PPTT binary. Also empty bios-tables-test-allowed-diff.h.
>
> The disassembled differences between actual and expected PPTT:
>
> /*
> * Intel ACPI Component Architecture
>
ping
https://lore.kernel.org/qemu-devel/20211229064421.5LPUBTk_b7lwFSu6jdh7beB7kZHoVtGGztQSJR1SClI@z/
Hi Marc,
On Tue, Dec 28, 2021 at 06:23:47PM +, Marc Zyngier wrote:
> Add basic support for Pointer Authentication when running a KVM
> guest and that the host supports it, loosely based on the SVE
> support.
>
> Although the feature is enabled by default when the host advertises
> it, it is p
Daniel Henrique Barboza writes:
> On 12/23/21 00:01, Richard Henderson wrote:
>> In contrast to Daniel's version, the code stays in power8-pmu.c,
>> but is better organized to not take so much overhead.
>> Before:
>> 32.97% qemu-system-ppc qemu-system-ppc64 [.] pmc_get_event
>> 20
On 02/01/2022 17:06, Konrad Schwarz wrote:
GDB target descriptions support typed registers;
such that `info register X' displays not only the hex value of
register `X', but also the individual bitfields the register
comprises (if any), using textual labels if possible.
This patch includes typ
On 23.12.21 18:50, Vladimir Sementsov-Ogievskiy wrote:
23.12.2021 19:53, Hanna Reitz wrote:
This test assumes that mirror flushes the source when entering the READY
state, and that the format level will pass that flush on to the protocol
level (where we intercept it with blkdebug).
However, app
On 30.12.21 17:00, Vladimir Sementsov-Ogievskiy wrote:
22.12.2021 14:41, Hanna Reitz wrote:
We want to add a --daemonize argument to QSD's command line. This will
require forking the process before we do any complex initialization
steps, like setting up the block layer or QMP. Therefore, we mu
From: Matheus Ferst
In the review of 66c6b40aba1, Richard Henderson suggested[1] using
"trap" instead of ".long 0x0" to generate the signal to test XER
save/restore behavior. However, linux-user aborts when a trap
exception is raised, so we kept the patch with SIGILL.
This patch series is a foll
From: Matheus Ferst
Now that linux-user delivers the signal on tw, we can change
signal_save_restore_xer to use SIGTRAP instead of SIGILL.
Suggested-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64le/signal_save_restore_xer.c | 8
1 file changed, 4 insertions(+)
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
linux-user/ppc/cpu_loop.c | 4 +++-
1 file changed, 3 insertions(+), 1 dele
On 1/2/22 10:34 PM, Cédric Le Goater wrote:
The compiler should know better how to inline code if necessary.
Suggested-by: Richard Henderson
Signed-off-by: Cédric Le Goater
---
target/ppc/excp_helper.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Richard H
On 1/2/22 10:34 PM, Cédric Le Goater wrote:
There is no need to deactivate MMU logging at compile time. Remove all
use of defines. Only keep DUMP_PAGE_TABLES for another series since
page tables could be dumped from the monitor.
Signed-off-by: Cédric Le Goater
Message-Id:<20211222064025.1541490-
Ping Laurent. Any suggestions for the follow-up questions?
On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
>
> On Thu, Dec 23, 2021 at 1:03 PM Laurent Vivier wrote:
> >
> > Le 23/12/2021 à 07:47, Tonis Tiigi a écrit :
> >
> > Please copy here what you explain in PATCH 0 regarding this patch.
On 30.12.21 17:12, Vladimir Sementsov-Ogievskiy wrote:
22.12.2021 14:41, Hanna Reitz wrote:
This option does basically the same as --fork does for qemu-nbd:
Can we share the code?
Before this patch we already have --fork code-path of qemu-nbd and
-daemonize code-path of QEMU.. Now we have on
Fixes the build on a mips64 host. Prior to the break, we identified
the arch via the __mips__ define; afterward we use meson's
host_machine.cpu_family(). Restore the previous combination.
Fixes: 823eb013452e ("configure, meson: move ARCH to meson.build")
Reported-by: Philippe Mathieu-Daudé
Sign
The cross-i386-tci test has timeouts because we're no longer
applying the timeout that we desired. Hack around it.
Reviewed-by: Philippe Mathieu-Daudé
Fixes: 23a77b2d18b8 ("build-system: clean up TCG/TCI configury")
Signed-off-by: Richard Henderson
---
tests/tcg/Makefile.target | 12 +-
The following changes since commit 69f153667fce723ee546d2f047d66d0cfa67c3cc:
Merge tag 'memory-api-20211231' of https://github.com/philmd/qemu into
staging (2021-12-30 17:02:42 -0800)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-misc-202
Set this test to be manually run, until failures can be fixed.
Signed-off-by: Richard Henderson
---
.gitlab-ci.d/static_checks.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitlab-ci.d/static_checks.yml b/.gitlab-ci.d/static_checks.yml
index 902843f8b3..5e955540d3 100644
--- a/.gitl
The parallel version of STBY did not take host endianness into
account, and also computed the incorrect address for STBY_E.
Bswap twice to handle the merge and store. Compute mask inside
the function rather than as a parameter. Force align the address,
rather than subtracting one.
Generalize th
Use $cpu instead of $ARCH, which has been removed from
the top-level configure.
Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Philippe Mathieu-Daudé
Fixes: 823eb013452e ("configure, meson: move ARCH to meson.build")
Signed-off-by: Richard Henderson
---
configure | 2 +-
tests/tcg
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signed-off-by: Matheus Ferst
---
linux-user/ppc/c
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Now that linux-user delivers the signal on tw, we can change
signal_save_restore_xer to use SIGTRAP instead of SIGILL.
Suggested-by: Richard Henderson
Signed-off-by: Matheus Ferst
---
tests/tcg/ppc64le/signal_save_res
Add basic support for Pointer Authentication when running a KVM
guest and that the host supports it, loosely based on the SVE
support.
Although the feature is enabled by default when the host advertises
it, it is possible to disable it by setting the 'pauth=off' CPU
property. The 'pauth' comment i
Hi Andrew,
On Mon, 03 Jan 2022 13:46:01 +,
Andrew Jones wrote:
>
> Hi Marc,
>
> On Tue, Dec 28, 2021 at 06:23:47PM +, Marc Zyngier wrote:
> > Add basic support for Pointer Authentication when running a KVM
> > guest and that the host supports it, loosely based on the SVE
> > support.
>
On 1/3/22 12:07, Alex Bennée wrote:
Daniel Henrique Barboza writes:
On 12/23/21 00:01, Richard Henderson wrote:
In contrast to Daniel's version, the code stays in power8-pmu.c,
but is better organized to not take so much overhead.
Before:
32.97% qemu-system-ppc qemu-system-ppc64
On 03/01/2022 14:50, Richard Henderson wrote:
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel source file
arch/powerpc/kernel/traps.c
Signe
On 1/3/22 03:46, Cédric Le Goater wrote:
On 12/23/21 21:18, Daniel Henrique Barboza wrote:
Hi,
In this version the tedious repetition was taken away from the
code by using a helper that increments the PMCs based on specified
conditions.
As far as Avocado test goes, the performance is the sa
On 1/3/22 10:12 AM, Matheus K. Ferst wrote:
On 03/01/2022 14:50, Richard Henderson wrote:
On 1/3/22 8:56 AM, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Handle POWERPC_EXCP_TRAP in cpu_loop to deliver SIGTRAP on tw[i]/td[i].
The si_code comes from do_program_check in the kernel s
Le 03/01/2022 à 18:07, Tõnis Tiigi a écrit :
Ping Laurent. Any suggestions for the follow-up questions?
On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
On Thu, Dec 23, 2021 at 1:03 PM Laurent Vivier wrote:
Le 23/12/2021 à 07:47, Tonis Tiigi a écrit :
Please copy here what you explain i
Hi,
This is the v2 of Richard's work sent in [1]. The initial implementation
presented some issues with the event-based branch kernel tests that I
fixed in this new version. This code is now passing all EBB PPC64
tests, it makes Avocado happy and it's all contained in the C helper.
Last patch is
From: Richard Henderson
Use the cached pmc_ins_cnt value. Unroll the loop over the
different PMC counters. Treat the PMC4 run-latch specially.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 78 ++---
1 file changed, 49 insertions(+), 29 del
From: Richard Henderson
Use the cached pmc_cyc_cnt value in pmu_update_cycles
and pmc_update_overflow_timer. This leaves pmc_get_event
and pmc_is_inactive unused, so remove them.
Signed-off-by: Richard Henderson
---
target/ppc/power8-pmu.c | 107
1 fil
From: Richard Henderson
This is the combination of frozen bit and counter type, on a per
counter basis. So far this is only used by HFLAGS_INSN_CNT, but
will be used more later.
Signed-off-by: Richard Henderson
[danielhb: fixed PMC4 cyc_cnt shift and insn run latch code]
Signed-off-by: Daniel H
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for what we need to do.
pmu_update_summaries() is already u
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case was
covered in the late pmc_get_event(), via the also gone pmc_is_inactive(),
that would return an
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a couple of pnv-phb3 and pnv-phb3-root-port fixes that
were also applied for the pnv4 equivale
On 1/3/22 05:28, Cédric Le Goater wrote:
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
The TYPE_PNV_PHB3_ROOT_BUS name is used as the default bus name when
the dev has no 'id'. However, pnv-phb3-root-bus is a bit too long to be
used as a bus name.
Most common QEMU buses and PCI controlle
On Mon, Jan 3, 2022 at 10:37 AM Laurent Vivier wrote:
>
> Le 03/01/2022 à 18:07, Tõnis Tiigi a écrit :
> > Ping Laurent. Any suggestions for the follow-up questions?
> >
> > On Thu, Dec 23, 2021 at 3:00 PM Tõnis Tiigi wrote:
> >>
> >> On Thu, Dec 23, 2021 at 1:03 PM Laurent Vivier wrote:
> >>>
>
On 2/1/22 22:58, Patrick Venture wrote:
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/npcm7xx_boards.c | 9 +
1 file changed, 9 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé
Hi!
"make html" and "make man" do not work anymore:
$ make help | grep -B1 html
Documentation targets:
html man - Build documentation in specified format
$ make html
GIT ui/keycodemapdb meson tests/fp/berkeley-testfloat-3
tests/fp/berkeley-softfloat-3 dtc capstone slirp
FreeBSD: Upgrade to 12.3 release
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
---
.gitlab-ci.d/cirrus.yml | 5 +
tests/vm/freebsd| 8 +++-
2 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/.gitlab-ci.d/cirrus.yml b/.gitlab-ci.d/cirrus.yml
index d273a9e713..18ded
On 21/12/2021 07.58, marcandre.lur...@redhat.com wrote:
From: Marc-André Lureau
Add a new dbus-doc directive to import D-Bus interfaces documentation
from the introspection XML. The comments annotations follow the
gtkdoc/kerneldoc style, and should be formatted with reST.
Note: I realize after
On 3/1/22 21:45, Brad Smith wrote:
FreeBSD: Upgrade to 12.3 release
Maybe some mention like:
'''
Note, since libasn1 got fixed in 12.3 [*], this commit re-enables GNUTLS.
[*]
https://gitlab.com/gnutls/libtasn1/-/merge_requests/71
'''
Signed-off-by: Brad Smith
Tested-by: Thomas Huth
---
On Mon, Jan 3, 2022 at 1:47 PM Brad Smith wrote:
> FreeBSD: Upgrade to 12.3 release
>
> Signed-off-by: Brad Smith
> Tested-by: Thomas Huth
> ---
> .gitlab-ci.d/cirrus.yml | 5 +
> tests/vm/freebsd| 8 +++-
> 2 files changed, 4 insertions(+), 9 deletions(-)
>
Reviewed-by: Warne
On Mon, Jan 3, 2022 at 1:57 PM Philippe Mathieu-Daudé
wrote:
> On 3/1/22 21:45, Brad Smith wrote:
> > FreeBSD: Upgrade to 12.3 release
>
> Maybe some mention like:
>
> '''
> Note, since libasn1 got fixed in 12.3 [*], this commit re-enables GNUTLS.
>
> [*]
> https://gitlab.com/gnutls/libtasn1/-/me
gitlab.com/rth7680/qemu.git tags/pull-misc-20220103
for you to fetch changes up to 5c23f0c3191907000bab278654570a7d5879822a:
gitlab: Disable check-python-tox (2022-01-03 08:55:55 -0800)
Fix some meson conversion breakage
Dis
On 1/3/22 19:58, Daniel Henrique Barboza wrote:
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a couple of pnv-phb3 and pnv-phb3-root-port fi
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
+/* Composite status for PMC[1-5] enabled and counting insns or cycles. */
+uint8_t pmc_ins_cnt;
+uint8_t pmc_cyc_cnt;
I should have updated the comment to 1-6 when I added cyc_cnt.
+sel = extract64(mmcr1, MMCR1_PMC4EVT_EX
On 1/3/22 18:20, Cédric Le Goater wrote:
On 1/3/22 19:58, Daniel Henrique Barboza wrote:
On 1/3/22 05:21, Cédric Le Goater wrote:
Hello Daniel,
On 12/28/21 20:37, Daniel Henrique Barboza wrote:
Hi,
This series implements pnv-phb4 user devices for the powernv9 machine.
It also includes a
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case was
covered in the late pmc_get_event(), via t
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
MMCR0 writes will change only MMCR0 bits which are used to calculate
HFLAGS_PMCC0, HFLAGS_PMCC1 and HFLAGS_INSN_CNT hflags. No other machine
register will be changed during this operation. This means that
hreg_compute_hflags() is overkill for wha
On 1/3/22 18:38, Richard Henderson wrote:
On 1/3/22 10:53 AM, Daniel Henrique Barboza wrote:
pmu_update_summaries() is not considering the case where the PMU can be
turned off (i.e. stop counting all events) if MMCR0_FC is set,
regardless of the other frozen counter bits state. This use case
These are the follow up cleanups from the RFC that touch the top level
of powerpc_excp. Applies on top of the 1/n series.
Patches 1-2: extract software TLB debug into a function;
Patch 3: group the "unimplemented" messages;
Patches 4-8: move ILE code into a separate function and put ILE and
The ppc_interrupts_little_endian function is suitable for determining
the endianness of interrupts for all Book3S CPUs.
(I'm keeping the MSR check for the rest of the CPUs, but it will go
away in the next patch.)
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 21 ++-
The ppc_interrupts_little_endian function could be used for interrupts
delivered in Hypervisor mode, so add support for powernv8 and powernv9
to it.
Also drop the comment because it is inaccurate, all CPUs that can run
little endian can have interrupts in little endian. The point is
whether they c
Remove the compile time definition and make the logging be controlled
by the `-d mmu` option in the cmdline.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_he
AIL only applies for Book3s CPUs, so move it along with ILE. This
moves ILE further down in the file because the AIL function can alter
vector so we cannot move it up.
Signed-off-by: Fabiano Rosas
---
target/ppc/excp_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deleti
1 - 100 of 164 matches
Mail list logo
