Re: QEMU CAS

Thank you for the great response pointing out many details we have missed! The fixed constraints solved the optimization problem. I am going to see what I can do about the other issues, it will take a while. Best regards On 23/12/2021 20:24, Richard Henderson wrote: On 12/23/21 1:51 AM, Ja

Re: [PATCH] Add service recovery options for QGA on windows

Hi, On Mon, Nov 15, 2021 at 4:30 AM wrote: > From: shenjiatong > > Add default recovery options for QGA on windows. Previously, QGA > on windows will not try to restart service if it is down. This PS > add some default options for the first, second and other failures, > with an interval of 1min

why tx_queue_size must be 256 for non-vhost-user tap nic

Hi, all: I tried to test the effort of nic queue's ring-size, but nic' tx vring-size is always 256. finally i found the code. could you tell why ? thanks - n->net_conf.tx_queue_size = MIN(virtio_net_max_tx_queue_size(n), n->net_conf.tx_queue_size);

[PATCH v6 00/23] QEMU RISC-V AIA support

From: Anup Patel The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: https://github.com/riscv/riscv-aia/re

[PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode

From: Anup Patel We should be returning illegal instruction trap when RV64 HS-mode tries to access RV32 HS-mode CSR. Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions") Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Bin M

[PATCH v6 06/23] target/riscv: Add AIA cpu feature

From: Anup Patel We define a CPU feature for AIA CSR support in RISC-V CPUs which can be set by machine/device emulation. The RISC-V CSR emulation will also check this feature for emulating AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Alista

[PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities

From: Anup Patel The AIA spec defines programmable 8-bit priority for each local interrupt at M-level, S-level and VS-level so we extend local interrupt processing to consider AIA interrupt priorities. The AIA CSRs which help software configure local interrupt priorities will be added by subseque

[PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs

From: Anup Patel The hgeie and hgeip CSRs are required for emulating an external interrupt controller capable of injecting virtual external interrupt to Guest/VM running at VS-level. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c

[PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs

From: Anup Patel A hypervisor can optionally take guest external interrupts using SGEIP bit of hip and hie CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 3 ++- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c |

[PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs

From: Anup Patel The AIA hvictl and hviprioX CSRs allow hypervisor to control interrupts visible at VS-level. This patch implements AIA hvictl and hviprioX CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv

[PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs

From: Anup Patel The AIA specification introduces new [m|s|vs]topi CSRs for reporting pending local IRQ number and associated IRQ priority. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c | 156 + 1 file changed, 156 inser

[PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts

From: Anup Patel The guest external interrupts from an interrupt controller are delivered only when the Guest/VM is running (i.e. V=1). This means any guest external interrupt which is triggered while the Guest/VM is not running (i.e. V=0) will be missed on QEMU resulting in Guest with sluggish r

[PATCH v6 07/23] target/riscv: Add defines for AIA CSRs

From: Anup Patel The RISC-V AIA specification extends RISC-V local interrupts and introduces new CSRs. This patch adds defines for the new AIA CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 127 +++

[PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs

From: Anup Patel The AIA specification defines [m|s|vs]iselect and [m|s|vs]ireg CSRs which allow indirect access to interrupt priority arrays and per-HART IMSIC registers. This patch implements AIA xiselect and xireg CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/c

[PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs

From: Anup Patel The AIA specification defines IMSIC interface CSRs for easy access to the per-HART IMSIC registers without using indirect xiselect and xireg CSRs. This patch implements the AIA IMSIC interface CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel --- target/riscv/csr.c |

[PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation

From: Anup Patel The machine or device emulation should be able to force set certain CPU features because: 1) We can have certain CPU features which are in-general optional but implemented by RISC-V CPUs on the machine. 2) We can have devices which require a certain CPU feature. For example,

[PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32

From: Anup Patel The AIA specification adds new CSRs for RV32 so that RISC-V hart can support 64 local interrupts on both RV32 and RV64. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 14 +- target/riscv/cpu_helper.c | 10 +

[PATCH v6 18/23] hw/intc: Add RISC-V AIA APLIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for wired interrupts called APLIC (Advanced Platform Level Interrupt Controller). The APLIC is capabable of forwarding wired interupts to RISC-V HARTs directly or as MSIs (Message Signaled Interup

[PATCH v6 19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine

From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=aplic" parameter is passed along with machine name in QEMU command-line. When "aia=none" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signed-off-by: Anup Patel

[PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs

From: Anup Patel The AIA specificaiton adds interrupt filtering support for M-mode and HS-mode. Using AIA interrupt filtering M-mode and H-mode can take local interrupt 13 or above and selectively inject same local interrupt to lower privilege modes. At the moment, we don't have any local interr

[PATCH v6 17/23] target/riscv: Allow users to force enable AIA CSRs in HART

From: Anup Patel We add "x-aia" command-line option for RISC-V HART using which allows users to force enable CPU AIA CSRs without changing the interrupt controller available in RISC-V machine. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/

[PATCH v6 16/23] hw/riscv: virt: Use AIA INTC compatible string when available

From: Anup Patel We should use the AIA INTC compatible string in the CPU INTC DT nodes when the CPUs support AIA feature. This will allow Linux INTC driver to use AIA local interrupt CSRs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- hw/riscv/virt.c |

[PATCH v6 21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine

From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=aplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts

[PATCH v6 22/23] docs/system: riscv: Document AIA options for virt machine

From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- docs/system/riscv/virt.rst | 16 1 file change

[PATCH v6 20/23] hw/intc: Add RISC-V AIA IMSIC device emulation

From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level gue

[PATCH v6 23/23] hw/riscv: virt: Increase maximum number of allowed CPUs

From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anu

[PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback

From: Anup Patel The AIA device emulation (such as AIA IMSIC) should be able to set (or provide) AIA ireg read-modify-write callback for each privilege level of a RISC-V HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 23

[PATCH v3 5/7] target/riscv: rvk: add CSR support for Zkr

- add SEED CSR - add USEED, SSEED fields for MSECCFG CSR Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- target/riscv/cpu_bits.h | 9 + target/riscv/csr.c | 73 + target/riscv/pmp.h | 8 +++-- 3 files changed, 87 insertions(+

[PATCH v3 7/7] target/riscv: rvk: expose zbk* and zk* properties

Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 961c5f4334..6575ec8cfa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -668,6 +668,19 @@ static

[PATCH v3 0/7] support subsets of scalar crypto extension

This patchset implements RISC-V K-extension v1.0.0.rc6 version instructions. Partial instructions are reused from B-extension. Specification: https://github.com/riscv/riscv-crypto The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-k-upstream-v3 To test rvk implementation

[PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*

Signed-off-by: liweiwei Signed-off-by: wangjunqiang Acked-by: Alistair Francis --- target/riscv/cpu.c | 23 +++ target/riscv/cpu.h | 13 + 2 files changed, 36 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..961c5f4334 100644

[PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

- share it between target/arm and target/riscv Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- crypto/meson.build | 1 + crypto/sm4.c | 48 ++ include/crypto/sm4.h | 6 + meson | 2 +- target/

[PATCH v3 2/7] target/riscv: rvk: add implementation of instructions for Zbk*

- reuse partial instructions of Zbb/Zbc extensions - add brev8, packh, unzip, zip, etc. Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- target/riscv/bitmanip_helper.c | 74 ++ target/riscv/helper.h | 5 + target/riscv/insn32.decode

[PATCH v3 6/7] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions

Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- disas/riscv.c | 171 +- 1 file changed, 170 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index 793ad14c27..eb1d36d1e5 100644 --- a/disas/riscv.c +++ b/disas/riscv.c

[PATCH v3 4/7] target/riscv: rvk: add implementation of instructions for Zk*

Signed-off-by: liweiwei Signed-off-by: wangjunqiang --- target/riscv/crypto_helper.c| 446 ++ target/riscv/helper.h | 43 +++ target/riscv/insn32.decode | 42 +++ target/riscv/insn_trans/trans_rvk.c.inc | 467 ++

Re: [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

Hi, On 12/30/21 15:30, liweiwei wrote: >- share it between target/arm and target/riscv "Share sm4_sbox between ARM and RISCV targets."? > > Signed-off-by: liweiwei > Signed-off-by: wangjunqiang > --- > crypto/meson.build | 1 + > crypto/sm4.c | 48 +

[PATCH] MAINTAINERS: Change philmd's email address

The phi...@redhat.com email address will stop working on 2022-01-01, change it to my personal email address. Update .mailmap in case anyone wants to send me an email because of some past commit I authored. Signed-off-by: Philippe Mathieu-Daudé --- .gitlab-ci.d/edk2/Dockerfile | 2 +- .mailmap

Re: [PATCH v3 3/7] crypto include/crypto target/arm: move sm4_sbox to crypto

Thanks for your review. 在 2021/12/30 下午10:46, Philippe Mathieu-Daudé 写道: Hi, On 12/30/21 15:30, liweiwei wrote: - share it between target/arm and target/riscv "Share sm4_sbox between ARM and RISCV targets."? Yes. sm4 related instruction in scalar crypto extension will use sm4_sbox. Sign

Re: [PATCH] gitlab-ci: Always upload artifacts by default

On 12/30/21 00:33, Philippe Mathieu-Daudé wrote: > GitLab defaults [1] to upload artifacts only when the job succeeds, > which is not helpful to troubleshoot failing tests. Switch to > always upload artifacts by default for QEMU jobs, by setting the > 'artifacts:when' keyword in the global default

Re: [PATCH v3 2/8] migration: Don't return for postcopy_chunk_hostpages()

On 12/24/21 07:49, Peter Xu wrote: > It always return zero, because it just can't go wrong so far. Simplify the > code with no functional change. > > Reviewed-by: Dr. David Alan Gilbert > Signed-off-by: Peter Xu > --- > migration/ram.c | 11 ++- > 1 file changed, 2 insertions(+), 9 del

Re: [PATCH v3 1/8] migration: Drop dead code of ram_debug_dump_bitmap()

On 12/24/21 07:49, Peter Xu wrote: > I planned to add "#ifdef DEBUG_POSTCOPY" around the function too because > otherwise it'll be compiled into qemu binary even if it'll never be used. > Then > I found that maybe it's easier to just drop it for good.. > > Reviewed-by: Dr. David Alan Gilbert >

Re: [PATCH v3 7/8] migration: Finer grained tracepoints for POSTCOPY_LISTEN

On 12/24/21 07:49, Peter Xu wrote: > The enablement of postcopy listening has a few steps, add a few tracepoints to > be there ready for some basic measurements for them. > > Signed-off-by: Peter Xu > --- > migration/savevm.c | 9 - > migration/trace-events | 2 +- > 2 files changed,

Re: [PATCH v3 8/8] migration: Tracepoint change in postcopy-run bottom half

On 12/24/21 07:50, Peter Xu wrote: > Remove the old two tracepoints and they're even near each other: > > trace_loadvm_postcopy_handle_run_cpu_sync() > trace_loadvm_postcopy_handle_run_vmstart() > > Add trace_loadvm_postcopy_handle_run_bh() with a finer granule trace. > > Signed-off-by:

Re: [PATCH v3 6/8] migration: Dump sub-cmd name in loadvm_process_command tp

On 12/24/21 07:49, Peter Xu wrote: > It'll be easier to read the name rather than index of sub-cmd when debugging. > > Signed-off-by: Peter Xu > --- > migration/savevm.c | 3 ++- > migration/trace-events | 2 +- > 2 files changed, 3 insertions(+), 2 deletions(-) > diff --git a/migration/tra

Re: [PATCH 1/3] qsd: Add pre-init argument parsing pass

22.12.2021 14:41, Hanna Reitz wrote: We want to add a --daemonize argument to QSD's command line. This will require forking the process before we do any complex initialization steps, like setting up the block layer or QMP. Therefore, we must scan the command line for it long before our current

Re: [PATCH v3 5/8] migration: Drop return code for disgard ram process

On 12/24/21 07:49, Peter Xu wrote: > It will just never fail. Drop those return values where they're constantly > zeros. > > A tiny touch-up on the tracepoint so trace_ram_postcopy_send_discard_bitmap() > is called after the logic itself (which sounds more reasonable). > > Reviewed-by: Dr. David

Re: [PATCH v2 00/23] hw: Have DMA APIs take MemTxAttrs arg & propagate MemTxResult (full)

On 12/23/21 12:55, Philippe Mathieu-Daudé wrote: > Hi Peter and Paolo. > > This series contains all the uncontroversary patches from > the "improve DMA situations, avoid re-entrancy issues" > earlier series. The rest will be discussed on top. > > The only operations added are: > - take MemTxAttrs

[PATCH] migration: Don't return for postcopy_send_discard_bm_ram()

postcopy_send_discard_bm_ram() always return zero. Since it can't fail, simplify and do not return anything. Signed-off-by: Philippe Mathieu-Daudé --- Based-on: <20211224065000.97572-1-pet...@redhat.com> --- migration/ram.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a

Re: [PATCH 2/3] qsd: Add --daemonize

22.12.2021 14:41, Hanna Reitz wrote: This option does basically the same as --fork does for qemu-nbd: Can we share the code? Before this patch we already have --fork code-path of qemu-nbd and -daemonize code-path of QEMU.. Now we have one more. Did you consider improving and sharing the old

Re: [PATCH v10 2/3] cpu-throttle: implement virtual CPU throttle

在 2021/12/24 13:12, Peter Xu 写道: On Tue, Dec 14, 2021 at 07:07:33PM +0800, huang...@chinatelecom.cn wrote: From: Hyman Huang(黄勇) Setup a negative feedback system when vCPU thread handling KVM_EXIT_DIRTY_RING_FULL exit by introducing throttle_us_per_full field in struct CPUState. Sleep throt

Re: [PATCH] MAINTAINERS: Change philmd's email address

On 12/30/21 6:58 AM, Philippe Mathieu-Daudé wrote: thephi...@redhat.com email address will stop working on 2022-01-01, change it to my personal email address. Update .mailmap in case anyone wants to send me an email because of some past commit I authored. Signed-off-by: Philippe Mathieu-Daudé

Re: [PATCH] MAINTAINERS: Change philmd's email address

On 12/30/21 6:58 AM, Philippe Mathieu-Daudé wrote: +Philippe Mathieu-Daudé Actually, it looks like the mailmap is backward. r~

Re: [PATCH v2 2/5] target/ppc: powerpc_excp: Add excp_vectors bounds check

On 12/29/21 8:57 AM, Fabiano Rosas wrote: The next patch will start accessing the excp_vectors array earlier in the function, so add a bounds check as first thing here. This converts the empty return on POWERPC_EXCP_NONE to an error. This exception number never reaches this function and if it do

Re: [PATCH v2 3/5] target/ppc: powerpc_excp: Set vector earlier

On 12/29/21 8:57 AM, Fabiano Rosas wrote: None of the interrupt setup code touches 'vector', so we can move it earlier in the function. This will allow us to later move the System Call Vectored setup that is on the top level into the POWERPC_EXCP_SYSCALL_VECTORED code block. This patch also move

Re: [PATCH 0/3] Reorg ppc64 pmu insn counting

On 12/23/21 18:19, Richard Henderson wrote: On 12/23/21 12:36 PM, Daniel Henrique Barboza wrote: This reorg is breaking PMU-EBB tests, unfortunately. These tests are run from the kernel tree [1] and I test them inside a pSeries TCG guest. You'll need to apply patches 9 and 10 of [2] beforeh

Re: [PATCH 1/4] acpi: fix QEMU crash when started with SLIC table

В Пн, 27/12/2021 в 14:31 -0500, Igor Mammedov пишет: > if QEMU is started with used provided SLIC table blob, > >   -acpitable sig=SLIC,oem_id='CRASH > ',oem_table_id="ME",oem_rev=2210,asl_compiler_id="",asl_compiler_re > v=,data=/dev/null > it will assert with: > >   hw/acpi/aml-buil

Re: [PATCH] MAINTAINERS: Change philmd's email address

On 12/30/21 23:00, Richard Henderson wrote: > On 12/30/21 6:58 AM, Philippe Mathieu-Daudé wrote: >> +Philippe Mathieu-Daudé  > > Actually, it looks like the mailmap is backward. Doh of course >_< Thanks for catching it.

[PATCH] tests/tcg: Unconditionally use 90 second timeout

The cross-i386-tci test has timeouts because we're no longer actually applying the timeout that we desired. Hack around it. Fixes: 23a77b2d18b8 ("build-system: clean up TCG/TCI configury") Signed-off-by: Richard Henderson --- tests/tcg/Makefile.target | 12 +--- 1 file changed, 5 insert

Re: [PATCH v2 14/23] dma: Let dma_buf_read() / dma_buf_write() propagate MemTxResult

On 12/23/21 12:55, Philippe Mathieu-Daudé wrote: > Since the previous commit, dma_buf_rw() returns a MemTxResult > type. Do not discard it, return it to the caller. > > Since both dma_buf_read/dma_buf_write functions were previously > returning the QEMUSGList size not consumed, add an extra argume

Re: [PATCH v2 00/23] hw: Have DMA APIs take MemTxAttrs arg & propagate MemTxResult (full)

On 12/30/21 17:07, Philippe Mathieu-Daudé wrote: > On 12/23/21 12:55, Philippe Mathieu-Daudé wrote: >> Hi Peter and Paolo. >> >> This series contains all the uncontroversary patches from >> the "improve DMA situations, avoid re-entrancy issues" >> earlier series. The rest will be discussed on top.

Re: [PATCH] tests/tcg: Unconditionally use 90 second timeout

On 12/31/21 00:54, Richard Henderson wrote: > The cross-i386-tci test has timeouts because we're no longer > actually applying the timeout that we desired. Hack around it. > > Fixes: 23a77b2d18b8 ("build-system: clean up TCG/TCI configury") > Signed-off-by: Richard Henderson > --- > tests/tcg/M

[PATCH v2] MAINTAINERS: Change philmd's email address

The phi...@redhat.com email address will stop working on 2022-01-01, change it to my personal email address. Update .mailmap in case anyone wants to send me an email because of some past commit I authored. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- v2: Fixed .mailm

[PULL 07/22] dma: Let dma_memory_map() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_memory_map(). Patch created mechanically using spatch with this script: @@ expression E1, E2, E3, E4; @@ - dma_memory_map(E1, E2, E3, E4) + dma_memory_map(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) Reviewed-by: Richard Henderson

[PULL 00/22] Memory API patches for 2021-12-31

The following changes since commit d5a9f352896fe43183ef01072b374e89a3488315: Merge tag 'pull-jobs-2021-12-29' of https://src.openvz.org/scm/~vsementsov/qemu into staging (2021-12-29 14:33:23 -0800) are available in the Git repository at: https://github.com/philmd/qemu.git tags/memory-api-2

[PULL 01/22] hw/scsi/megasas: Use uint32_t for reply queue head/tail values

While the reply queue values fit in 16-bit, they are accessed as 32-bit: 661:s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa); 662:s->reply_queue_head %= MEGASAS_MAX_FRAMES; 663:s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa); 664:s->reply_queue_tail %=

[PULL 02/22] dma: Let dma_memory_valid() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_memory_valid(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé Acked-by: Stefan Hajnoczi Message-Id: <20211223115554.3155328-2-phi...@redhat.com> --- include

[PULL 03/22] dma: Let dma_memory_set() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_memory_set(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé Acked-by: Stefan Hajnoczi Message-Id: <20211223115554.3155328-3-phi...@redhat.com> --- include/h

[PULL 04/22] dma: Let dma_memory_rw_relaxed() take MemTxAttrs argument

We will add the MemTxAttrs argument to dma_memory_rw() in the next commit. Since dma_memory_rw_relaxed() is only used by dma_memory_rw(), modify it first in a separate commit to keep the next commit easier to review. Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Igle

[PULL 08/22] dma: Have dma_buf_rw() take a void pointer

DMA operations are run on any kind of buffer, not arrays of uint8_t. Convert dma_buf_rw() to take a void pointer argument to save us pointless casts to uint8_t *. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-8-phi...@redhat.com> --- softmmu

[PULL 14/22] dma: Let dma_buf_rw() propagate MemTxResult

dma_memory_rw() returns a MemTxResult type. Do not discard it, return it to the caller. Since dma_buf_rw() was previously returning the QEMUSGList size not consumed, add an extra argument where this size can be stored. Update the 2 callers. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Math

[PULL 05/22] dma: Let dma_memory_rw() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_memory_rw(). Reviewed-by: Richard Henderson Reviewed-by: Li Qiang Reviewed-by: Edgar E. Iglesias Signed-off-by: Philippe Mathieu-Daudé Acked-by: Stefan Hajnoczi Message-Id: <20211223115554.3155328-5-phi...@redhat.com> --- include/hw

[PULL 12/22] dma: Let dma_buf_write() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_buf_write(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-12-phi...@redhat.com> --- include/sysemu/dma.h | 2 +- hw/id

[PULL 10/22] pci: Let pci_dma_rw() take MemTxAttrs argument

Let devices specify transaction attributes when calling pci_dma_rw(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-10-phi...@redhat.com> --- include/hw/pci/pci.h | 10 ++

[PULL 15/22] dma: Let st*_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling st*_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-16-phi...@redhat.com> --- inclu

[PULL 13/22] dma: Let dma_buf_read() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_buf_read(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-13-phi...@redhat.com> --- include/sysemu/dma.h | 2 +- hw/id

[PULL 11/22] dma: Let dma_buf_rw() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_buf_rw(). Keep the default MEMTXATTRS_UNSPECIFIED in the 2 callers. Reviewed-by: Klaus Jensen Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-11-phi...@redhat.com> --- softmmu/dma-helpers.c | 11 ++-

[PULL 21/22] pci: Let st*_pci_dma() propagate MemTxResult

st*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-23-phi...@redhat.com> --- include/hw/pci/pci.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions

[PULL 06/22] dma: Let dma_memory_read/write() take MemTxAttrs argument

Let devices specify transaction attributes when calling dma_memory_read() or dma_memory_write(). Patch created mechanically using spatch with this script: @@ expression E1, E2, E3, E4; @@ ( - dma_memory_read(E1, E2, E3, E4) + dma_memory_read(E1, E2, E3, E4, MEMTXATTRS_UNSPECIFIED) |

[PULL 16/22] dma: Let ld*_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling ld*_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-17-phi...@redhat.com> --- inclu

[PULL 22/22] pci: Let ld*_pci_dma() propagate MemTxResult

ld*_dma() returns a MemTxResult type. Do not discard it, return it to the caller. Update the few callers. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-24-phi...@redhat.com> --- include/hw/pci/pci.h | 17 - hw/audio/int

[PULL 09/22] dma: Have dma_buf_read() / dma_buf_write() take a void pointer

DMA operations are run on any kind of buffer, not arrays of uint8_t. Convert dma_buf_read/dma_buf_write functions to take a void pointer argument and save us pointless casts to uint8_t *. Remove this pointless casts in the megasas device model. Reviewed-by: Klaus Jensen Signed-off-by: Philippe M

[PULL 17/22] dma: Let st*_dma() propagate MemTxResult

dma_memory_write() returns a MemTxResult type. Do not discard it, return it to the caller. Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-18-phi...@redhat.com> --- include/sysemu/dma.h | 20 ++--

[PULL 18/22] dma: Let ld*_dma() propagate MemTxResult

dma_memory_read() returns a MemTxResult type. Do not discard it, return it to the caller. Update the few callers. Reviewed-by: Richard Henderson Reviewed-by: Cédric Le Goater Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-19-phi...@redhat.com> --- include/hw/pci/pci

[PULL 19/22] pci: Let st*_pci_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling st*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-21-phi...@redhat.com> --- include/hw/pci/pci.h | 11 ++

[PULL 20/22] pci: Let ld*_pci_dma() take MemTxAttrs argument

Let devices specify transaction attributes when calling ld*_pci_dma(). Keep the default MEMTXATTRS_UNSPECIFIED in the few callers. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20211223115554.3155328-22-phi...@redhat.com> --- include/hw/pci/pci.h | 6 +++---

Re: [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*

On Thu, Dec 30, 2021 at 10:32 PM liweiwei wrote: > > Signed-off-by: liweiwei > Signed-off-by: wangjunqiang nits: looks like the best practice of the name is: Weiwei Li and Junqiang Wang > Acked-by: Alistair Francis > --- > target/riscv/cpu.c | 23 +++ > target/riscv/cpu.

Re: [PATCH v3 kvm/queue 05/16] KVM: Maintain ofs_tree for fast memslot lookup by file offset

On Tue, Dec 28, 2021 at 09:48:08PM +, Sean Christopherson wrote: > On Fri, Dec 24, 2021, Chao Peng wrote: > > On Thu, Dec 23, 2021 at 06:02:33PM +, Sean Christopherson wrote: > > > On Thu, Dec 23, 2021, Chao Peng wrote: > > > > > > In other words, there needs to be a 1:1 gfn:file+offset ma

Re: [PATCH v3 1/7] target/riscv: rvk: add cfg properties for zbk* and zk*

在 2021/12/31 上午10:04, Bin Meng 写道: On Thu, Dec 30, 2021 at 10:32 PM liweiwei wrote: Signed-off-by: liweiwei Signed-off-by: wangjunqiang nits: looks like the best practice of the name is: Weiwei Li and Junqiang Wang Thanks for your comment.  I'll update this later. Acked-by: Alistair Fr

Re: [PATCH v3 kvm/queue 11/16] KVM: Add kvm_map_gfn_range

On Fri, Dec 24, 2021 at 12:13:51PM +0800, Chao Peng wrote: > On Thu, Dec 23, 2021 at 06:06:19PM +, Sean Christopherson wrote: > > On Thu, Dec 23, 2021, Chao Peng wrote: > > > This new function establishes the mapping in KVM page tables for a > > > given gfn range. It can be used in the memory f

Re: [PATCH v3 kvm/queue 03/16] mm/memfd: Introduce MEMFD_OPS

On Fri, Dec 24, 2021 at 11:53:15AM +0800, Robert Hoo wrote: > On Thu, 2021-12-23 at 20:29 +0800, Chao Peng wrote: > > From: "Kirill A. Shutemov" > > > > +static void notify_fallocate(struct inode *inode, pgoff_t start, > > pgoff_t end) > > +{ > > +#ifdef CONFIG_MEMFD_OPS > > + struct shmem_ino

Re: [PATCH v3 kvm/queue 04/16] KVM: Extend the memslot to support fd-based private memory

On Thu, Dec 23, 2021 at 05:35:37PM +, Sean Christopherson wrote: > On Thu, Dec 23, 2021, Chao Peng wrote: > > > + struct file *file; > > Please use more descriptive names, shaving characters is not at all priority. > > > + u64 ofs; > > I believe this should be loff_t. > > struct

[PATCH v2 3/6] target/riscv: add support for zfinx

From: liweiwei - update extension check REQUIRE_ZFINX_OR_F - update single float point register read/write - disable nanbox_s check Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/fpu_helper.c | 89 +++ target/riscv/helpe

[PATCH v2 1/6] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}

From: liweiwei Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 12 target/riscv/cpu.h | 4 target/riscv/translate.c | 8 3 files changed, 24 insertions(+) diff --git

[PATCH v2 0/6] support subsets of Float-Point in Integer Registers extensions

This patchset implements RISC-V Float-Point in Integer Registers extensions(Version 1.0.0-rc), which includes Zfinx, Zdinx, Zhinx and Zhinxmin extension. Specification: https://github.com/riscv/riscv-zfinx/blob/main/zfinx-1.0.0-rc.pdf The port is available here: https://github.com/plctlab/plct

[PATCH v2 2/6] target/riscv: hardwire mstatus.FS to zero when enable zfinx

From: liweiwei Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.c| 4 target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c| 24 +++- target/riscv/translate.c | 5 + 4 files changed, 33 insert

[PATCH v2 5/6] target/riscv: add support for zhinx/zhinxmin

From: liweiwei - update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN - update half float point register read/write - disable nanbox_h check Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/fpu_helper.c | 89 +

[PATCH v2 6/6] target/riscv: expose zfinx, zdinx, zhinx{min} properties

From: liweiwei Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc7da446f1..3dd07759e1 100644 --- a/target/r

[PATCH v2 4/6] target/riscv: add support for zdinx

From: liweiwei -- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvd.c.inc | 319 ++-- target/riscv/translate.c

Re: [PATCH v8 0/7] Add vmnet.framework based network backend

ping https://patchew.org/QEMU/20211211104413.50524-1-yaroshchuk2...@gmail.com/ сб, 11 дек. 2021 г. в 13:44, Vladislav Yaroshchuk : > macOS provides networking API for VMs called 'vmnet.framework': > https://developer.apple.com/documentation/vmnet > > We can provide its support as the new QEMU ne

[PATCH] MAINTAINERS: email address change

Fujitsu's mail service has migrated to O365 months ago, the lizhij...@cn.fujitsu.com address will stop working on 2022-06-01, change it to my new email address lizhij...@fujitsu.com. Signed-off-by: Li Zhijian --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAI

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