On Thu, Dec 16, 2021 at 5:31 AM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> 15.12.2021 22:39, John Snow wrote:
> > Signed-off-by: John Snow
>
> Not simple to check, how much new behavior is equal to the old one.. And
> impossible to check, is everything updated that should b
Cc'ing qemu-arm developers.
On 12/16/21 18:31, abhijeet inamdar wrote:
> Hi,
>
> I was running my .elf file on my custom machine(CM3) and was hit with
> this error when debugging and had the required -d flags and single stepping.
>
> IN: Hal_MemFault
> 0x7004e794: 4770 bx lr
>
> Tr
On Thu, Dec 16, 2021 at 5:52 AM Vladimir Sementsov-Ogievskiy <
vsement...@virtuozzo.com> wrote:
> 15.12.2021 22:39, John Snow wrote:
> > Remove the QEMU_PYTHON_LEGACY_QMP environment variable, making the
> > switch permanent. Update Exceptions and import paths as necessary.
> >
> > Signed-off-by:
On 12/16/21 13:21, Richard Henderson wrote:
On 12/15/21 11:02 PM, Cédric Le Goater wrote:
Fails testing:
/home/gitlab-runner/builds/yKcZqVC9/0/qemu-project/qemu/docs/specs/ppc-spapr-hcalls.rst:101:Block
quote ends without a blank line; unexpected unindent.
I didn't see it under :
https:/
dma_buf_read/dma_buf_write() return a MemTxResult type.
Do not discard it, propagate the DMA error to the caller.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/nvme/ctrl.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index fa410a179a6.
Now that the DMA API allow passing MemTxAttrs argument and
returning MemTxResult (with MEMTX_BUS_ERROR in particular),
we can restrict the NVMe controller to memories (prohibitting
accesses by the DMA engine to devices) and block yet another
DMA re-entrancy attack.
I'll will try to get a reproduce
Async DMA requests might access MMIO regions and re-program the
NVMe controller internal registers while DMA requests are still
scheduled or in flight. Avoid that by prohibing the controller
to access non-memories regions.
The bug has been audited looking at the following report from
Qiuhao Li:
16.12.2021 20:22, John Snow wrote:
On Thu, Dec 16, 2021 at 4:51 AM Vladimir Sementsov-Ogievskiy mailto:vsement...@virtuozzo.com>> wrote:
15.12.2021 22:39, John Snow wrote:
> This exception can be injected into any await statement. If we are
> canceled via timeout, we want to clea
On Thu, Dec 16, 2021 at 06:55:09PM +0100, Philippe Mathieu-Daudé wrote:
> dma_buf_read/dma_buf_write() return a MemTxResult type.
> Do not discard it, propagate the DMA error to the caller.
>
> Signed-off-by: Philippe Mathieu-Daudé
Looks good.
Reviewed-by: Keith Busch
On Thu, Dec 16, 2021 at 06:55:10PM +0100, Philippe Mathieu-Daudé wrote:
> Async DMA requests might access MMIO regions and re-program the
> NVMe controller internal registers while DMA requests are still
> scheduled or in flight. Avoid that by prohibing the controller
> to access non-memories regio
On 12/16/21 9:51 AM, Cédric Le Goater wrote:
It's certainly due to
[PULL 017/102] docs: rSTify ppc-spapr-hcalls.txt
However, it does not reproduce on f34 and 21.10 systems using python-sphinx
3.4.3-2 and 3.5.4-2
Correct, it's a system running 18.04.5 LTS, python3-sphinx 1.6.7.
https://git
On 12/15/21 12:25 PM, Paolo Bonzini wrote:
The following changes since commit 50456a6794fbb8dc94a31eb9534e91c586da7add:
Merge tag 'pull-ppc-20211129' of https://github.com/legoater/qemu into
staging (2021-11-29 21:56:06 +0100)
are available in the Git repository at:
https://gitlab.com/b
On Thu, Dec 16, 2021 at 6:55 PM Philippe Mathieu-Daudé
wrote:
>
> Fixes: CVE-2021-3929
RHBZ: https://bugzilla.redhat.com/show_bug.cgi?id=2020298
> Reported-by: Qiuhao Li
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/nvme/ctrl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>
On 12/16/21 16:51, Jon Maloy wrote:
> On 12/16/21 04:36, Philippe Mathieu-Daudé wrote:
>> Hi Jon,
>>
>> On 10/21/21 18:10, Jon Maloy wrote:
>>> The fact that the MMIO handler is not re-entrant causes an infinite
>>> loop under certain conditions:
>>>
>>> Guest write to TDT -> Loopback -> RX (DMA t
On 12/16/21 15:11, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>
>> When experimenting raising GLIB_VERSION_MIN_REQUIRED to 2.68
>> (Fedora 34 provides GLib 2.68.1) we get:
>>
>> hw/virtio/virtio-crypto.c:245:24: error: 'g_memdup' is deprecated: Use
>> 'g_memdup2' instead [-Werror,-Wde
On 24.11.21 07:44, Emanuele Giuseppe Esposito wrote:
Signed-off-by: Emanuele Giuseppe Esposito
Reviewed-by: Stefan Hajnoczi
---
block.c| 18 ++
block/create.c | 10 ++
2 files changed, 28 insertions(+)
[...]
diff --git a/block/create.c b/block/create.c
in
On Thu, 16 Dec 2021 at 17:44, Philippe Mathieu-Daudé wrote:
>
> Cc'ing qemu-arm developers.
>
> On 12/16/21 18:31, abhijeet inamdar wrote:
> > Hi,
> >
> > I was running my .elf file on my custom machine(CM3) and was hit with
> > this error when debugging and had the required -d flags and single st
On 211216 1935, Philippe Mathieu-Daudé wrote:
> On 12/16/21 16:51, Jon Maloy wrote:
> > On 12/16/21 04:36, Philippe Mathieu-Daudé wrote:
> >> Hi Jon,
> >>
> >> On 10/21/21 18:10, Jon Maloy wrote:
> >>> The fact that the MMIO handler is not re-entrant causes an infinite
> >>> loop under certain cond
On Dec 16 18:55, Philippe Mathieu-Daudé wrote:
> Now that the DMA API allow passing MemTxAttrs argument and
> returning MemTxResult (with MEMTX_BUS_ERROR in particular),
> we can restrict the NVMe controller to memories (prohibitting
> accesses by the DMA engine to devices) and block yet another
>
On 12/16/21 19:18, Richard Henderson wrote:
On 12/16/21 9:51 AM, Cédric Le Goater wrote:
It's certainly due to
[PULL 017/102] docs: rSTify ppc-spapr-hcalls.txt
However, it does not reproduce on f34 and 21.10 systems using python-sphinx
3.4.3-2 and 3.5.4-2
Correct, it's a system running 18
could you drop this patch for now?
Can we address that as a followup in v7.0 ? We have time for it and I would
also prefer not to resend such a large PR.
I need to resend, so I will drop that patch in v2.
Thanks,
C.
On Dec 16 13:35, Philippe Mathieu-Daudé wrote:
> This is the continuation of part 1 (dma_memory API):
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg820359.html
>
> This series update the dma_buf API.
>
> Based on "hw: Let the DMA API take a MemTxAttrs argument"
> Based-on: <202107020924
On Dec 16 20:13, Klaus Jensen wrote:
> On Dec 16 18:55, Philippe Mathieu-Daudé wrote:
> > Now that the DMA API allow passing MemTxAttrs argument and
> > returning MemTxResult (with MEMTX_BUS_ERROR in particular),
> > we can restrict the NVMe controller to memories (prohibitting
> > accesses by the
This was the one I received.
///jon
On 12/16/21 14:01, Alexander Bulekov wrote:
On 211216 1935, Philippe Mathieu-Daudé wrote:
On 12/16/21 16:51, Jon Maloy wrote:
On 12/16/21 04:36, Philippe Mathieu-Daudé wrote:
Hi Jon,
On 10/21/21 18:10, Jon Maloy wrote:
The fact that the MMIO handler is
On Thu, 16 Dec 2021 at 20:07, abhijeet inamdar
wrote:
>
> If I won't make that change it gives me immediate error as follows:
>
> Taking exception 18 [v7M INVSTATE UsageFault]
> ...BusFault with BFSR.STKERR
> ...taking pending nonsecure exception 3
> qemu: fatal: Lockup: can't take terminal derive
From: "Lucas Mateus Castro (alqotel)"
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruct
From: Daniel Henrique Barboza
This test, if enabled by hand, was failing when the ivhsmem device was
being declared as DEVICE_NATIVE_ENDIAN with the following error:
/ppc64/ivshmem/pair: OK
/ppc64/ivshmem/server:
**
ERROR:/home/danielhb/qemu/tests/qtest/ivshmem-test.c:367:test_ivshmem_server:
as
The following changes since commit 76b56fdfc9fa43ec6e5986aee33f108c6c6a511e:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2021-12-14 12:46:18 -0800)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-ppc-2021121
From: Daniel Henrique Barboza
The ivshmem device, as with most PCI devices, uses little endian byte
order. However, the endianness of its mmio_ops is marked as
DEVICE_NATIVE_ENDIAN. This presents not only the usual problems with big
endian hosts but also with PowerPC little endian hosts as well,
From: Alexey Kardashevskiy
This has really just one fix from Stefan, the rest is housekeeping.
The full changelog is:
Alexey Kardashevskiy (3):
Revert "make: Define default rule for .c when V=1 or V=2"
js2x: Fix compile and cleanup
version: update to 2022
Stefan Berger (1
From: "Lucas Mateus Castro (alqotel)"
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27
From: "Lucas Mateus Castro (alqotel)"
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Reviewed-by: Richard Henderson
Signed-off-by: Lucas Mateus Castro (alqotel)
Message-Id: <20211201163808.440385-3-lucas.ara...@eldorado.org.b
From: Richard Henderson
Now that vxisi and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-9-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 38
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
[ clg: replaced Power9 by POWER9 ]
Message-Id:
Signed-off-by: Cédric Le Goater
---
docs/system/ppc/powernv.rst | 55 +++--
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/docs/system/ppc/powe
From: Peter Maydell
The mac.h header defines a MAX_CPUS macro. This is confusingly named,
because it suggests it's a generic setting, but in fact it's used
by only the g3beige and mac99 machines. It's also using a single
macro for two values which aren't inherently the same -- if one
of these two
From: Daniel Henrique Barboza
If one tries to use -machine powernv9,accel=kvm in a Power9 host, a
cryptic error will be shown:
qemu-system-ppc64: Register sync failed... If you're using kvm-hv.ko, only
"-cpu host" is possible
qemu-system-ppc64: kvm_init_vcpu: kvm_arch_init_vcpu failed (0): Inva
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-7-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-par
From: Christophe Lombard
The PCIe extended configuration space on the device is not currently
accessible to the host. if by default, it is still inaccessible for
conventional for PCIe buses, add the current flag
PCI_BUS_EXTENDED_CONFIG_SPACE on the root bus permits PCI-E extended
config space ac
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
mtvsrbm: Move to VSR Byte Mask
mtvsrhm: Move to VSR Halfword Mask
mtvsrwm: Move to VSR Word Mask
mtvsrdm: Move to VSR Doubleword Mask
mtvsrqm: Move to VSR Quadword Mask
mtvsrbmi: Move to VSR Byte Mask Immediate
Reviewed-by:
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
[ clg: - replaced lingua by terminology
- add a new line at EOF ]
Message-Id:
Signed-off-by: Cédric Le Goater
---
docs/specs/ppc-spapr-hcalls.txt | 92 -
1 file c
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vextractbm: Vector Extract Byte Mask
vextracthm: Vector Extract Halfword Mask
vextractwm: Vector Extract Word Mask
vextractdm: Vector Extract Doubleword Mask
vextractqm: Vector Extract Quadword Mask
Signed-off-by: Matheus Fe
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<7d3c8bad1ca76eb13d6ce2b16dd9a821edcdb27b.1638982486.git.lagar...@br.ibm.com>
Signed-off-by: Cédric Le Goater
---
docs/system/ppc/pseries.rst | 2 +-
1 file changed, 1 insertion(+), 1 deleti
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-8-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat.c
From: Richard Henderson
In GEN_FLOAT_B, we called helper_reset_fpstatus immediately
before calling helper_fri*. Therefore get_float_exception_flags
is known to be zero, and this code can be simplified.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-17-richard.hender...@lina
From: Daniel Henrique Barboza
Put in a more accessible place the reasoning behind our decision
to officially drop KVM support in the powernv machine.
Signed-off-by: Daniel Henrique Barboza
Message-Id: <20211130133153.444601-3-danielhb...@gmail.com>
Signed-off-by: Cédric Le Goater
---
docs/sys
From: Richard Henderson
We will process flags other than in valid in helper_float_check_status,
which is invoked after the writeback to FRT.
Fixes a bug in which FRT is not written when OE/UE/XE are enabled.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-21-richard.hender...
From: Matheus Ferst
Implement the following PowerISA v3.1 instructions:
vexpandbm: Vector Expand Byte Mask
vexpandhm: Vector Expand Halfword Mask
vexpandwm: Vector Expand Word Mask
vexpanddm: Vector Expand Doubleword Mask
vexpandqm: Vector Expand Quadword Mask
Reviewed-by: Richard Henderson
Sig
From: Richard Henderson
There's no reason the callers can't tail call to one function.
Leave it up to the compiler either way.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-15-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
From: Leonardo Garcia
Signed-off-by: Leonardo Garcia
Reviewed-by: Daniel Henrique Barboza
Message-Id:
<7f13e40e05ddb411697b0777b0e37757f76905e9.1638982486.git.lagar...@br.ibm.com>
Signed-off-by: Cédric Le Goater
---
docs/specs/{ppc-spapr-hcalls.txt => ppc-spapr-hcalls.rst} | 0
1 file change
From: Daniel Henrique Barboza
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens
From: Richard Henderson
PowerPC has these flags, and it's easier to compute them here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-5-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 2 ++
fpu/softfloa
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-6-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-part
From: Richard Henderson
Use float64r32_muladd. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-29-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/p
From: Richard Henderson
Now that vximz and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-10-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 26
From: Richard Henderson
This is the proper type for the enumeration.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-16-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 2 +-
1 file changed, 1 i
From: Richard Henderson
We will shortly have more than 8 bits of exceptions.
Repack the existing flags into low bits and reformat to hex.
Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <2029160502.17432-2-richard.hender...@linaro.org>
Signed-off-by: Cédric
They have been there since 2007 without any board using them, most
were protected by a TODO define. Drop support.
Signed-off-by: Cédric Le Goater
Reviewed-by: Richard Henderson
Reviewed-by: David Gibson
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211202191108.1291515-1-...@kaod.org>
Si
From: Richard Henderson
Use float64r32_mul. Fixes a double-rounding issue with performing
the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-32-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-4-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-pa
From: Richard Henderson
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-13-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 20 ++
and one error message to a LOG_GUEST_ERROR.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 159 +++-
hw/ppc/trace-events | 20 ++
2 files changed, 74 inser
From: Richard Henderson
These variants take a float64 as input, compute the result to
infinite precision (as we do with FloatParts), round the result
to the precision and dynamic range of float32, and then return
the result in the format of float64.
This is the operation PowerPC requires for its
From: Richard Henderson
Let float64_round_to_int detect and silence snans.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-18-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 24 +++-
1 file changed, 11 insertio
From: Fabiano Rosas
The 603e uses the same exception code as 603 so we don't need a
dedicated entry for it.
This is only a removal of redundant code, no functional change.
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: Cédric Le Goater
Message-Id: <20211208123029.20
From: Leonardo Garcia
The purpose of this document is to substitute the content currently
available in the QEMU wiki at [0]. This initial version does contain
some additional content as well. Whenever this documentation gets
upstream and is reflected in [1], the QEMU wiki will be edited to point
From: Richard Henderson
PowerPC has this flag, and it's easier to compute it here
than after the fact.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-3-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
include/fpu/softfloat-types.h | 1 +
fpu/softfloat-part
From: Thomas Huth
The PPC 405 CPU is a system-on-a-chip, so all 405 machines are very similar,
except for some external periphery. However, the periphery of the 'taihu'
machine is hardly emulated at all (e.g. neither the LCD nor the USB part had
been implemented), so there is not much value added
From: Richard Henderson
Create a common function for all of the madd helpers.
Let the compiler tail call or inline as it chooses.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-20-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 3
It was introduced in commit b8d3f5d12642 ("Add flags to support
PowerPC 405 bootinfos variations.") but since its value has always
been set to '1'.
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-6-...@kaod.org>
Signed-off-by: Cédric Le Goa
From: Richard Henderson
Now that vximz, vxisi, and vxsnan are computed directly by
softfloat, we don't need to recompute it. This replaces the
separate float{32,64}_maddsub_update_excp functions with a
single float_invalid_op_madd function.
Fix VSX_MADD by passing sfprf to float_invalid_op_madd
The machine can already boot with kernel and initrd U-boot images if a
firmware is loaded first. Adapt and improve the load sequence to let
the machine boot directly from a Linux kernel ELF image and a usual
initrd image if a firmware image is not provided. For that, install a
custom CPU reset hand
I will be useful to rework the boot from Linux.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-7-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 2 +-
hw/ppc/ppc405_boards.c | 6 +-
hw/ppc/ppc405_uc.c | 4 ++--
3 files changed, 8 insertion
From: Richard Henderson
Use float_flag_invalid_snan instead of recomputing
the snan-ness of the operand.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-26-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 15 +--
1 file
Adapt the fields offset in the board information for Linux. Since
Linux relies on the CPU frequency value, I wonder how it ever worked.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-15-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 9 +
1 fi
From: Richard Henderson
Now that vxidi, vxzdz, and vxsnan are computed directly by
softfloat, we don't need to recompute it via classes.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-11-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helpe
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-8-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405.h| 7 +++
hw/ppc/ppc405_boards.c | 16 +++-
2 files changed, 14 insertions(+), 9 deletions(-)
diff
Signed-off-by: Cédric Le Goater
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211206103712.1866296-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc.c| 2 ++
hw/ppc/trace-events | 3 +++
2 files changed, 5 insertions(+)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index e
From: Fabiano Rosas
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disa
From: Richard Henderson
Fixes a bug in which e.g XE enabled causes inexact to be raised
before the writeback to the architectural register.
All of the users of GEN_FLOAT_B either set set_fprf, or are one
of the convert-to-integer instructions that require this behaviour.
Split out the two gen_he
From: Daniel Henrique Barboza
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x8000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being
This routine is a small helper to cleanup the code. The update of the
flash fields were removed because there are not of any use when booting
from a Linux kernel image. It should be functionally equivalent.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-11-...@kaod.org>
Signe
From: Richard Henderson
We only needed one ieee arithmetic operation to raise
exceptions. To convert back to register form, we can
use our simpler non-arithmetic function.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-24-richard.hender...@linaro.org>
Signed-off-by: Cédric
The default addresses to load the kernel, fdt, initrd of AMCC boards
in U-Boot v2015.10 are :
"kernel_addr_r=100\0"
"fdt_addr_r=180\0"
"ramdisk_addr_r=190\0"
The taihu is one of these boards, the ref405ep is not but we don't
have much information on it and both
From: Richard Henderson
When computing the predicate "is this value currently formatted
for single precision", we do not want to round the value according
to the current rounding mode, nor perform a floating-point equality.
We want to see if the N bits that make up single-precision are the
only o
From: Richard Henderson
Use float64r32_{add,sub,div}. Fixes a double-rounding issue with
performing the compuation in float64 and then rounding afterward.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-31-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
t
The maximum number of PHB3 devices per chip can be different depending
on the POWER8 processor model.
Signed-off-by: Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza
Message-Id: <20211213132830.108372-4-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb3.c | 2 +-
1 fil
These values are computed and updated by U-Boot at startup. Use them
as defaults to improve direct Linux boot.
Signed-off-by: Cédric Le Goater
Message-Id: <20211206103712.1866296-13-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/ppc405_uc.c | 6 +++---
1 file changed, 3 insertions(+),
From: Daniel Henrique Barboza
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occur
From: Richard Henderson
We were returning nanval for any instance of invalid being set,
but that is an incorrect for VXCVI. This failure can be seen
in the float_convs tests.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-14-richard.hender...@linaro.org>
Signed-off-by: Cédr
From: Fabiano Rosas
The Floating-point Unavailable and Decrementer interrupts are being
registered at the same 0x900 address. The FPU should be at 0x800
instead.
Verified on MPC555, MPC860 and MPC885 user manuals.
Reported-by: BALATON Zoltan
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard H
From: Matheus Ferst
This instruction has VRT and VRB fields instead of T/TX and B/BX.
Reviewed-by: Richard Henderson
Signed-off-by: Matheus Ferst
Message-Id: <20211213120958.24443-4-victor.colo...@eldorado.org.br>
Signed-off-by: Cédric Le Goater
---
target/ppc/translate/vsx-impl.c.inc | 5 ++
From: Richard Henderson
Calling helper_frsp directly from other helpers generates
the incorrect retaddr. Split out a helper that takes the
retaddr as a parameter.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-22-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
It is never used.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-5-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.
From: Daniel Henrique Barboza
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert wi
From: Fabiano Rosas
The exception model id for 601v has been removed without mention
why. I assume it was inadvertent and restore it here.
Fixes: b632a148b6 ("target-ppc: Use QOM method dispatch for MMU fault handling")
Signed-off-by: Fabiano Rosas
Reviewed-by: Richard Henderson
Reviewed-by: C
It prepares ground for PHB5 which has different values.
Reviewed-by: Daniel Henrique Barboza
Reviewed-by: Frederic Barrat
Signed-off-by: Cédric Le Goater
Message-Id: <20211213132830.108372-9-...@kaod.org>
Signed-off-by: Cédric Le Goater
---
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/p
From: Richard Henderson
Now that vxsnan is computed directly by softfloat,
we don't need to recompute it.
Signed-off-by: Richard Henderson
Message-Id: <2029160502.17432-23-richard.hender...@linaro.org>
Signed-off-by: Cédric Le Goater
---
target/ppc/fpu_helper.c | 13 -
1 file
QEMU installs a custom U-Boot in-memory descriptor to share board
information with Linux, which means that the QEMU machine was
initially designed to support booting Linux directly without using the
loaded FW. But, it's not that simple because the CPU still starts at
address 0xfffc where nothin
Each PEC device of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" property.
Reviewed-by: Daniel Henrique Barboza
Reviewed-b
From: Daniel Henrique Barboza
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amou
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