Re: Redesign of QEMU startup & initial configuration

On Thu, Dec 02, 2021 at 07:57:38AM +0100, Markus Armbruster wrote: > = Motivation = > > QEMU startup and initial configuration were designed many years ago for > a much, much simpler QEMU. They have since changed beyond recognition > to adapt to new needs. There was no real redesign. Adaption t

Re: [PATCH] target/ppc: powerpc_excp: Guard ALIGNMENT interrupt with CONFIG_TCG

Fabiano Rosas writes: > Cédric Le Goater writes: > >> Richard, >> >> On 12/9/21 16:05, Fabiano Rosas wrote: >>> Cédric Le Goater writes: >>> On 12/9/21 00:06, Fabiano Rosas wrote: > We cannot have TCG code in powerpc_excp because the function is called > from kvm-only code via ppc

[PATCH v2 for-7.0] scripts: Explain the difference between linux-headers and standard-headers

If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth Signed-off-by: Peter Maydell --- v1 of this was from Thomas; I suggested so

Re: [PATCH v2 for-7.0] scripts: Explain the difference between linux-headers and standard-headers

On 09/12/2021 20.45, Peter Maydell wrote: If you don't know it, it's hard to figure out the difference between the linux-headers folder and the include/standard-headers folder. So let's add a short explanation to clarify the difference. Suggested-by: Thomas Huth Signed-off-by: Peter Maydell --

Re: [PATCH v2] target/i386: Use assert() to sanity-check b1 in SSE decode

Gave up pinging for i386 maintainers; will take this via target-arm.next. thanks -- PMM On Mon, 15 Nov 2021 at 14:38, Peter Maydell wrote: > > Ping^4. Who is collecting target/i386 patches these days ? > > -- PMM > > On Mon, 1 Nov 2021 at 16:18, Peter Maydell wrote: > > > > Ping^3, now 2 month

Re: Redesign of QEMU startup & initial configuration

I’ll take the liberty to cut one part (I agree with much of what you say elsewhere) > On 9 Dec 2021, at 20:11, Daniel P. Berrangé wrote: > > As illustrated earlier, I'd really like us to consider being a bit > more adventurous on the CLI side. I'm convinced that a CLI for > directly configurabl

Re: [PATCH 1/1] uas: add stream number sanity checks.

On Wed, Aug 18, 2021 at 02:05:05PM +0200, Gerd Hoffmann wrote: > The device uses the guest-supplied stream number unchecked, which can > lead to guest-triggered out-of-band access to the UASDevice->data3 and > UASDevice->status3 fields. Add the missing checks. > > Fixes: CVE-2021-3713 > Signed-of

Re: Redesign of QEMU startup & initial configuration

On Thu, Dec 09, 2021 at 09:01:24PM +0100, Mark Burton wrote: > I’ll take the liberty to cut one part (I agree with much of what you say > elsewhere) > > > On 9 Dec 2021, at 20:11, Daniel P. Berrangé wrote: > > > > As illustrated earlier, I'd really like us to consider being a bit > > more adven

[PATCH v2 3/4] intel_iommu: Only allow interrupt remapping to be enabled if it's supported

From: David Woodhouse We should probably check if we were meant to be exposing IR, before letting the guest turn the IRE bit on. Signed-off-by: David Woodhouse Reviewed-by: Peter Xu Acked-by: Jason Wang --- hw/i386/intel_iommu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff

[PATCH v2 4/4] intel_iommu: Fix irqchip / X2APIC configuration checks

We don't need to check kvm_enable_x2apic(). It's perfectly OK to support interrupt remapping even if we can't address CPUs above 254. Kind of pointless, but still functional. The check on kvm_enable_x2apic() needs to happen *anyway* in order to allow CPUs above 254 even without an IOMMU, so allow

[PATCH v2 1/4] target/i386: Fix sanity check on max APIC ID / X2APIC enablement

The check on x86ms->apic_id_limit in pc_machine_done() had two problems. Firstly, we need KVM to support the X2APIC API in order to allow IRQ delivery to APICs >= 255. So we need to call/check kvm_enable_x2apic(), which was done elsewhere in *some* cases but not all. Secondly, microvm needs the s

[PATCH v2 2/4] intel_iommu: Support IR-only mode without DMA translation

From: David Woodhouse By setting none of the SAGAW bits we can indicate to a guest that DMA translation isn't supported. Tested by booting Windows 10, as well as Linux guests with the fix at https://git.kernel.org/torvalds/c/c40c10 Signed-off-by: David Woodhouse Acked-by: Claudio Fontana -

Re: [PATCH v6 09/18] target/riscv: accessors to registers upper part and 128-bit load/store

On Mon, Nov 29, 2021 at 12:03 AM Frédéric Pétrot wrote: > > Get function to retrieve the 64 top bits of a register, stored in the gprh > field of the cpu state. Set function that writes the 128-bit value at once. > The access to the gprh field can not be protected at compile time to make > sure it

Re: [PATCH 1/7] hw/intc: sifive_plic: Add a reset function

On Wed, Dec 8, 2021 at 10:00 PM Philippe Mathieu-Daudé wrote: > > Hi Alistair, > > On 12/8/21 07:42, Alistair Francis wrote: > > From: Alistair Francis > > > > Signed-off-by: Alistair Francis > > --- > > hw/intc/sifive_plic.c | 12 > > 1 file changed, 12 insertions(+) > > > > diff

[PATCH] COLO: Move some trace code behind qemu_mutex_unlock_iothread()

Signed-off-by: Lei Rao --- migration/colo.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migration/colo.c b/migration/colo.c index 2415325262..3ccacb29c8 100644 --- a/migration/colo.c +++ b/migration/colo.c @@ -683,8 +683,8 @@ static void colo_incoming_process_checkp

Re: [PATCH v7 2/7] net/vmnet: add vmnet backends to qapi/net

Vladislav Yaroshchuk writes: > Create separate netdevs for each vmnet operating mode: > - vmnet-host > - vmnet-shared > - vmnet-bridged > > Signed-off-by: Vladislav Yaroshchuk > --- [...] > diff --git a/qapi/net.json b/qapi/net.json > index 7fab2e7cd8..8ed7bf0c04 100644 > --- a/qapi/net.json >

[PATCH 0/2] RISC-V: Populate mtval and stval

From: Alistair Francis Populate mtval and stval when taking an illegal instruction exception. The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value

[PATCH 1/2] target/riscv: Set the opcode in DisasContext

From: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1d57bc97b5..24251bc8cc 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -586

[PATCH 2/2] target/riscv: Implement the stval/mtval illegal instruction

From: Alistair Francis The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers based on the CPU feature. Signed-off-by: Alistair Francis --- target/riscv/cpu.h|

Re: [PATCH 7/7] hw/riscv: Use error_fatal for SoC realisation

Alistair Francis writes: > From: Alistair Francis > > When realising the SoC use error_fatal instead of error_abort as the > process can fail and report useful information to the user. > > Currently a user can see this: > >$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -disp

Re: [PATCH v10 00/77] support vector extension v1.0

On Wed, Dec 8, 2021 at 2:40 PM Alistair Francis wrote: > On Mon, Nov 29, 2021 at 1:04 PM wrote: > > > > From: Frank Chang > > > > This patchset implements the vector extension v1.0 for RISC-V on QEMU. > > > > RVV v1.0 spec is now fronzen for public review: > > https://github.com/riscv/riscv-v-s

[PATCH v6 0/8] target/riscv: support Zfh, Zfhmin extension v0.1

From: Frank Chang Zfh - Half width floating point Zfhmin - Subset of half width floating point Zfh, Zfhmin v0.1 is now in public review period and is required by RVV extension: https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/63gDCinXTwE/m/871Wm9XIBQAJ Zfh, Zfhmin can be enabled with -c

[PATCH v6 5/8] target/riscv: zfh: half-precision floating-point classify

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 6 ++ target/riscv/helper.h | 1 + target/riscv/insn32.de

[PATCH v6 3/8] target/riscv: zfh: half-precision convert and move

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Acked-by: Alistair Francis --- target/riscv/fpu_helper.c | 67 + target/riscv/helper.h | 12 + target/riscv/insn32.deco

[PATCH v6 2/8] target/riscv: zfh: half-precision computational

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 86 +++ target/riscv/helper.h | 13 +++ target/ri

[PATCH v6 1/8] target/riscv: zfh: half-precision load and store

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson --- target/riscv/cpu.h| 1 + target/riscv/insn32.decode| 4 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 65 ++

[PATCH v6 7/8] target/riscv: zfh: implement zfhmin extension

From: Frank Chang Zfhmin extension is a subset of Zfh extension, consisting only of data transfer and conversion instructions. If enabled, only the following instructions from Zfh extension are included: * flh, fsh, fmv.x.h, fmv.h.x, fcvt.s.h, fcvt.h.s * If D extension is present: fcvt.d.h,

[PATCH v6 6/8] target/riscv: zfh: add Zfh cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f812998123..0f808a5bee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -629,6 +629,7 @

[PATCH v6 4/8] target/riscv: zfh: half-precision floating-point compare

From: Kito Cheng Signed-off-by: Kito Cheng Signed-off-by: Chih-Min Chao Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/fpu_helper.c | 21 + target/riscv/helper.h | 3 ++ target/riscv/i

[PATCH v6 8/8] target/riscv: zfh: add Zfhmin cpu property

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0f808a5bee..9835829588 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -630,6 +630,7 @

Re: [PATCH 3/4] Move CONFIG_XFS handling to meson.build

On 02/11/2021 12.34, Paolo Bonzini wrote: On 28/10/21 20:59, Thomas Huth wrote: Checking for xfsctl() can be done more easily in meson.build. Also, this is not a "real" feature like the other features that we provide with the "--enable-xxx" and "--disable-xxx" switches for the configure script,

[PATCH v11 01/77] target/riscv: drop vector 0.7.1 and add 1.0 support

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 16 target/riscv/cpu.h | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target

[PATCH v11 02/77] target/riscv: Use FIELD_EX32() to extract wd field

From: Frank Chang Signed-off-by: Frank Chang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/vector_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..70f58981

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