From: Alistair Francis <alistair.fran...@wdc.com> Populate mtval and stval when taking an illegal instruction exception.
The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value on an illegal instruction. This doesn't match all CPUs (some CPUs won't write the data), but in QEMU let's just populate the value on illegal instructions. This won't break any guest software, but will provide more information to guests. *** BLURB HERE *** Alistair Francis (2): target/riscv: Set the opcode in DisasContext target/riscv: Implement the stval/mtval illegal instruction target/riscv/cpu.h | 2 ++ target/riscv/cpu_helper.c | 25 +++++++++++-------------- target/riscv/translate.c | 5 +++++ 3 files changed, 18 insertions(+), 14 deletions(-) -- 2.31.1
