> On Nov 19, 2021, at 2:42 PM, Alex Williamson
> wrote:
>
> On Mon, 8 Nov 2021 16:46:39 -0800
> John Johnson wrote:
>
>> Signed-off-by: Elena Ufimtseva
>> Signed-off-by: John G Johnson
>> Signed-off-by: Jagannathan Raman
>> ---
>> hw/vfio/user-protocol.h | 14
>> includ
> On Nov 19, 2021, at 2:42 PM, Alex Williamson
> wrote:
>
> On Mon, 8 Nov 2021 16:46:47 -0800
> John Johnson wrote:
>
>> bug fix: only set qemu file error if there is a file
>
>
> I don't understand this commit log. Is this meant to be a revision
> log? In general it would be nice to h
On 06/12/2021 23.20, Laurent Vivier wrote:
Scan the PCI devices to find bridge and set PCI_SECONDARY_BUS and
PCI_SUBORDINATE_BUS (algorithm from seabios)
Signed-off-by: Laurent Vivier
---
include/hw/pci/pci_bridge.h | 8 +++
tests/qtest/libqos/pci.c| 118 +++
On 07.12.21 08:06, Daniil Tatianin wrote:
> This is needed for cases where we want to make sure that a shared memory
> region gets allocated from a specific NUMA node. This is impossible to do
> with mbind(2) because it ignores the policy for memory mapped with
> MAP_SHARED. We work around this by
On 06/12/2021 23.20, Laurent Vivier wrote:
Add test cases to test several error cases that must be
generated by invalid failover configuration.
Add a combination of coldplug and hotplug test cases to be
sure the primary is correctly managed according the
presence or not of the STANDBY feature.
On 07.12.21 08:06, Daniil Tatianin wrote:
> Previously we would calculate the last set bit in the mask, and add
> 2 to that value to get the maxnode value. This is unnecessary since
> the mbind syscall allows the bitmap to be any (reasonable) size as
> long as all the unused bits are clear. This al
On 06/12/2021 23.20, Laurent Vivier wrote:
Update the migration test to check we correctly wait the end
of the card unplug before doing the migration.
Signed-off-by: Laurent Vivier
---
tests/qtest/virtio-net-failover.c | 34 +++
1 file changed, 34 insertions(+)
d
On 06/12/2021 23.20, Laurent Vivier wrote:
Add some tests to check the state of the machine if the migration
is cancelled while we are using virtio-net failover.
Signed-off-by: Laurent Vivier
---
tests/qtest/virtio-net-failover.c | 291 ++
1 file changed, 291 inse
On 06/12/2021 23.20, Laurent Vivier wrote:
Signed-off-by: Laurent Vivier
---
tests/qtest/virtio-net-failover.c | 279 ++
1 file changed, 279 insertions(+)
diff --git a/tests/qtest/virtio-net-failover.c
b/tests/qtest/virtio-net-failover.c
index 57abb99e7f6e..ace90
The netfilter test needs a NIC, no matter which one, so it uses
e1000 by default (or virtio-net-ccw on s390x). However, this NIC
might not be always compiled into the QEMU target binary, so assuming
that this NIC is always available is a bad idea. Since the exact type
of NIC does not really matter
07.12.2021 02:00, Eric Blake wrote:
On Mon, Dec 06, 2021 at 02:40:45PM +0300, Vladimir Sementsov-Ogievskiy wrote:
Simple reply message
The simple reply message MUST be sent by the server in response to all
requests if structured replies have not been negotiated using
-`NBD_OPT_STR
Subject: [PATCH for 6.2?] gicv3: fix ICH_MISR's LRENP computation
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.E
Jonah Palmer writes:
> From: Laurent Vivier
>
> These new commands show the internal status of a VirtIODevice's
> VirtQueue and a vhost device's vhost_virtqueue (if active).
>
> Signed-off-by: Jonah Palmer
> ---
[...]
> diff --git a/qapi/virtio.json b/qapi/virtio.json
> index 7ef1f95..56e56d2
Sorry for the inconvenience, I screwed-up with the subject line.
Should I resend ?
Damien
On 12/7/21 10:29, Damien Hedde wrote:
Subject: [PATCH for 6.2?] gicv3: fix ICH_MISR's LRENP computation
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture versi
On 02/12/2021 15:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
Signed-off-by: Cédric Le Goater
---
The Naples chip (Garrison) can have 4 PHBs and it seems we have a
power8nvl machine type for it.
On 02/12/2021 15:42, Cédric Le Goater wrote:
It is never used.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Frederic Barrat
hw/ppc/pnv.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index bd768dcc28ad..988b305398b2 100644
--- a/hw/ppc/pnv.c
+++
On 02/12/2021 15:42, Cédric Le Goater wrote:
This requires a link to the chip to add the regions under the XSCOM
address space. This change will help us providing support for user
created PHB3 devices.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Frederic Barrat
include/hw/pci-h
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.EOIcount is non-zero.
When only LRENPIE was set (and EOI count was
On 12/6/21 21:09, David Gibson wrote:
On Mon, Dec 06, 2021 at 10:02:53AM -0300, Daniel Henrique Barboza wrote:
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device
On 02/12/2021 15:42, Cédric Le Goater wrote:
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in the chip. In case of user
created devices,
Jonah Palmer writes:
> From: Laurent Vivier
>
> This new command shows the information of a VirtQueue element.
>
> Signed-off-by: Jonah Palmer
> ---
> hw/virtio/virtio-stub.c | 9 +++
> hw/virtio/virtio.c | 154
> qapi/virtio.json| 183
>
Setting -uuid in the pnv machine does not work:
./qemu-system-ppc64 -machine powernv8,accel=tcg -uuid
7ff61ca1-a4a0-4bc1-944c-abd114a35e80
qemu-system-ppc64: error creating device tree: (fdt_property_string(fdt,
"system-id", buf)): FDT_ERR_BADSTATE
This happens because we're using fdt_property
On 02/12/2021 15:42, Cédric Le Goater wrote:
The powernv machine uses the object hierarchy to populate the device
tree and each device should be parented to the chip it belongs to.
This is not the case for user created devices which are parented to
the container "/unattached".
Make sure a PHB
On 02/12/2021 15:42, Cédric Le Goater wrote:
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
This one is a bit of black magic for me. I don't see an equivalent for
P9 though. Not needed there? I'll have another comment about P
On 02/12/2021 15:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
A num_pecs class attri
On 02/12/2021 15:42, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Empty log message ok in qemu?
But it looks ok to me.
Reviewed-by: Frederic Barrat
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 4 ++--
On 02/12/2021 15:42, Cédric Le Goater wrote:
Next changes will make use of it.
Signed-off-by: Cédric Le Goater
---
Reviewed-by: Frederic Barrat
include/hw/pci-host/pnv_phb4.h | 2 ++
hw/pci-host/pnv_phb4_pec.c | 2 ++
hw/ppc/pnv.c | 2 ++
3 files changed, 6 i
On 02/12/2021 15:42, Cédric Le Goater wrote:
Each PEC devices of the POWER9 chip has a predefined number of stacks,
equivalent of a root port complex:
PEC0 -> 1 stack
PEC1 -> 2 stacks
PEC2 -> 3 stacks
Introduce a class attribute to hold these values and remove the
"num-stacks" prope
On 02/12/2021 15:42, Cédric Le Goater wrote:
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and PHB5)
Signed-off-by: Cédric Le Goater
--
On 02/12/2021 15:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
I doubt I see all the implications here, but it doesn't look wrong to
me, so:
Reviewed-by: Frederic Barrat
Fred
h
On 12/7/21 10:40, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
All POWER8 machines have a maximum of 3 PHB3 devices. Adapt the
PNV8_CHIP_PHB3_MAX definition for consistency.
Signed-off-by: Cédric Le Goater
---
The Naples chip (Garrison) can have 4 PHBs and it seems
On Thu, Nov 4, 2021 at 10:23 AM Alistair Francis wrote:
>
> On Tue, Oct 26, 2021 at 6:00 PM Anup Patel wrote:
> >
> > The AIA device emulation (such as AIA IMSIC) should be able to set
> > (or provide) AIA ireg read-modify-write callback for each privilege
> > level of a RISC-V HART.
> >
> > Sign
On 02/12/2021 15:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
I forgot to mention the typo in the commit title: "he PHB4".
Fred
hw/pci-host/pnv_phb4_pec.c | 6 +-
hw/ppc/pnv
On 02/12/2021 15:42, Cédric Le Goater wrote:
PHB4 devices and PCI devices can now be added to the powernv9 machine
using:
-device pnv-phb4-pec,chip-id=0,index=0
-device nec-usb-xhci,bus=pci.0,addr=0x0
In case of user created devices, a lookup on 'chip-id' is required to
assign the owni
On 02/12/2021 15:42, Cédric Le Goater wrote:
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c | 31 +--
On 12/7/21 10:47, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
PHB3 devices and PCI devices can now be added to the powernv8 machine
using :
-device pnv-phb3,chip-id=0,index=1 \
-device nec-usb-xhci,bus=pci.1,addr=0x0
The 'index' property identifies the PHB3 in t
Signed-off-by: Vladislav Yaroshchuk
---
meson.build | 4
meson_options.txt | 2 ++
scripts/meson-buildoptions.sh | 3 +++
3 files changed, 9 insertions(+)
diff --git a/meson.build b/meson.build
index 96de1a6ef9..ce8acf6ada 100644
--- a/meson.build
+++ b/meson.b
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-host.c | 93
1 file changed, 87 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-host.c b/net/vmnet-host.c
index 4a5ef99dc7..9c2e760ed1 100644
--- a/net/vmnet-host.c
+++ b/net/vmnet-host.c
@@ -
Signed-off-by: Vladislav Yaroshchuk
---
net/vmnet-bridged.m | 98 ++---
1 file changed, 92 insertions(+), 6 deletions(-)
diff --git a/net/vmnet-bridged.m b/net/vmnet-bridged.m
index 4e42a90391..3c9da9dc8b 100644
--- a/net/vmnet-bridged.m
+++ b/net/vmnet-br
macOS provides networking API for VMs called 'vmnet.framework':
https://developer.apple.com/documentation/vmnet
We can provide its support as the new QEMU network backends which
represent three different vmnet.framework interface usage modes:
* `vmnet-shared`:
allows the guest to communicat
Create separate netdevs for each vmnet operating mode:
- vmnet-host
- vmnet-shared
- vmnet-bridged
Signed-off-by: Vladislav Yaroshchuk
---
net/clients.h | 11
net/meson.build | 7 +++
net/net.c | 10
net/vmnet-bridged.m | 25 +
net/vmnet-common.m | 20
On 12/7/21 11:01, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
Empty log message ok in qemu?
checkpatch didn't complain :) I might make an effort for v2.
Thanks,
C.
But it looks ok to me.> Reviewed-by: Frederic Barrat
Interaction with vmnet.framework in different modes
differs only on configuration stage, so we can create
common `send`, `receive`, etc. procedures and reuse them.
vmnet.framework supports iov, but writing more than
one iov into vmnet interface fails with
'VMNET_INVALID_ARGUMENT'. Collecting provi
Signed-off-by: Vladislav Yaroshchuk
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..5c696e38da 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2631,6 +2631,11 @@ W: http://info.iet.unipi.it/~luigi/netmap/
S: Maintained
F: net/n
Signed-off-by: Vladislav Yaroshchuk
---
qemu-options.hx | 25 +
1 file changed, 25 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index ae2c6dbbfc..1ffa5eedd5 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2677,6 +2677,25 @@ DEF("netdev", HAS_ARG, QE
On 12/7/21 11:06, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
Use the num_stacks class attribute to compute the PHB index depending
on the PEC index :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB3, PHB4 and P
On 12/7/21 10:53, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
PHB3s ared SysBus devices and should be allowed to be dynamically
created.
Signed-off-by: Cédric Le Goater
---
This one is a bit of black magic for me.
Yes. QEMU internals related to sysbus. I am not a
On 12/7/21 11:08, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
This is not useful and will be in the way for support of user created
PHB4 devices.
Signed-off-by: Cédric Le Goater
---
I doubt I see all the implications here,
It is good practice to avoid statics in
On 12/7/21 11:10, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
This change will help us providing support for user created PHB4
devices.
Signed-off-by: Cédric Le Goater
---
hw/pci-host/pnv_phb4_pec.c | 36
hw/ppc/pnv.c
On 12/7/21 11:00, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PHBs (PHB1 and PHB2)
* PEC2 provides 3 PHBs (PHB
From: Long YunJian
when blockcommit from active leaf node, sometimes, we get assertion failed with
"mirror_run: Assertion `QLIST_EMPTY(&bs->tracked_requests)' failed" messages.
According to the core file, we find bs->tracked_requests has IO request,
so assertion failed.
(gdb) bt
#0 0x7f410df
On 12/2/21 03:51, Cédric Le Goater wrote:
> Hello Leonardo,
>
> On 11/23/21 13:10, lagar...@linux.ibm.com wrote:
>> From: Leonardo Garcia
>>
>> Signed-off-by: Leonardo Garcia
>> ---
>
> It seems that POWER10 was renamed to Power10 but not POWER9. And :
>
> https://en.wikipedia.org/wiki/Power9
This function calls three functions:
- postcopy_discard_send_init(ms, block->idstr);
- postcopy_chunk_hostpages_pass(ms, block);
- postcopy_discard_send_finish(ms);
However only the 2nd function call is meaningful. It's major role is to make
sure dirty bits are applied in host-page-size gr
It always return zero, because it just can't go wrong so far. Simplify the
code with no functional change.
Signed-off-by: Peter Xu
---
migration/ram.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/migration/ram.c b/migration/ram.c
index 756ac800a7..fb8c1a887e 1
It'll be easier to read the name rather than index of sub-cmd when debugging.
Signed-off-by: Peter Xu
---
migration/savevm.c | 2 +-
migration/trace-events | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/migration/savevm.c b/migration/savevm.c
index d59e976d50..17b8e25
It will just never fail. Drop those return values where they're constantly
zeros.
A tiny touch-up on the tracepoint so trace_ram_postcopy_send_discard_bitmap()
is called after the logic itself (which sounds more reasonable).
Signed-off-by: Peter Xu
---
migration/migration.c | 5 +
migrati
Right now we loop ramblocks for twice, the 1st time chunk the dirty bits with
huge page information; the 2nd time we send the discard ranges. That's not
necessary - we can do them in a single loop.
Signed-off-by: Peter Xu
---
migration/ram.c | 20 ++--
1 file changed, 10 inserti
The enablement of postcopy listening has a few steps, add a few tracepoints to
be there ready for some basic measurements for them.
Signed-off-by: Peter Xu
---
migration/savevm.c | 5 -
migration/trace-events | 2 +-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/migratio
Some queued patches for ram disgard cleanup, and some debug probes.
QEMU's ram disgard logic is probably a bit hard to predict because we send a
bunch of packets to notify the disgarded ranges rather than sending the bitmap.
The packets to send depending on the bitmap layout.
Initially I thought
I planned to add "#ifdef DEBUG_POSTCOPY" around the function too because
otherwise it'll be compiled into qemu binary even if it'll never be used. Then
I found that maybe it's easier to just drop it for good..
Signed-off-by: Peter Xu
---
migration/ram.c | 39
[CC-ing qemu-block, Vladimir, Kevin, and John – when sending patches,
please look into the MAINTAINERS file or use the
scripts/get_maintainer.pl script to find out who to CC on them. It’s
very to overlook patches on qemu-devel :/]
On 07.12.21 11:56, Yi Wang wrote:
From: Long YunJian
when b
On Mon, Dec 6, 2021 at 11:15 PM Markus Armbruster wrote:
>
> Watch this:
>
> $ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display
> none -drive if=pflash
> QEMU 6.1.93 monitor - type 'help' for more information
> (qemu) Unexpected error in sifive_u_otp_realize() at
On 12/7/21 10:44, Damien Hedde wrote:
> According to the "Arm Generic Interrupt Controller Architecture
> Specification GIC architecture version 3 and 4" (version G: page 345
> for aarch64 or 509 for aarch32):
> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
> ICH_HCR.EOIcount is non-zero
On 12/7/21 13:45, Philippe Mathieu-Daudé wrote:
On 12/7/21 10:44, Damien Hedde wrote:
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR
v3:
- Fixed FUSE export aio_set_fd_handler() call that I missed and double-checked
for any other missing call sites using Coccinelle [Rich]
v2:
- Cleaned up unused return values in nvme and virtio-blk [Stefano]
- Documented try_poll_mode() ready_list argument [Stefano]
- Unified virtio-blk/scsi d
Prepare virtio_scsi_handle_cmd() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd more
specific. This way it won't trigger when dataplane has already been
started.
Signed-off-by: Stefan Hajnoczi
---
hw/scsi/virtio-scsi.c | 2 +-
1 file changed, 1 inse
The return value of virtio_blk_handle_vq() is no longer used. Get rid of
it. This is a step towards unifying the dataplane and non-dataplane
virtqueue handler functions.
Prepare virtio_blk_handle_output() to be used by both dataplane and
non-dataplane by making the condition for starting ioeventfd
The virtqueue host notifier API
virtio_queue_aio_set_host_notifier_handler() polls the virtqueue for new
buffers. AioContext previously required a bool progress return value
indicating whether an event was handled or not. This is no longer
necessary because the AioContext polling API has been split
The difference between ->handle_output() and ->handle_aio_output() was
that ->handle_aio_output() returned a bool return value indicating
progress. This was needed by the old polling API but now that the bool
return value is gone, the two functions can be unified.
Signed-off-by: Stefan Hajnoczi
-
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when in fact the event handler was running for a long time.
For example,
Now that virtio-blk and virtio-scsi are ready, get rid of
the handle_aio_output() callback. It's no longer needed.
Signed-off-by: Stefan Hajnoczi
---
include/hw/virtio/virtio.h | 4 +--
hw/block/dataplane/virtio-blk.c | 16 ++
hw/scsi/virtio-scsi-dataplane.c | 54 --
On Mon, Dec 06, 2021 at 02:34:45PM +, Peter Maydell wrote:
> On Mon, 6 Dec 2021 at 14:33, Stefan Hajnoczi wrote:
> >
> > v3:
> > - Added __attribute__((weak)) to get_ptr_*() [Florian]
>
> Do we really need it *only* on get_ptr_*() ? If we need to
> noinline the other two we probably also shou
On Tue, 7 Dec 2021 at 13:05, Damien Hedde wrote:
> On 12/7/21 13:45, Philippe Mathieu-Daudé wrote:
> > On 12/7/21 10:44, Damien Hedde wrote:
> >> According to the "Arm Generic Interrupt Controller Architecture
> >> Specification GIC architecture version 3 and 4" (version G: page 345
> >> for aarch
On 12/6/21 8:54 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
When testing live migration with multifd channels (8, 16, or a bigger number)
and using qemu -incoming (without "defer"), if a network error occurs
(for example, triggering the kernel SYN flooding detection),
On 12/6/21 8:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
Thanks for Daniel's review.
Hi David and Juan,
Any comments for this patch?
Yeh I think that's OK, so
Reviewed-by: Dr. David Alan Gilbert
I'd have a slight preference for it being before the post I thi
On Mon, Dec 06, 2021 at 02:34:45PM +, Peter Maydell wrote:
> On Mon, 6 Dec 2021 at 14:33, Stefan Hajnoczi wrote:
> >
> > v3:
> > - Added __attribute__((weak)) to get_ptr_*() [Florian]
>
> Do we really need it *only* on get_ptr_*() ? If we need to
> noinline the other two we probably also shou
On Tue, 7 Dec 2021 at 13:53, Stefan Hajnoczi wrote:
>
> On Mon, Dec 06, 2021 at 02:34:45PM +, Peter Maydell wrote:
> > On Mon, 6 Dec 2021 at 14:33, Stefan Hajnoczi wrote:
> > >
> > > v3:
> > > - Added __attribute__((weak)) to get_ptr_*() [Florian]
> >
> > Do we really need it *only* on get_pt
I believe you're right. Looking at the implementation of shmem_alloc_page, it uses the inode policy, which is set viavma->set_policy (from the mbind() call in this case). set_mempolicy is both useless and redundant here, as thread'spolicy is only ever used in case vma->get_policy returns NULL (whic
On 07/12/2021 11:45, Cédric Le Goater wrote:
On 12/7/21 11:00, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provides 1 PHB (PHB0)
* PEC1 provides 2 PH
No cover letter?
On Tue, Dec 07, 2021 at 02:45:10PM +0100, Li Zhang wrote:
>
> On 12/6/21 8:54 PM, Dr. David Alan Gilbert wrote:
> > * Li Zhang (lizh...@suse.de) wrote:
> > > When testing live migration with multifd channels (8, 16, or a bigger
> > > number)
> > > and using qemu -incoming (without "defer"), if a
On Tue, 7 Dec 2021 at 09:44, Damien Hedde wrote:
>
> According to the "Arm Generic Interrupt Controller Architecture
> Specification GIC architecture version 3 and 4" (version G: page 345
> for aarch64 or 509 for aarch32):
> LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
> ICH_HCR.EOIcou
On 12/7/21 15:03, Frederic Barrat wrote:
On 07/12/2021 11:45, Cédric Le Goater wrote:
On 12/7/21 11:00, Frederic Barrat wrote:
On 02/12/2021 15:42, Cédric Le Goater wrote:
POWER9 processor comes with 3 PHB4 PECs (PCI Express Controller) and
each PEC can have several PHBs :
* PEC0 provi
The following changes since commit 7635eff97104242d618400e4b6746d0a5c97af82:
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging (2021-12-06 11:18:06 -0800)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-202
With arm32, the ABI gives us 8-byte alignment for the stack.
While it's possible to realign the stack to provide 16-byte alignment,
it's far easier to simply not encode 16-byte alignment in the
VLD1 and VST1 instructions that we emit.
Remove the assertion in temp_allocate_frame, limit natural alig
On Mon, 6 Dec 2021 11:47:55 +
Daniel P. Berrangé wrote:
> On Mon, Dec 06, 2021 at 12:43:12PM +0100, Claudio Imbrenda wrote:
> > On Mon, 6 Dec 2021 11:21:10 +
> > Daniel P. Berrangé wrote:
> >
> > > On Mon, Dec 06, 2021 at 12:06:11PM +0100, Claudio Imbrenda wrote:
> > > > This patch
On 07.12.21 14:58, Daniil Tatianin wrote:
> I believe you're right. Looking at the implementation of
> shmem_alloc_page, it uses the inode policy, which is set via
> vma->set_policy (from the mbind() call in this case). set_mempolicy is
> both useless and redundant here, as thread's
> policy is onl
> -Original Message-
> From: Qemu-devel
> On Behalf Of Peter Maydell
...
> On Tue, 7 Dec 2021 at 09:44, Damien Hedde
> wrote:
> >
> > According to the "Arm Generic Interrupt Controller Architecture
> > Specification GIC architecture version 3 and 4" (version G: page 345
> > for aarch64 or
On 12/7/21 15:21, Peter Maydell wrote:
On Tue, 7 Dec 2021 at 09:44, Damien Hedde wrote:
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH
On Tue, 7 Dec 2021 at 15:18, Brian Cain wrote:
> Peter Maydell wrote:
> > I won't try to put this into 6.2 unless you have a common guest
> > that runs into this bug.
> I know that Qualcomm encounters this issue with its hypervisor
> (https://github.com/quic/gunyah-hypervisor). Apologies for no
> -Original Message-
> From: Peter Maydell
...
> On Tue, 7 Dec 2021 at 15:18, Brian Cain wrote:
> > Peter Maydell wrote:
> > > I won't try to put this into 6.2 unless you have a common guest
> > > that runs into this bug.
>
> > I know that Qualcomm encounters this issue with its hyperv
On 12/7/21 3:16 PM, Daniel P. Berrangé wrote:
On Tue, Dec 07, 2021 at 02:45:10PM +0100, Li Zhang wrote:
On 12/6/21 8:54 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
When testing live migration with multifd channels (8, 16, or a bigger number)
and using qemu -incoming
On Tue, 7 Dec 2021 at 15:24, Peter Maydell wrote:
> The bug is a bug in any case and we'll fix it, it's just a
> question of whether it meets the bar to go into 6.2, which is
> hopefully going to have its final RC tagged today. If this
> patch had arrived a week ago then the bar would have been
>
On 12/7/21 16:45, Peter Maydell wrote:
On Tue, 7 Dec 2021 at 15:24, Peter Maydell wrote:
The bug is a bug in any case and we'll fix it, it's just a
question of whether it meets the bar to go into 6.2, which is
hopefully going to have its final RC tagged today. If this
patch had arrived a wee
The FUSE exports feature is not built because most container images do
not have libfuse3 development headers installed. Add the necessary
packages to the Dockerfiles.
Cc: Hanna Reitz
Cc: Richard W.M. Jones
Signed-off-by: Stefan Hajnoczi
---
tests/docker/dockerfiles/alpine.docker| 1 +
On Tue, Dec 07, 2021 at 04:00:25PM +, Stefan Hajnoczi wrote:
...
> diff --git a/tests/docker/dockerfiles/centos8.docker
> b/tests/docker/dockerfiles/centos8.docker
> index 7f135f8e8c..a2dae4be29 100644
> --- a/tests/docker/dockerfiles/centos8.docker
> +++ b/tests/docker/dockerfiles/centos8.doc
On Mon, Dec 06, 2021 at 05:00:47PM -0600, Eric Blake wrote:
> On Mon, Dec 06, 2021 at 02:40:45PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> > > Simple reply message
> > >
> > > The simple reply message MUST be sent by the server in response to all
> > > requests if structured replies
On Tue, Dec 07, 2021 at 01:55:34PM +, Peter Maydell wrote:
> On Tue, 7 Dec 2021 at 13:53, Stefan Hajnoczi wrote:
> >
> > On Mon, Dec 06, 2021 at 02:34:45PM +, Peter Maydell wrote:
> > > On Mon, 6 Dec 2021 at 14:33, Stefan Hajnoczi wrote:
> > > >
> > > > v3:
> > > > - Added __attribute__((
Hi Markus,
It looks promising. I did not think we could so "easily" have a new
working startup. But I'm not so sure that I understand how we should
progress from here.
I see 3 main parts in this:
A. introducing new binary (meson, ...)
B. startup api: phase related stuff (maybe more)
C. cli to
> -Original Message-
> From: Peter Maydell
> Sent: Monday, November 29, 2021 2:05 PM
> To: qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Paolo Bonzini ; Sergio Lopez ;
> Taylor Simpson ; Yoshinori Sato
> ; Marcel Apfelbaum
>
> Subject: [PATCH for-7.0 2/4] target/hexagon/cpu.h: don't
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