On 12/2/21 03:51, Cédric Le Goater wrote: > Hello Leonardo, > > On 11/23/21 13:10, lagar...@linux.ibm.com wrote: >> From: Leonardo Garcia <lagar...@br.ibm.com> >> >> Signed-off-by: Leonardo Garcia <lagar...@br.ibm.com> >> --- > > It seems that POWER10 was renamed to Power10 but not POWER9. And : > > https://en.wikipedia.org/wiki/Power9 redirects to POWER9 > https://en.wikipedia.org/wiki/POWER10 redirects to Power10 > > I will keep the upper case POWER9. No need to resend.
Ok. Thanks! I'll keep this nomenclature on the pseries documentation patches as well. Cheers, Leo > > Thanks, > > C. > > > >> docs/system/ppc/powernv.rst | 57 +++++++++++++++++++------------------ >> 1 file changed, 29 insertions(+), 28 deletions(-) >> >> diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst >> index 86186b7d2c..eda4219a27 100644 >> --- a/docs/system/ppc/powernv.rst >> +++ b/docs/system/ppc/powernv.rst >> @@ -1,7 +1,7 @@ >> -PowerNV family boards (``powernv8``, ``powernv9``) >> +PowerNV family boards (``powernv8``, ``powernv9``, ``powernv10``) >> ================================================================== >> -PowerNV (as Non-Virtualized) is the "baremetal" platform using the >> +PowerNV (as Non-Virtualized) is the "bare metal" platform using the >> OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can >> be used as an hypervisor OS, running KVM guests, or simply as a host >> OS. >> @@ -15,17 +15,15 @@ beyond the scope of what QEMU addresses today. >> Supported devices >> ----------------- >> - * Multi processor support for POWER8, POWER8NVL and POWER9. >> - * XSCOM, serial communication sideband bus to configure chiplets >> - * Simple LPC Controller >> - * Processor Service Interface (PSI) Controller >> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9) >> - * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge >> - * Simple OCC is an on-chip microcontroller used for power management >> - tasks >> - * iBT device to handle BMC communication, with the internal BMC >> - simulator provided by QEMU or an external BMC such as an Aspeed >> - QEMU machine. >> + * Multi processor support for POWER8, POWER8NVL and Power9. >> + * XSCOM, serial communication sideband bus to configure chiplets. >> + * Simple LPC Controller. >> + * Processor Service Interface (PSI) Controller. >> + * Interrupt Controller, XICS (POWER8) and XIVE (Power9) and XIVE2 >> (Power10). >> + * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge. >> + * Simple OCC is an on-chip micro-controller used for power >> management tasks. >> + * iBT device to handle BMC communication, with the internal BMC >> simulator >> + provided by QEMU or an external BMC such as an Aspeed QEMU machine. >> * PNOR containing the different firmware partitions. >> Missing devices >> @@ -33,27 +31,25 @@ Missing devices >> A lot is missing, among which : >> - * POWER10 processor >> - * XIVE2 (POWER10) interrupt controller >> - * I2C controllers (yet to be merged) >> - * NPU/NPU2/NPU3 controllers >> - * EEH support for PCIe Host bridge controllers >> - * NX controller >> - * VAS controller >> - * chipTOD (Time Of Day) >> + * I2C controllers (yet to be merged). >> + * NPU/NPU2/NPU3 controllers. >> + * EEH support for PCIe Host bridge controllers. >> + * NX controller. >> + * VAS controller. >> + * chipTOD (Time Of Day). >> * Self Boot Engine (SBE). >> - * FSI bus >> + * FSI bus. >> Firmware >> -------- >> The OPAL firmware (OpenPower Abstraction Layer) for OpenPower >> systems >> includes the runtime services ``skiboot`` and the bootloader kernel >> and >> -initramfs ``skiroot``. Source code can be found on GitHub: >> +initramfs ``skiroot``. Source code can be found on the `OpenPOWER >> account at >> +GitHub <https://github.com/open-power>`_. >> - https://github.com/open-power. >> - >> -Prebuilt images of ``skiboot`` and ``skiroot`` are made available on >> the `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ >> site. >> +Prebuilt images of ``skiboot`` and ``skiroot`` are made available on >> the >> +`OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site. >> QEMU includes a prebuilt image of ``skiboot`` which is updated >> when a >> more recent version is required by the models. >> @@ -83,6 +79,7 @@ and a SATA disk : >> Complex PCIe configuration >> ~~~~~~~~~~~~~~~~~~~~~~~~~~ >> + >> Six PHBs are defined per chip (POWER9) but no default PCI layout is >> provided (to be compatible with libvirt). One PCI device can be added >> on any of the available PCIe slots using command line options such as: >> @@ -157,7 +154,7 @@ one on the command line : >> The files `palmetto-SDR.bin >> <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__ >> and `palmetto-FRU.bin >> <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__ >> define a Sensor Data Record repository and a Field Replaceable Unit >> -inventory for a palmetto BMC. They can be used to extend the QEMU BMC >> +inventory for a Palmetto BMC. They can be used to extend the QEMU BMC >> simulator. >> .. code-block:: bash >> @@ -189,4 +186,8 @@ CAVEATS >> ------- >> * No support for multiple HW threads (SMT=1). Same as pseries. >> - * CPU can hang when doing intensive I/Os. Use ``-append >> powersave=off`` in that case. >> + >> +Maintainer contact information >> +------------------------------ >> + >> +Cédric Le Goater <c...@kaod.org> >> \ No newline at end of file >> > >
