This patch gives an introduction to the LoongArch target.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
MAINTAINERS | 5
target/loongarch/README | 76 +
2 files changed, 81 insertions(+)
This patch adds target state header, target definitions
and initialization routines.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/cpu-param.h | 18 +++
target/loongarch/cpu.c | 313 +++
t
Based-on:
https://patchew.org/QEMU/1637893388-10282-1-git-send-email-gaos...@loongson.cn/
Hi all,
This series only support linux-user emulation.
More about LoongArch at: https://github.com/loongson/
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
Patches need revie
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_shift.c.inc | 106 +++
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_atomic.c.inc | 136 +
target/loongarch/i
This patch adds main translation routines and
basic functions for translation.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h| 6 ++
target/loongarch/op_helper.c | 21 ++
target/loongarch/translate.c | 159 ++
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helper.h | 4 ++
target/loongarch/insn_trans/trans_extra.c.in
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Signed
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/signal.c| 198 +
linux-user/loongarch64/target_signal.h | 13 +++
2 files changed, 211 insertions(+)
create mode 100644 linux-user/loongarch64/signal.c
create mode 100644 li
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loonga
This includes:
- FCMP.cond.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 60
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_fc
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
--
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
linux-user/loongarch64/syscall_nr.h | 313
linux
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/helpe
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c| 393 +++
tar
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
include/elf.h | 2 ++
linux-user/elfload.c| 58 +
linux-user/loongarch64/target_elf.h | 12
3 files changed, 72 insertions(
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/fpu_helper.c
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_fmemory.c.inc | 153
target/loongarch/insns.dec
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
configure | 5 ++
linux-user/loongarch64/cpu_loop.c | 94 +
linux-user/loongarch64/target_cpu.h | 34 ++
3 files changed, 133 inse
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 7de996d..da6a937 100755
--- a/scripts/qemu
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
linux-user/loongarch64/sockbits.h | 11 +++
linux-user/loongarch64/target_errno_defs.h | 12
lin
On 01.12.21 00:45, Michael S. Tsirkin wrote:
> On Tue, Nov 30, 2021 at 10:28:35AM +0100, David Hildenbrand wrote:
>> Support VIRTIO_MEM_F_UNPLUGGED_INACCESSIBLE in QEMU, which indicates to
>> a guest that we don't support reading unplugged memory. We indicate
>> the feature based on a new "unplugge
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/target_structs.h | 47 +
1 file changed, 47 insertions(+)
create mode 100644 linux-user/loongarch64/target_structs.h
diff --git a/linux-user/loongarch64/target_structs.h
b/linux-use
This patch adds support for disassembling via option '-d in_asm'.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
include/disas/dis-asm.h | 2 +
meson.build | 1 +
target/loongarch/disas.c | 612 +++
3 files changed, 615 ins
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
target/loongarch/insn_trans/trans_branch.c.inc | 83 ++
target/loongarch/insns.decode
This patch adds loongarch64 linux-user default configs file.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 configs/targets/loongarch64-linux-user.ma
This patch adds build loongarch-linux-user target support.
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
---
meson.build | 2 +-
target/loongarch/meson.build | 19 +++
target/meson.build | 1 +
3 files changed,
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
Reviewed-by: Richard Henderson
Acked-by: Alex Bennée
---
tests/tcg/configure.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 9b76f58..49a05ec 100755
--- a/tests/tcg/configure.sh
++
On 29/11/2021 11.07, Daniel P. Berrangé wrote:
On Fri, Nov 26, 2021 at 05:27:24PM +0100, Thomas Huth wrote:
The device-crash-test script has been quite neglected in the past,
so that it bit-rot quite often. Let's add CI jobs that run this
script for at least some targets, so that this script doe
>>>
>>> * It has been passing the tests with various combinations like 64KB
>>> and 4KB page sizes on host and guest, different memory device
>>> backends like normal, transparent huge page and HugeTLB, plus
>>> migration.
>>
>> Perfect. A note that hugetlbfs isn't fully suppo
On Wed, Dec 01, 2021 at 03:54:27PM +0800, Rao, Lei wrote:
> We found that the QIO channel coroutine could not be awakened in some
> corner cases during our stress test for COLO.
> The patch fixes as follow:
> #0 0x7fad72e24bf6 in __ppoll (fds=0x5563d75861f0, nfds=1,
> timeout
-Original Message-
From: Daniel P. Berrangé
Sent: Wednesday, December 1, 2021 5:11 PM
To: Rao, Lei
Cc: Zhang, Chen ; ebl...@redhat.com;
vsement...@virtuozzo.com; kw...@redhat.com; hre...@redhat.com;
qemu-bl...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [PATCH] QIO: Add force_quit
On Tue, 30 Nov 2021 09:21:58 -0800
Ben Widawsky wrote:
> On 21-11-30 13:09:56, Jonathan Cameron wrote:
> > On Mon, 29 Nov 2021 18:28:43 +
> > Alex Bennée wrote:
> >
> > > Ben Widawsky writes:
> > >
> > > > On 21-11-26 12:08:08, Alex Bennée wrote:
> > > >>
> > > >> Ben Widawsky w
On Tue, Nov 30, 2021 at 06:40:49PM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 30, 2021 at 01:45:10PM +, Stefan Hajnoczi wrote:
> > Packed Virtqueues wrap used_idx instead of letting it run freely like
> > Split Virtqueues do. If the used ring wraps more than once there is no
> > way to comp
On Wed, Dec 01, 2021 at 09:48:31AM +, Rao, Lei wrote:
>
>
> -Original Message-
> From: Daniel P. Berrangé
> Sent: Wednesday, December 1, 2021 5:11 PM
> To: Rao, Lei
> Cc: Zhang, Chen ; ebl...@redhat.com;
> vsement...@virtuozzo.com; kw...@redhat.com; hre...@redhat.com;
> qemu-bl..
On 12/1/21 00:01, Fabiano Rosas wrote:
These tests ensure that our emulation for these cpus is not completely
broken and we can at least run OpenBIOS on them.
$ make check-avocado AVOCADO_TESTS=../tests/avocado/ppc_74xx.py
Signed-off-by: Fabiano Rosas
Reviewed-by: Willian Rampazzo
---
Note th
First patch extends the ppc64 tests as we used them before the
conversion to meson.
The other patches improve the usage of the qtests with target
binaries that have a reduced set of machines (since this is
possible now e.g. by using the --with-devices-=... config
switch).
Thomas Huth (4):
tests
For the upcoming patches, we will need a way to gets a list with all
available machine types. Refactor the qtest_cb_for_every_machine()
to split the related code out into a separate new function, and
gather the aliases of the various machine types, too.
Signed-off-by: Thomas Huth
---
tests/qtest
The 'xlnx-can-test' and the 'fuzz-xlnx-dp-test' need the "xlnx-zcu102"
machine and thus should only be built and run if CONFIG_XLNX_ZYNQMP_ARM
is enabled.
Signed-off-by: Thomas Huth
---
tests/qtest/meson.build | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/tests/qtest/meso
The ppc64 target is a superset of the 32-bit target, so we should
include the tests here, too. This used to be done in the past already,
but it got lost during the conversion to meson.
Fixes: a2ce7dbd91 ("meson: convert tests/qtest to meson")
Signed-off-by: Thomas Huth
---
tests/qtest/meson.buil
It is nowadays possible to build QEMU with a reduced set of machines
in each binary. However, the qtests still hard-code the expected
machines and fail if the binary does not feature the required machine.
Let's get a little bit more flexible here: Add a function that can be
used to query whether a
* Juan Quintela (quint...@redhat.com) wrote:
> "Dr. David Alan Gilbert" wrote:
> > * Juan Quintela (quint...@redhat.com) wrote:
> >> Signed-off-by: Juan Quintela
> >
> > Can you explain a bit more what's going on here?
>
> Sorry.
>
> Until patch 20, we have what we had always have:
>
> pages t
Jonathan Cameron writes:
> On Tue, 30 Nov 2021 09:21:58 -0800
> Ben Widawsky wrote:
>
>> On 21-11-30 13:09:56, Jonathan Cameron wrote:
>> > On Mon, 29 Nov 2021 18:28:43 +
>> > Alex Bennée wrote:
>> >
>> > > Ben Widawsky writes:
>> > >
>> > > > On 21-11-26 12:08:08, Alex Bennée wrot
On Tue, Nov 30, 2021 at 11:20:57AM +, Stefan Hajnoczi wrote:
Adaptive polling measures the execution time of the polling check plus
handlers called when a polled event becomes ready. Handlers can take a
significant amount of time, making it look like polling was running for
a long time when i
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
* Daniel P. Berrangé (berra...@redhat.com) wrote:
On Fri, Nov 26, 2021 at 04:31:53PM +0100, Li Zhang wrote:
When doing live migration with multifd chann
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
>
> On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
> > * Li Zhang (lizh...@suse.de) wrote:
> > > On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
> > > > * Daniel P. Berrangé (berra...@redhat.com) wrote:
> > > > > On Fri, Nov 26, 202
On Tue, 30 Nov 2021 05:05:09 +0900,
Peter Maydell wrote:
>
> The qemu-common.h header is not supposed to be included from any
> other header files, only from .c files (as documented in a comment at
> the start of it).
>
> Nothing actually relies on target/rx/cpu.h including it, so we can
> just d
On Mon, Nov 29, 2021 at 12:05 AM Frédéric Pétrot
wrote:
>
> lwu and ld are functionally close to the other loads, but were after the
> stores in the source file.
> Similarly, xor was away from or and and by two arithmetic functions, while
> the immediate versions were nicely put together.
> This p
On 01/12/2021 04:51, Cédric Le Goater wrote:
The ISO is too big for quick tests. Isn't there a minimum initrd ? can
we build a
builroot-like image for FreeBSD ?
FreeBSD doesn't use initrd. Its bootloader loads kernel modules directly
from disk (unfortunately, it doesn't work on PowerNV).
B
On 11/29/21 21:55, Peter Maydell wrote:
> softmmu/rtc.c defines two public functions: qemu_get_timedate() and
> qemu_timedate_diff(). Currently we keep the prototypes for these in
> qemu-common.h, but most files don't need them. Move them to their
> own header, a new include/sysemu/rtc.h.
>
> Si
On 11/29/21 21:05, Peter Maydell wrote:
> Peter Maydell (4):
> include/hw/i386: Don't include qemu-common.h in .h files
> target/hexagon/cpu.h: don't include qemu-common.h
> target/rx/cpu.h: Don't include qemu-common.h
> hw/arm: Don't include qemu-common.h unnecessarily
Reviewed-by: Phili
On 11/30/21 18:32, Peter Maydell wrote:
> The calculation of the length of TLB range invalidate operations
> in tlbi_aa64_range_get_length() is incorrect in two ways:
> * the NUM field is 5 bits, but we read only 4 bits
> * we miscalculate the page_shift value, because of an
>off-by-one error
On 11/30/21 20:52, David Gibson wrote:
On Tue, Nov 30, 2021 at 07:24:04PM -0300, Daniel Henrique Barboza wrote:
On 11/29/21 01:36, David Gibson wrote:
On Thu, Nov 25, 2021 at 12:08:13PM -0300, Daniel Henrique Barboza wrote:
The PMU is already counting cycles by calculating time elapsed in
Explicitly remove the file entries from sysfs before dropping the final
reference for symmetry reasons and for consistency with the rest of the
driver.
Signed-off-by: Johan Hovold
---
drivers/firmware/qemu_fw_cfg.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/qemu_fw_cfg.
Commit fe3c60684377 ("firmware: Fix a reference count leak.") "fixed"
a kobject leak in the file registration helper by properly calling
kobject_put() for the entry in case registration of the object fails
(e.g. due to a name collision).
This would however result in a NULL pointer dereference when
Make sure to always NUL-terminate file names retrieved from the firmware
to avoid accessing data beyond the entry slab buffer and exposing it
through sysfs in case the firmware data is corrupt.
Fixes: 75f3e8e47f38 ("firmware: introduce sysfs driver for QEMU's fw_cfg
device")
Cc: sta...@vger.kerne
An initialised kobject must be freed using kobject_put() to avoid
leaking associated resources (e.g. the object name).
Commit fe3c60684377 ("firmware: Fix a reference count leak.") "fixed"
the leak in the first error path of the file registration helper but
left the second one unchanged. This "fix
When searching for the latest umn.edu patches I stumbled upon a recently
submitted fix for a bug purportedly introduced by umn.edu:
https://lore.kernel.org/r/yazc4lbx5hrjd...@hovoldconsulting.com
The patch in question is obviously bogus, but a closer look at the
function in question revea
On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wrote:
On 11/29/21 12:20 PM, Dr. David Alan Gilbert wrote:
* Daniel P. Berrangé (berra...@redhat.com) wrote
On 11/30/21 10:41, Michal Prívozník wrote:
> On 11/30/21 09:35, Mark Cave-Ayland wrote:
>> Hi all,
>>
>> Has there been a recent change as to how square brackets are encoded
>> within QOM names? I noticed that the output has changed here in the
>> "info qom-tree" output in qemu-system-m68k for the
On Wed, Dec 01, 2021 at 02:42:04PM +0100, Li Zhang wrote:
>
> On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
> > On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
> > > On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
> > > > * Li Zhang (lizh...@suse.de) wrote:
> > > > > On 11/29/21 12:20
On 12/1/21 3:09 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 02:42:04PM +0100, Li Zhang wrote:
On 12/1/21 1:22 PM, Daniel P. Berrangé wrote:
On Wed, Dec 01, 2021 at 01:11:13PM +0100, Li Zhang wrote:
On 11/29/21 3:50 PM, Dr. David Alan Gilbert wrote:
* Li Zhang (lizh...@suse.de) wro
On Wed, Dec 1, 2021 at 01:19 Richard Henderson
wrote:
> On 11/30/21 9:47 PM, Eduardo Habkost wrote:
> > * MAINTAINERS: Change my email address (Eduardo Habkost)
> >
> > Eduardo Habkost (1):
> >MAINTAINERS: Change my email address
> >
> > MAINTAINERS | 12 ++--
> > 1 file changed, 6
01.12.2021 12:48, Rao, Lei wrote:
-Original Message-
From: Daniel P. Berrangé
Sent: Wednesday, December 1, 2021 5:11 PM
To: Rao, Lei
Cc: Zhang, Chen ; ebl...@redhat.com;
vsement...@virtuozzo.com; kw...@redhat.com; hre...@redhat.com; qemu-bl...@nongnu.org;
qemu-devel@nongnu.org
Subje
Hi,
In this new version the most significant change is in patch 6,
where a new hflag allows us to not call the instruction helper
inside translate.c unless we're absolutely certain that there
is an instruction count event being sampled and active in the
PMU. This change turned out to be a big boos
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample,
PMUEventType. This enum represents a Perf event that is being sampled by
a specific counter 'sprn'. Events that aren't available (i.e. no event
was set in MMCR1) wi
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert will occur. This alert
can trigger
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- MMCR0 reg initial value is set to 0x8000 (MMCR0_FC set) to avoid
having to spin the PMU right at system init;
- to retrieve the events that are being profiled, pmc_get_event() will
From: Gustavo Romero
Following up the rfebb implementation, this patch adds the EBB exception
support that are triggered by Performance Monitor alerts. This exception
occurs when an enabled PMU condition or event happens and both MMCR0_EBE
and BESCR_PME are set.
The supported PM alerts will cons
Calling pmu_update_cycles() on every PMC read/write operation ensures
that the values being fetched are up to date with the current PMU state.
In theory we can get away by just trapping PMCs reads, but we're going
to trap PMC writes to deal with counter overflow logic later on. Let's
put the requ
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The followin
MMCR1 determines the events to be sampled by the PMU. Updating the
counters at every MMCR1 write ensures that we're not sampling more
or less events by looking only at MMCR0 and the PMCs.
It is worth noticing that both the Book3S PowerPC PMU, and this IBM
Power8+ PMU that we're modeling, also uses
The current logic is only considering event-based exceptions triggered
by the performance monitor. This is true now, but we might want to add
support for external event-based exceptions in the future.
Let's make it a bit easier to do so by adding the bit logic that would
happen in case we were dea
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions (Perf
event PM_INST_CMPL) by counting the amount of instructions translated in
On [2021 Nov 29] Mon 17:44:37, Peter Maydell wrote:
> On Wed, 24 Nov 2021 at 10:16, Francisco Iglesias
> wrote:
> >
> > Add an interface for controlling DMA models that are reused with other
> > models. This allows a controlling model to start transfers through the
> > DMA while reusing the DMA's
Implement the DMA control interface for allowing direct control of DMA
operations from inside peripheral models embedding (and reusing) the
Xilinx CSU DMA.
Signed-off-by: Francisco Iglesias
---
hw/dma/xlnx_csu_dma.c | 32
include/hw/dma/xlnx_csu_dma.h |
Connect Versal's PMC SLCR (system-level control registers) model.
Signed-off-by: Francisco Iglesias
---
hw/arm/xlnx-versal.c | 17 +
include/hw/arm/xlnx-versal.h | 6 ++
2 files changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index
Add a model of Xilinx Versal's OSPI flash memory controller.
Signed-off-by: Francisco Iglesias
---
hw/ssi/meson.build|1 +
hw/ssi/xlnx-versal-ospi.c | 1892 +
include/hw/ssi/xlnx-versal-ospi.h | 86 ++
3 files changed, 1979 insert
Add support for Micron Xccela flash mt35xu01g.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/block/m25p80.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index b77503dc84..c6bf3c6bfa 100644
--- a/hw/block/m25p80.c
+++ b/hw/
Add a model of Versal's PMC SLCR (system-level control registers).
Signed-off-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Acked-by: Edgar E. Iglesias
---
hw/misc/meson.build|5 +-
hw/misc/xlnx-versal-pmc-iou-slcr.c | 1445
Add in the missing includes in the header for being able to build the DMA
model when reusing it.
Signed-off-by: Francisco Iglesias
Reviewed-by: Peter Maydell
---
include/hw/dma/xlnx_csu_dma.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma
Connect the OSPI flash memory controller model (including the source and
destination DMA).
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 88
include/hw/arm/xlnx-versal.h | 20 ++
2 files c
Connect Micron Xccela mt35xu01g flashes to the OSPI flash memory
controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal
An option on real hardware when embedding a DMA engine into a peripheral
is to make the peripheral control the engine through a custom DMA control
(hardware) interface between the two. Software drivers in this scenario
configure and trigger DMA operations through the controlling peripheral's
regist
List myself as maintainer for the Xilinx Versal OSPI controller.
Signed-off-by: Francisco Iglesias
Reviewed-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7543eb4d59..e52cc94840 100644
--- a/MAINTAINERS
+++ b/MAINT
Also, since being the author, list myself as maintainer for the file.
Signed-off-by: Francisco Iglesias
---
MAINTAINERS| 1 +
docs/devel/dma-ctrl-if.rst | 320 +
docs/devel/index.rst | 1 +
3 files changed, 322 insertions(+)
Hi,
This series attempts to add support for Xilinx Versal's PMC SLCR
(system-level control registers) and OSPI flash memory controller to
Xilinx Versal virt machine.
The series start with adding a model of Versal's PMC SLCR and connecting
the model to the Versal virt machine. The series then adds
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 6.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu-project.org/qemu-6.2.0-rc3.tar.xz
http://downl
The instructions mtfsf, mtfsfi and mtfsb1, when called, fail to set the FI
bit (bit 46 in the FPSCR) and can set to 1 the reserved bit 52 of the
FPSCR, as reported in https://gitlab.com/qemu-project/qemu/-/issues/266
(although the bug report is only for mtfsf, the bug applies to mtfsfi and
mtfsb1 a
mtfsf, mtfsfi and mtfsb1 instructions call helper_float_check_status
after updating the value of FPSCR, but helper_float_check_status
checks fp_status and fp_status isn't updated based on FPSCR and
since the value of fp_status is reset earlier in the instruction,
it's always 0.
Because of this hel
This commit fixes the difference reported in the bug in the reserved
bit 52, it does this by adding this bit to the mask of bits to not be
directly altered in the ppc_store_fpscr function (the hardware used to
compare to QEMU was a Power9).
The bits 0 to 27 were also added to the mask, as they are
Added tests for the mtfsf to check if FI bit of FPSCR is being set
and if exception calls are being made correctly.
Signed-off-by: Lucas Mateus Castro (alqotel)
---
tests/tcg/ppc64/Makefile.target | 1 +
tests/tcg/ppc64le/Makefile.target | 1 +
tests/tcg/ppc64le/mtfsf.c | 61
QEMU TLS macros must be used to make TLS variables safe with coroutines.
Signed-off-by: Stefan Hajnoczi
---
util/async.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/util/async.c b/util/async.c
index 6f6717a34b..ddd9f24419 100644
--- a/util/async.c
+++ b/util/
RCU may be used from coroutines. Standard __thread variables cannot be
used by coroutines. Use the coroutine TLS macros instead.
Signed-off-by: Stefan Hajnoczi
---
include/qemu/rcu.h | 7 ---
tests/unit/rcutorture.c| 10 +-
tests/unit/test-rcu-list.c | 4 ++--
util/rcu.
qemu_mutex_iothread_locked() may be used from coroutines. Standard
__thread variables cannot be used by coroutines. Use the coroutine TLS
macros instead.
Signed-off-by: Stefan Hajnoczi
---
softmmu/cpus.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/softmmu/cpus.c b
On 211201 1537, dhbbb wrote:
> Hello Alex，
> Thanks for your kind reply,it really helped me a lot! I am more
> familiar with AFL than libfuzzer，and i noticed that you said "This
> minimal init/exec interface is also supported by other fuzzers, such
> as AFL[++]".But your project seems to be highly
This patch series solves the coroutines TLS problem. Coroutines re-entered from
another thread sometimes see stale TLS values. This happens because compilers
may cache values across yield points, so a value from the previous thread will
be used when the coroutine is re-entered in another thread.
S
Compiler optimizations can cache TLS values across coroutine yield
points, resulting in stale values from the previous thread when a
coroutine is re-entered by a new thread.
Serge Guelton developed an __attribute__((noinline)) wrapper and tested
it with clang and gcc. I formatted his idea accordin
On 12/1/21 17:38, Lucas Mateus Castro (alqotel) wrote:
The instructions mtfsf, mtfsfi and mtfsb1, when called, fail to set the FI
bit (bit 46 in the FPSCR) and can set to 1 the reserved bit 52 of the
FPSCR, as reported in https://gitlab.com/qemu-project/qemu/-/issues/266
(although the bug report
1 - 100 of 142 matches
Mail list logo
