> -Original Message-
> From: Jason Wang
> Sent: Monday, November 1, 2021 11:46 AM
> To: Zhang, Chen
> Cc: qemu-dev ; Markus Armbruster
> ; Li Zhijian
> Subject: Re: [PATCH V5 1/3] net/filter: Optimize transfer protocol for filter-
> mirror/redirector
>
> On Fri, Oct 29, 2021 at 4:08 P
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case for SGX numa info
with 'info numa' command in the monitor.
Signed-off-by: Yang Zhong
---
hw/core/numa.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 510d096a88..1aa05dcf42 100644
--- a/hw/core/numa.c
The basic SGX patches were merged into Qemu release, the left NUMA
function for SGX should be enabled. The patch1 implemented the SGX NUMA
ACPI to enable NUMA in the SGX guest. Since Libvirt need detailed host
SGX EPC sections info to decide how to allocate EPC sections for SGX NUMA
guest, the SGXE
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180
Add the SGXEPCSection list into SGXInfo to show the multiple
SGX EPC sections detailed info, not the total size like before.
This patch can enable numa support for 'info sgx' command and
QMP interfaces. The new interfaces show each EPC section info
in one numa node. Libvirt can use QMP interface to
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong
---
docs/system/i386/sgx.rst | 31 +++
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/docs/system/i386/sgx.rst b/doc
For bare-metal SGX on real hardware, the hardware provides guarantees
SGX state at reboot. For instance, all pages start out uninitialized.
The vepc driver provides a similar guarantee today for freshly-opened
vepc instances, but guests such as Windows expect all pages to be in
uninitialized state
On Mon, Nov 1, 2021 at 12:26 PM Alistair Francis wrote:
>
> On Tue, Oct 26, 2021 at 5:01 PM Anup Patel wrote:
> >
> > The RISC-V AIA specification extends RISC-V local interrupts and
> > introduces new CSRs. This patch adds defines for the new AIA CSRs.
> >
> > Signed-off-by: Anup Patel
>
> What
29.10.2021 23:32, Eric Blake wrote:
On Thu, Oct 28, 2021 at 12:24:39PM +0200, Vladimir Sementsov-Ogievskiy wrote:
Let's detect block-size automatically if not specified by user:
If both files define cluster-size, use minimum to be more precise.
If both files don't specify cluster-size, use
From: "Rao, Lei"
This patch fixes the following:
qemu-system-x86_64: invalid runstate transition: 'shutdown' -> 'running'
Aborted (core dumped)
The gdb bt as following:
0 __GI_raise (sig=sig@entry=6) at ../sysdeps/unix/sysv/linux/raise.c:50
1 0x7faa3d613859 in __GI_abort () at abort.c:79
2
From: "Rao, Lei"
Signed-off-by: Lei Rao
Reviewed-by: Dr. David Alan Gilbert
---
migration/colo.c | 2 +-
net/colo-compare.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/migration/colo.c b/migration/colo.c
index 79fa1f6619..616dc00af7 100644
--- a/migration/colo.c
++
Changes since v1:
--Move the s->rp_state.from_dst_file = NULL behind qemu_close().
The series of patches include:
Fixed some bugs of qemu crash and segment fault.
Optimized the function of fill_connection_key.
Remove some unnecessary code to improve COLO.
Rao, Lei
From: "Rao, Lei"
The GDB statck is as follows:
Program terminated with signal SIGSEGV, Segmentation fault.
0 object_class_dynamic_cast (class=0x55c8f5d2bf50, typename=0x55c8f2f7379e
"qio-channel") at qom/object.c:832
if (type->class->interfaces &&
[Current thread is 1 (Thread 0x7f756e9
From: "Rao, Lei"
After the live migration, the related fd will be cleanup in
migration_incoming_state_destroy(). So, the qemu_close()
in colo_process_incoming_thread is not necessary.
Signed-off-by: Lei Rao
---
migration/colo.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/migration/
From: "Rao, Lei"
This patch fixed as follows:
Thread 1 (Thread 0x7f34ee738d80 (LWP 11212)):
#0 __pthread_clockjoin_ex (threadid=139847152957184,
thread_return=0x7f30b1febf30, clockid=, abstime=,
block=) at pthread_join_common.c:145
#1 0x563401998e36 in qemu_thread_join (thread=0
From: "Rao, Lei"
When we first stated the COLO, the last-mode is as follows:
{ "execute": "query-colo-status" }
{"return": {"last-mode": "primary", "mode": "primary", "reason": "none"}}
The last-mode is unreasonable. After the patch, will be changed to the
following:
{ "execute": "query-colo-sta
From: "Rao, Lei"
Remove some unnecessary code to improve the performance of
the filter-rewriter module.
Signed-off-by: Lei Rao
Reviewed-by: Zhang Chen
---
net/colo-compare.c| 2 +-
net/colo.c| 31 ---
net/colo.h| 6 +++---
net/filter-r
On Sun, Oct 31, 2021 at 7:59 PM Juan Quintela wrote:
>
> Eugenio Pérez wrote:
> > As qemu guidelines:
> > Unless a pointer is used to modify the pointed-to storage, give it the
> > "const" attribute.
> >
> > In the particular case of iova_tree_find it allows to enforce what is
> > requested by it
29.10.2021 23:44, Eric Blake wrote:
On Thu, Oct 28, 2021 at 12:24:40PM +0200, Vladimir Sementsov-Ogievskiy wrote:
Allow compare only top images of backing chains. This is useful to
Allow the comparison of only the top image of backing chains.
compare images with same backing file or to compa
ch-for-6.2-pull-request
for you to fetch changes up to c3f93230df9ad1d3260f03655faa8f9f23c90a52:
hw/input/lasips2: QOM'ify the Lasi PS/2 (2021-10-31 21:05:40 +0100)
Trivial patches branch pull r
From: Markus Armbruster
I noticed -cpu help printing enough trailing spaces to make the output
at least 84 characters wide. Looks ugly unless the terminal is wider.
Ugly or not, trailing spaces are stupid.
The culprit is this line in x86_cpu_list_entry():
qemu_printf("x86 %-20s %-58s\n",
From: Philippe Mathieu-Daudé
We want to use the OBJECT_DECLARE_SIMPLE_TYPE() macro to QOM'ify
this device in the next commit. To make its review simpler, as a
first step move the LASIPS2State and LASIPS2Port declarations to
'hw/input/lasips2.h'
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by:
From: Philippe Mathieu-Daudé
Hardware emulated models don't belong to the TCG MAINTAINERS
section. Move them to the 'HP-PARISC Machines' section.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Helge Deller
Message-Id: <20211004083835.3802961-1-f4...@amsat.or
From: Yanan Wang
The expected output string from cpu_slot_to_string() ought to be
like "socket-id: *, die-id: *, core-id: *, thread-id: *", so add
the missing ", " before "die-id". This affects the readability
of the error message.
Fixes: 176d2cda0d ("i386/cpu: Consolidate die-id validity in smp
From: Philippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Message-Id: <20210920064048.2729397-4-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/hppa/lasi.c | 10 +-
hw/input/lasips2.c | 38 ---
From: Philippe Mathieu-Daudé
Artist is another device, this one is the Lasi PS/2.
Rename the functions accordingly.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Damien Hedde
Message-Id: <20210920064048.2729397-2-f4...@amsat.org>
Signed-off-by: Laurent Vivier
---
hw/input/lasips2.c | 8
When vhost-user vdpa client suspend, backend may close all resources,
VQ notifier mmap address become invalid, restore MR which contains
the invalid address is wrong. vdpa client will set VQ notifier after
reconnect.
This patch removes VQ notifier restore and related flags to avoid reusing
invalid
When vDPA applicaiton in client mode shutdown, unmapped VQ notifier
might being accessed by vCPU thread under high tx traffic, it will
crash VM in rare conditon. This patch try to fix it with better RCU
sychronization of new flatview.
v2: no RCU draining on vCPU thread
v3: minor fix on coding styl
When vhost-user device cleanup is executed and un-mmaps notifier
address, VM cpu thread writing the notifier fails by accessing invalid
address error.
To avoid this concurrent issue, call RCU and wait for a memory flatview
update, then un-mmap notifiers in callback.
Fixes: 44866521bd6e ("vhost-us
On Thu, 28 Oct 2021 22:32:09 +1100
Gavin Shan wrote:
> On 10/28/21 2:40 AM, Igor Mammedov wrote:
> > On Wed, 27 Oct 2021 13:29:58 +0800
> > Gavin Shan wrote:
> >
> >> The empty NUMA nodes, where no memory resides, aren't exposed
> >> through ACPI SRAT table. It's not user preferred behaviour
Hi Simon,
this seems a great endeavor. I'd like to better understand the scope of it.
Is it to be used as part of what could become a U-Boot entry ABI scheme? By
that I mean giving some fixed aspects
to U-Boot entry while letting boards to have flexibility (say for instance
that the first 5 archi
On Mon, Nov 1, 2021 at 4:34 AM Jason Wang wrote:
>
> On Fri, Oct 29, 2021 at 10:16 PM Eugenio Pérez wrote:
> >
> > The -1 assumes that all devices with no cvq have an spare vq allocated
> > for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This may not be the
> > case, and the device may have
On Tue, Oct 26, 2021 at 2:43 PM Anup Patel wrote:
>
> We should be returning illegal instruction trap when RV64 HS-mode tries
> to access RV32 HS-mode CSR.
>
> Fixes: d6f20dacea51 ("target/riscv: Fix 32-bit HS mode access permissions")
> Signed-off-by: Anup Patel
> Reviewed-by: Alistair Francis
On Sun, Oct 31, 2021 at 10:47 PM Michael S. Tsirkin wrote:
>
> On Fri, Oct 29, 2021 at 04:16:08PM +0200, Eugenio Pérez wrote:
> > The -1 assumes that all devices with no cvq have an spare vq allocated
> > for them, but with no offer of VIRTIO_NET_F_CTRL_VQ. This may not be the
> > case, and the de
On Fri, Oct 29, 2021 at 8:41 PM Eugenio Pérez wrote:
>
> This series enable shadow virtqueue (SVQ) for vhost-vdpa devices. This
> is intended as a new method of tracking the memory the devices touch
> during a migration process: Instead of relay on vhost device's dirty
> logging capability, SVQ in
On Mon, Nov 01, 2021 at 10:03:19AM +0100, Eugenio Perez Martin wrote:
> On Sun, Oct 31, 2021 at 10:47 PM Michael S. Tsirkin wrote:
> >
> > On Fri, Oct 29, 2021 at 04:16:08PM +0200, Eugenio Pérez wrote:
> > > The -1 assumes that all devices with no cvq have an spare vq allocated
> > > for them, but
On Wed, Oct 27, 2021 at 11:59:45AM +0200, Laurent Vivier wrote:
> If the guest driver doesn't support the STANDBY feature, by default
> we keep the virtio-net device and don't hotplug the VFIO device,
> but in some cases, user can prefer to use the VFIO device rather
> than the virtio-net one. We c
This patch gives an introduction to the LoongArch target.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
MAINTAINERS | 5
target/loongarch/README | 76 +
2 files changed, 81 insertions(+)
Hi all,
This series only support linux-user emulation.
More about LoongArch at: https://github.com/loongson/
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
Patches need review:
* 0002-target-loongarch-Add-core-definition.patch
* 0016-target-loongarch-Add-disasse
This includes:
- F{ADD/SUB/MUL/DIV}.{S/D}
- F{MADD/MSUB/NMADD/NMSUB}.{S/D}
- F{MAX/MIN}.{S/D}
- F{MAXA/MINA}.{S/D}
- F{ABS/NEG}.{S/D}
- F{SQRT/RECIP/RSQRT}.{S/D}
- F{SCALEB/LOGB/COPYSIGN}.{S/D}
- FCLASS.{S/D}
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
--
This includes:
- ADD.{W/D}, SUB.{W/D}
- ADDI.{W/D}, ADDU16ID
- ALSL.{W[U]/D}
- LU12I.W, LU32I.D LU52I.D
- SLT[U], SLT[U]I
- PCADDI, PCADDU12I, PCADDU18I, PCALAU12I
- AND, OR, NOR, XOR, ANDN, ORN
- MUL.{W/D}, MULH.{W[U]/D[U]}
- MULW.D.W[U]
- DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
- ANDI, ORI, XORI
Review
This patch adds main translation routines and
basic functions for translation.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/helper.h| 9 +++
target/loongarch/op_helper.c | 22 ++
target/loongarch/translate.c | 160 +
This patch adds target state header, target definitions
and initialization routines.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/cpu-param.h | 19 +++
target/loongarch/cpu.c | 352 +++
t
This includes:
- EXT.W.{B/H}
- CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
- BYTEPICK.{W/D}
- REVB.{2H/4H/2W/D}
- REVH.{2W/D}
- BITREV.{4B/8B}, BITREV.{W/D}
- BSTRINS.{W/D}, BSTRPICK.{W/D}
- MASKEQZ, MASKNEZ
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loonga
This includes:
- FMOV.{S/D}
- FSEL
- MOVGR2FR.{W/D}, MOVGR2FRH.W
- MOVFR2GR.{S/D}, MOVFRH2GR.S
- MOVGR2FCSR, MOVFCSR2GR
- MOVFR2CF, MOVCF2FR
- MOVGR2CF, MOVCF2GR
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/fpu_helper.c|
This includes:
- LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
- LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
- LDPTR.{W/D}, STPTR.{W/D}
- PRELD
- LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
- DBAR, IBAR
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/helpe
This includes:
- LL.{W/D}, SC.{W/D}
- AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].{W/D}
- AM{MAX/MIN}[_DB].{WU/DU}
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/insn_trans/trans_atomic.c | 133 +
target/loongarch/i
This includes:
- FCMP.cond.{S/D}
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/fpu_helper.c| 60
target/loongarch/helper.h| 9 +
target/loongarch/insn_trans/trans_fcmp.c
This includes:
- FCVT.S.D, FCVT.D.S
- FFINT.{S/D}.{W/L}, FTINT.{W/L}.{S/D}
- FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
- FRINT.{S/D}
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/fpu_helper.c| 393 +++
tar
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
accel/tcg/user-exec.c | 15 +++
linux-user/loongarch64/signal.c| 163 +
linux-user/loongarch64/target_signal.h | 30 ++
3 files changed, 208 insertions(+)
create mode 100644 l
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
configure | 5 ++
linux-user/loongarch64/cpu_loop.c | 98 +
linux-user/loongarch64/target_cpu.h | 35 +
3 files changed, 138 insertions(+)
create mode 100644 lin
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/insn_trans/trans_shift.c | 131 +++
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
include/elf.h | 2 ++
linux-user/elfload.c| 58 +
linux-user/loongarch64/target_elf.h | 14 +
3 files changed, 74 insertions(+)
create mode 100644 linux-us
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
tests/tcg/configure.sh | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
index 1f985cc..d8f677d 100755
--- a/tests/tcg/configure.sh
+++ b/tests/tcg/configure
This includes:
- CRC[C].W.{B/H/W/D}.W
- SYSCALL
- BREAK
- ASRT{LE/GT}.D
- RDTIME{L/H}.W, RDTIME.D
- CPUCFG
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/helper.h | 4 ++
target/loongarch/insn_trans/trans_extra.c | 87 +
This includes:
- sockbits.h
- target_errno_defs.h
- target_fcntl.h
- termbits.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/sockbits.h | 1 +
linux-user/loongarch64/target_errno_defs.h | 7 +++
linux-user/loongarch64/target_fcntl.h | 12 ++
Base-on: <20210925173032.2434906-30-...@xen0n.name>
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
accel/tcg/user-exec.c | 64 ---
1 file changed, 61 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.
This patch adds loongarch64 linux-user default configs file.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
configs/targets/loongarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 configs/targets/loongarch64-linux-user.ma
Base-on: <20210925173032.2434906-29-...@xen0n.name>
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/host/loongarch64/hostdep.h | 23
linux-user/host/loongarch64/safe-syscall.inc.S | 80 ++
2 files changed, 103 insertions(+)
create mo
This includes:
- FLD.{S/D}, FST.{S/D}
- FLDX.{S/D}, FSTX.{S/D}
- FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/insn_trans/trans_fmemory.c | 187
target/loongarch/insns.dec
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 7d0aee6769..eb425d74d2 100644
-
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/host/loongarch64/hostdep.h | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 linux-user/host/loongarch64/hostdep.h
diff --git a/linux-user/host/loongarch64/hostdep.h
b/linux-user/host/loongarch64/hostdep.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/target_structs.h | 49 +
1 file changed, 49 insertions(+)
create mode 100644 linux-user/loongarch64/target_structs.h
diff --git a/linux-user/loongarch64/target_structs.h
b/linux-use
On Fri, Oct 29, 2021 at 02:17:43PM +, Jag Raman wrote:
> Hi Stefan,
>
> > On Oct 27, 2021, at 11:17 AM, Stefan Hajnoczi wrote:
> >
> > On Mon, Oct 11, 2021 at 01:31:07AM -0400, Jagannathan Raman wrote:
> >> diff --git a/hw/remote/Kconfig b/hw/remote/Kconfig
> >> index 08c16e235f..f9e512d44a
When pc is written, it is sign-extended to fill the widest supported XLEN.
Signed-off-by: LIU Zhiwei
---
target/riscv/translate.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1d57bc97b5..7d7
When sew <= 32bits, not need to extend scalar reg.
When sew > 32bits, if xlen is less that sew, we should sign extend
the scalar register, except explicitly specified by the spec.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
target/riscv/vector_helper.c
This patch adds support for disassembling via option '-d in_asm'.
Acked-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
include/disas/dis-asm.h | 2 +
meson.build | 1 +
target/loongarch/disas.c | 919
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
scripts/qemu-binfmt-conf.sh | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 7de996d..da6a937 100755
--- a/scripts/qemu
In this patch set, we process the pc reigsters writes,
gdb reads and writes, and address calculation under
different UXLEN settings.
LIU Zhiwei (13):
target/riscv: Sign extend pc for different ol
target/riscv: Extend pc for runtime pc write
target/riscv: Ignore the pc bits above XLEN
targe
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 8
target/riscv/internals.h| 1 +
target/riscv/vector_helper.c| 54 +
3 files changed, 46 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_r
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
target/loongarch/insn_trans/trans_branch.c | 85 ++
target/loongarch/insns.decode
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 20 ++--
target/riscv/insn_trans/trans_rvf.c.inc | 21 -
target/riscv/insn_trans/trans_rvi.c.inc | 21 ++---
3 files changed, 24 insertions(+), 38 deletions(-)
diff --git a
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h | 2 ++
target/riscv/helper.h | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
target/riscv/vector_helper.c| 19 +++
4 files changed, 20 insertions(+), 7 deletions(-)
d
We should disable '__BITS_PER_LONG' at [1] before run gensyscalls.sh
[1] arch/loongarch/include/uapi/asm/bitsperlong.h
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
linux-user/loongarch64/syscall_nr.h | 312
linux-user/loongarch64/target_syscall
This patch adds build loongarch-linux-user target support.
Reviewed-by: Richard Henderson
Signed-off-by: Song Gao
Signed-off-by: Xiaojuan Yang
---
meson.build | 2 +-
target/loongarch/meson.build | 19 +++
target/meson.build | 1 +
3 files changed,
Only check the range that has passed the address translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 09e76229bc..535420ee66 100644
--- a/t
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hit zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c| 20 +---
target/riscv/cpu.h
Signed-off-by: LIU Zhiwei
---
target/riscv/gdbstub.c | 73 +++---
1 file changed, 54 insertions(+), 19 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 23429179e2..15abbbdb54 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv
Signed-off-by: LIU Zhiwei
---
target/riscv/csr.c | 6 --
target/riscv/insn_trans/trans_rvi.c.inc | 2 +-
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9f41954894..471c10acf6 100644
--- a/target/riscv/csr.c
+++
After excpetion return, we should give a xlen view of context in new
priveledge, including the general registers, pc, and CSRs.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 1 +
.../riscv/insn_trans/trans_privileged.c.inc | 2 ++
target/riscv/op_helper.c
As pc will be written by the xepc in exception return, just ignore
pc in translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 4 ++--
target/riscv/insn_trans/trans_privileged.c.inc | 7 ++-
target/riscv/op_helper.c | 4 ++--
3 file
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 01da065710..ed042f7bb9 100644
--- a/target/riscv/insn_trans/trans_rvv.
In sev_add_kernel_loader_hashes, the sizes of structs are known at
compile-time, so calculate needed padding at compile-time.
No functional change intended.
Signed-off-by: Dov Murik
---
target/i386/sev.c | 28 ++--
1 file changed, 18 insertions(+), 10 deletions(-)
diff
Tom Lendacky and Brijesh Singh reported two issues with launching SEV
guests with the -kernel QEMU option when an old [1] or wrongly configured [2]
OVMF images are used.
The fixes in patches 1 and 2 allow such guests to boot by skipping the
kernel/initrd/cmdline hashes addition to the initial gues
ping?
On 10/27/21 07:06, Philippe Mathieu-Daudé wrote:
> Sensors models are listed in the 'Misc devices' category.
> Move them to their own category.
>
> Reviewed-by: Cédric Le Goater
> Reviewed-by: Hao Wu
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> v2: Only include hw/sensor/, removed AER
Commit cff03145ed3c ("sev/i386: Introduce sev_add_kernel_loader_hashes
for measured linux boot", 2021-09-30) introduced measured direct boot
with -kernel, using an OVMF-designated hashes table which QEMU fills.
However, if OVMF doesn't designate such an area, QEMU would completely
abort the VM lau
Build failed running the 'clang-user' job:
TESTlinux-test on sh4
../linux-user/syscall.c:10373:34: runtime error: member access within
misaligned address 0x0048af34 for type 'struct linux_dirent64',
which requires 8 byte alignment
0x0048af34: note: pointer points here
00 00 00 00 0
On 28/10/2021 11:41, Dov Murik wrote:
>
>
> On 27/10/2021 22:43, Brijesh Singh wrote:
>> Hi Dov,
>>
>> Sorry for coming a bit late on it but I am seeing another issue with
>> this patch. The hash build logic looks for a SEV_HASH_TABLE_RV_GUID in
>> the GUID list. If found, it uses the base add
Commit cff03145ed3c ("sev/i386: Introduce sev_add_kernel_loader_hashes
for measured linux boot", 2021-09-30) introduced measured direct boot
with -kernel, using an OVMF-designated hashes table which QEMU fills.
However, no checks are performed on the validity of the hashes area
designated by OVMF.
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
+static void gen_set_pc(DisasContext *ctx, target_ulong dest)
+{
+TCGv t = tcg_constant_tl(dest);
+switch (get_ol(ctx)) {
+case MXL_RV32:
+tcg_gen_ext32s_tl(cpu_pc, t);
Don't compute with tcg to do what you can in C. Dest is constant.
A
Can this patch go via the Trivial tree?
On 10/27/21 06:32, Philippe Mathieu-Daudé wrote:
> These authors have some incorrect author email field.
>
> Acked-by: Pan Nengyuan
> Reviewed-by: Alex Chen
> Reviewed-by: Hyman Huang
> Reviewed-by: Haibin Zhang
> Signed-off-by: Philippe Mathieu-Daudé
On 10/31/21 17:43, Taylor Simpson wrote:
> Tests for
> packet semantics
> vector loads (aligned and unaligned)
> vector stores (aligned and unaligned)
> vector masked stores
> vector new value store
> maximum HVX temps in a packet
> vector operations
>
> Acked-by: Richa
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hit zero. So extend pc register
according to current xlen for these cases.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c| 20
On Fri, Oct 29, 2021 at 02:42:49PM +, Jag Raman wrote:
> > On Oct 27, 2021, at 11:40 AM, Stefan Hajnoczi wrote:
> > On Mon, Oct 11, 2021 at 01:31:08AM -0400, Jagannathan Raman wrote:
> >> diff --git a/hw/remote/vfio-user-obj.c b/hw/remote/vfio-user-obj.c
> >> new file mode 100644
> >> index 00
On Fri, Oct 29, 2021 at 02:59:02PM +, Jag Raman wrote:
>
>
> > On Oct 27, 2021, at 11:59 AM, Stefan Hajnoczi wrote:
> >
> > On Mon, Oct 11, 2021 at 01:31:09AM -0400, Jagannathan Raman wrote:
> >> @@ -94,9 +101,31 @@ static void vfu_object_set_device(Object *obj, const
> >> char *str, Error
On Fri, Oct 29, 2021 at 03:58:28PM +, Jag Raman wrote:
>
>
> > On Oct 27, 2021, at 12:05 PM, Stefan Hajnoczi wrote:
> >
> > On Mon, Oct 11, 2021 at 01:31:10AM -0400, Jagannathan Raman wrote:
> >> Find the PCI device with specified id. Initialize the device context
> >> with the QEMU PCI dev
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
The read from PC for translation is in cpu_get_tb_cpu_state, before translation.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
Could perhaps be sorted to pa
On 11/1/21 6:01 AM, LIU Zhiwei wrote:
+switch (env->misa_mxl_max) {
+case MXL_RV32:
+tmp = (uint32_t)ldl_p(mem_buf);
Signed int32_t.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 10/31/21 13:02, wangyanan (Y) wrote:
> Hi Philippe,
>
> I saw that there are some cross-build failures and a clang complain
> about this patch in your triggered CI pipeline. I believe the minor
> diff below will resolve them. If you are going to resend v2 of the
> "qdev-hotplug" patches, I woul
Hi,
On 2021/11/1 17:51, Song Gao wrote:
> Base-on: <20210925173032.2434906-30-...@xen0n.name>
> Signed-off-by: Song Gao
> Signed-off-by: Xiaojuan Yang
> ---
> accel/tcg/user-exec.c | 64
> ---
> 1 file changed, 61 insertions(+), 3 deletions(-)
W
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